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ARM: Add a base class to support usada8.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:07 -05:00
parent 64ade8316e
commit c643b1c274
4 changed files with 61 additions and 0 deletions
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15
src/arch/arm/insts/misc.cc
View file

@ -168,6 +168,21 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
std::string
RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
ss << ", ";
printReg(ss, op1);
ss << ", ";
printReg(ss, op2);
ss << ", ";
printReg(ss, op3);
return ss.str();
}
std::string
RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

18
src/arch/arm/insts/misc.hh
View file

@ -142,6 +142,24 @@ class RegRegRegImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
IntRegIndex op3;
RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1,
IntRegIndex _op2, IntRegIndex _op3) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), op3(_op3)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegOp : public PredOp
{
protected:

2
src/arch/arm/isa/operands.isa
View file

@ -102,6 +102,8 @@ def operands {{
maybePCRead, maybePCWrite),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
maybePCRead, maybePCWrite),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
maybePCRead, maybePCWrite),
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,

26
src/arch/arm/isa/templates/misc.isa
View file

@ -146,6 +146,32 @@ def template RegRegRegImmOpConstructor {{
}
}};
def template RegRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
protected:
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
IntRegIndex _op2, IntRegIndex _op3);
%(BasicExecDeclare)s
};
}};
def template RegRegRegRegOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
IntRegIndex _op3)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3)
{
%(constructor)s;
}
}};
def template RegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{