sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

ARM: Implement the mrc and mcr instructions.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 6c1b10043f
commit 625a43e7c7
1 changed files with 14 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/arch/arm/isa/insts/misc.isa
View file

@ -500,4 +500,18 @@ let {{
header_output += RegRegImmImmOpDeclare.subst(bfiIop)
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
exec_output += PredOpExecute.subst(bfiIop)
mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
{ "code": "Dest = MiscOp1;",
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mrc15Iop)
decoder_output += RegRegOpConstructor.subst(mrc15Iop)
exec_output += PredOpExecute.subst(mrc15Iop)
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
{ "code": "MiscDest = Op1;",
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mcr15Iop)
decoder_output += RegRegOpConstructor.subst(mcr15Iop)
exec_output += PredOpExecute.subst(mcr15Iop)
}};