ARM: Decode the neon instruction space.
This commit is contained in:
Gabe Black
parent
e50e6a260f
commit
85ba2a3243
3 changed files with 714 additions and 7 deletions
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@ -119,7 +119,7 @@ decode BIGTHUMB {
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0x0: decode HTOPCODE_4 {
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0x0: decode HTOPCODE_8 {
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0x0: Thumb32StoreSingle::thumb32StoreSingle();
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0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
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0x1: ThumbNeonMem::thumbNeonMem();
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}
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0x1: decode HTOPCODE_6_5 {
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0x0: LoadByteMemoryHints::loadByteMemoryHints();
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@ -144,7 +144,7 @@ decode BIGTHUMB {
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0xf: McrMrc15::mcrMrc15();
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}
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}
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0x3: WarnUnimpl::Advanced_SIMD();
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0x3: ThumbNeonData::thumbNeonData();
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default: decode LTCOPROC {
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0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStre();
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0xf: decode HTOPCODE_9_4 {
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@ -45,6 +45,716 @@
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// Floating Point operate instructions
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//
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let {{
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header_output = '''
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StaticInstPtr
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decodeNeonMem(ExtMachInst machInst);
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StaticInstPtr
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decodeNeonData(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeNeonMem(ExtMachInst machInst)
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{
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const uint32_t b = bits(machInst, 11, 8);
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const bool a = bits(machInst, 23);
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const bool l = bits(machInst, 21);
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if (l) {
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// Load instructions.
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if (a) {
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switch (b) {
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}
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// Single.
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} else {
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switch (b) {
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}
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// Multiple.
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}
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} else {
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// Store instructions.
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if (a) {
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switch (b) {
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}
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// Single.
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} else {
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switch (b) {
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}
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// Multiple.
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}
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}
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return new WarnUnimplemented("neon memory", machInst);
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}
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'''
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decoder_output += '''
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static StaticInstPtr
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decodeNeonThreeRegistersSameLength(ExtMachInst machInst)
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{
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const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
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const uint32_t a = bits(machInst, 11, 8);
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const bool b = bits(machInst, 4);
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const uint32_t c = bits(machInst, 21, 20);
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switch (a) {
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case 0x0:
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if (b) {
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if (bits(machInst, 9) == 0) {
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return new WarnUnimplemented("vhadd", machInst);
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} else {
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return new WarnUnimplemented("vhsub", machInst);
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}
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} else {
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return new WarnUnimplemented("vqadd", machInst);
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}
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case 0x1:
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if (!b) {
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return new WarnUnimplemented("vrhadd", machInst);
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} else {
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if (u) {
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switch (c) {
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case 0:
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return new WarnUnimplemented("veor", machInst);
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case 1:
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return new WarnUnimplemented("vbsl", machInst);
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case 2:
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return new WarnUnimplemented("vbit", machInst);
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case 3:
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return new WarnUnimplemented("vbif", machInst);
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}
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} else {
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switch (c) {
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case 0:
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return new WarnUnimplemented("vand (reg)", machInst);
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case 1:
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return new WarnUnimplemented("vbic (reg)", machInst);
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case 2:
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{
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const IntRegIndex n = (IntRegIndex)(
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(uint32_t)bits(machInst, 19, 16) |
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(uint32_t)(bits(machInst, 7) << 4));
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const IntRegIndex m = (IntRegIndex)(
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(uint32_t)bits(machInst, 3, 0) |
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(uint32_t)(bits(machInst, 5) << 4));
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if (n == m) {
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return new WarnUnimplemented("vmov (reg)",
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machInst);
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} else {
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return new WarnUnimplemented("vorr (reg)",
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machInst);
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}
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}
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case 3:
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return new WarnUnimplemented("vorn (reg)", machInst);
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}
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}
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}
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case 0x2:
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if (b) {
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return new WarnUnimplemented("vqsub", machInst);
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} else {
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if (bits(machInst, 9) == 0) {
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return new WarnUnimplemented("vhadd", machInst);
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} else {
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return new WarnUnimplemented("vhsub", machInst);
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}
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}
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case 0x3:
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if (b) {
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return new WarnUnimplemented("vcge (reg)", machInst);
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} else {
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return new WarnUnimplemented("vcgt (reg)", machInst);
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}
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case 0x4:
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if (b) {
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return new WarnUnimplemented("vqshl (reg)", machInst);
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} else {
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return new WarnUnimplemented("vshl (reg)", machInst);
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}
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case 0x5:
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if (b) {
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return new WarnUnimplemented("vqrshl", machInst);
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} else {
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return new WarnUnimplemented("vrshl", machInst);
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}
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case 0x6:
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if (b) {
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return new WarnUnimplemented("vmin (int)", machInst);
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} else {
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return new WarnUnimplemented("vmax (int)", machInst);
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}
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case 0x7:
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if (b) {
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return new WarnUnimplemented("vaba", machInst);
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} else {
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if (bits(machInst, 23) == 1) {
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if (bits(machInst, 6) == 1) {
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return new Unknown(machInst);
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} else {
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return new WarnUnimplemented("vabdl (int)", machInst);
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}
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} else {
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return new WarnUnimplemented("vabd (int)", machInst);
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}
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}
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case 0x8:
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if (b) {
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if (u) {
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return new WarnUnimplemented("vceq (reg)", machInst);
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} else {
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return new WarnUnimplemented("vtst", machInst);
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}
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} else {
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if (u) {
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return new WarnUnimplemented("vsub (int)", machInst);
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} else {
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return new WarnUnimplemented("vadd (int)", machInst);
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}
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}
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case 0x9:
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if (b) {
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if (u) {
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return new WarnUnimplemented("vmul (poly)", machInst);
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} else {
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return new WarnUnimplemented("vmul (int)", machInst);
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}
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} else {
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if (u) {
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return new WarnUnimplemented("vmls (int)", machInst);
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} else {
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return new WarnUnimplemented("vmla (int)", machInst);
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}
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}
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case 0xa:
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if (b) {
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return new WarnUnimplemented("vpmin (int)", machInst);
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} else {
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return new WarnUnimplemented("vpmax (int)", machInst);
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}
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case 0xb:
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if (b) {
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if (u) {
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return new Unknown(machInst);
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} else {
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return new WarnUnimplemented("vpadd (int)", machInst);
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}
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} else {
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if (u) {
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return new WarnUnimplemented("vqrdmulh", machInst);
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} else {
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return new WarnUnimplemented("vqdmulh", machInst);
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}
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}
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case 0xc:
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return new Unknown(machInst);
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case 0xd:
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if (b) {
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if (u) {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vmul (fp)", machInst);
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} else {
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return new Unknown(machInst);
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}
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} else {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vmla (fp)", machInst);
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} else {
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return new WarnUnimplemented("vmls (fp)", machInst);
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}
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}
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} else {
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if (u) {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vpadd (fp)", machInst);
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} else {
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return new WarnUnimplemented("vabd (fp)", machInst);
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}
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} else {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vadd (fp)", machInst);
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} else {
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return new WarnUnimplemented("vsub (fp)", machInst);
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}
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}
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}
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case 0xe:
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if (b) {
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if (u) {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vacge", machInst);
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} else {
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return new WarnUnimplemented("vacgt", machInst);
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}
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} else {
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return new Unknown(machInst);
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}
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} else {
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if (u) {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vcge (reg)", machInst);
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} else {
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return new WarnUnimplemented("vcgt (reg)", machInst);
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}
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} else {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vceq (reg)", machInst);
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} else {
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return new Unknown(machInst);
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}
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}
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}
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case 0xf:
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if (b) {
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if (u) {
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return new Unknown(machInst);
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} else {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vrecps", machInst);
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} else {
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return new WarnUnimplemented("vrsqrts", machInst);
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}
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}
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} else {
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if (u) {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vpmax (fp)", machInst);
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} else {
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return new WarnUnimplemented("vpmin (fp)", machInst);
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}
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} else {
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if (bits(c, 1) == 0) {
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return new WarnUnimplemented("vmax (fp)", machInst);
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} else {
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return new WarnUnimplemented("vmin (fp)", machInst);
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}
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}
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}
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}
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return new Unknown(machInst);
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}
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static StaticInstPtr
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decodeNeonOneRegModImm(ExtMachInst machInst)
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{
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const bool op = bits(machInst, 5);
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const uint32_t cmode = bits(machInst, 11, 8);
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if (op) {
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if (bits(cmode, 3) == 0) {
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if (bits(cmode, 0) == 0) {
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return new WarnUnimplemented("vmov (imm)", machInst);
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} else {
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return new WarnUnimplemented("vorr (imm)", machInst);
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}
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} else {
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if (bits(cmode, 2) == 1) {
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return new WarnUnimplemented("vmov (imm)", machInst);
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} else {
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if (bits(cmode, 0) == 0) {
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return new WarnUnimplemented("vmov (imm)", machInst);
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} else {
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return new WarnUnimplemented("vorr (imm)", machInst);
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}
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}
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}
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} else {
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if (bits(cmode, 3) == 0) {
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if (bits(cmode, 0) == 0) {
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return new WarnUnimplemented("vmvn (imm)", machInst);
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} else {
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return new WarnUnimplemented("vbic (imm)", machInst);
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}
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} else {
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if (bits(cmode, 2) == 1) {
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switch (bits(cmode, 1, 0)) {
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case 0:
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case 1:
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return new WarnUnimplemented("vmvn (imm)", machInst);
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case 2:
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return new WarnUnimplemented("vmov (imm)", machInst);
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case 3:
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return new Unknown(machInst);
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}
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return new WarnUnimplemented("vmov (imm)", machInst);
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} else {
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if (bits(cmode, 0) == 0) {
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return new WarnUnimplemented("vmvn (imm)", machInst);
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} else {
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return new WarnUnimplemented("vbic (imm)", machInst);
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}
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}
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}
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}
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return new Unknown(machInst);
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}
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static StaticInstPtr
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decodeNeonTwoRegAndShift(ExtMachInst machInst)
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{
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const uint32_t a = bits(machInst, 11, 8);
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const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
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const bool b = bits(machInst, 6);
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const bool l = bits(machInst, 7);
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switch (a) {
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case 0x0:
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return new WarnUnimplemented("vshr", machInst);
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case 0x1:
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return new WarnUnimplemented("vsra", machInst);
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case 0x2:
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return new WarnUnimplemented("vrshr", machInst);
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case 0x3:
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return new WarnUnimplemented("vrsra", machInst);
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case 0x4:
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if (u) {
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return new WarnUnimplemented("vsri", machInst);
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} else {
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return new Unknown(machInst);
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}
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case 0x5:
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if (u) {
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return new WarnUnimplemented("vsli", machInst);
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} else {
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return new WarnUnimplemented("vshl (imm)", machInst);
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}
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case 0x6:
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case 0x7:
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return new WarnUnimplemented("vqshl, vqshlu (imm)", machInst);
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case 0x8:
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if (l) {
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return new Unknown(machInst);
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} else if (u) {
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if (b) {
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return new WarnUnimplemented("vqrshrn, vqrshrun", machInst);
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} else {
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return new WarnUnimplemented("vqshrn, vqshrun", machInst);
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}
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} else {
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if (b) {
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return new WarnUnimplemented("vrshrn", machInst);
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} else {
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return new WarnUnimplemented("vshrn", machInst);
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}
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}
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case 0x9:
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if (l) {
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return new Unknown(machInst);
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} else if (b) {
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return new WarnUnimplemented("vqrshrn, vqrshrun", machInst);
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} else {
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return new WarnUnimplemented("vqshrn, vqshrun", machInst);
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}
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case 0xa:
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if (l || b) {
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return new Unknown(machInst);
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} else {
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// If the shift amount is zero, it's vmovl.
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return new WarnUnimplemented("vshll, vmovl", machInst);
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}
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case 0xe:
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case 0xf:
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if (l) {
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return new Unknown(machInst);
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} else if (a == 0xe) {
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return new WarnUnimplemented("vcvt (fixed to fp)", machInst);
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} else if (a == 0xf) {
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return new WarnUnimplemented("vcvt (fp to fixed)", machInst);
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}
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}
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return new Unknown(machInst);
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}
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static StaticInstPtr
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decodeNeonThreeRegDiffLengths(ExtMachInst machInst)
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{
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const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
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const uint32_t a = bits(machInst, 11, 8);
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switch (a) {
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case 0x0:
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return new WarnUnimplemented("vaddl", machInst);
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case 0x1:
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return new WarnUnimplemented("vaddw", machInst);
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case 0x2:
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return new WarnUnimplemented("vsubl", machInst);
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case 0x3:
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return new WarnUnimplemented("vsubw", machInst);
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case 0x4:
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if (u) {
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return new WarnUnimplemented("vraddhn", machInst);
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} else {
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return new WarnUnimplemented("vaddhn", machInst);
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}
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case 0x5:
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return new WarnUnimplemented("vabal", machInst);
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case 0x6:
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if (u) {
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return new WarnUnimplemented("vrsubhn", machInst);
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} else {
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return new WarnUnimplemented("vsubhn", machInst);
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}
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case 0x7:
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if (bits(machInst, 23)) {
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return new WarnUnimplemented("vabdl (int)", machInst);
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} else {
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return new WarnUnimplemented("vabd (int)", machInst);
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}
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case 0x8:
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return new WarnUnimplemented("vmlal (int)", machInst);
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case 0xa:
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return new WarnUnimplemented("vmlsl (int)", machInst);
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case 0x9:
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if (bits(machInst, 23) == 0) {
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if (bits(machInst, 4) == 0) {
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if (u) {
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return new WarnUnimplemented("vmls (int)", machInst);
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} else {
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return new WarnUnimplemented("vmla (int)", machInst);
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}
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} else {
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if (u) {
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return new WarnUnimplemented("vmul (poly)", machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vmul (int)", machInst);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmlal", machInst);
|
||||
}
|
||||
case 0xb:
|
||||
if (!u) {
|
||||
return new Unknown(machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmlsl", machInst);
|
||||
}
|
||||
case 0xc:
|
||||
return new WarnUnimplemented("vmull (int)", machInst);
|
||||
case 0xd:
|
||||
if (!u) {
|
||||
return new Unknown(machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmull", machInst);
|
||||
}
|
||||
case 0xe:
|
||||
return new WarnUnimplemented("vmull (poly)", machInst);
|
||||
}
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
|
||||
static StaticInstPtr
|
||||
decodeNeonTwoRegScalar(ExtMachInst machInst)
|
||||
{
|
||||
const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
|
||||
const uint32_t a = bits(machInst, 11, 8);
|
||||
|
||||
switch (a) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("vmla (int scalar)", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("vmla (fp scalar)", machInst);
|
||||
case 0x4:
|
||||
return new WarnUnimplemented("vmls (int scalar)", machInst);
|
||||
case 0x5:
|
||||
return new WarnUnimplemented("vmls (fp scalar)", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("vmlal (scalar)", machInst);
|
||||
case 0x6:
|
||||
return new WarnUnimplemented("vmlsl (scalar)", machInst);
|
||||
case 0x3:
|
||||
if (u) {
|
||||
return new Unknown(machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmlal", machInst);
|
||||
}
|
||||
case 0x7:
|
||||
if (u) {
|
||||
return new Unknown(machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmlsl", machInst);
|
||||
}
|
||||
case 0x8:
|
||||
return new WarnUnimplemented("vmul (int scalar)", machInst);
|
||||
case 0x9:
|
||||
return new WarnUnimplemented("vmul (fp scalar)", machInst);
|
||||
case 0xa:
|
||||
return new WarnUnimplemented("vmull (scalar)", machInst);
|
||||
case 0xb:
|
||||
if (u) {
|
||||
return new Unknown(machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqdmull", machInst);
|
||||
}
|
||||
case 0xc:
|
||||
return new WarnUnimplemented("vqdmulh", machInst);
|
||||
case 0xd:
|
||||
return new WarnUnimplemented("vqrdmulh", machInst);
|
||||
}
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
|
||||
static StaticInstPtr
|
||||
decodeNeonTwoRegMisc(ExtMachInst machInst)
|
||||
{
|
||||
const uint32_t a = bits(machInst, 17, 16);
|
||||
const uint32_t b = bits(machInst, 10, 6);
|
||||
switch (a) {
|
||||
case 0x0:
|
||||
switch (bits(b, 4, 1)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("vrev64", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("vrev32", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("vrev16", machInst);
|
||||
case 0x4:
|
||||
case 0x5:
|
||||
return new WarnUnimplemented("vpaddl", machInst);
|
||||
case 0x8:
|
||||
return new WarnUnimplemented("vcls", machInst);
|
||||
case 0x9:
|
||||
return new WarnUnimplemented("vclz", machInst);
|
||||
case 0xa:
|
||||
return new WarnUnimplemented("vcnt", machInst);
|
||||
case 0xb:
|
||||
return new WarnUnimplemented("vmvn (reg)", machInst);
|
||||
case 0xc:
|
||||
case 0xd:
|
||||
return new WarnUnimplemented("vpadal", machInst);
|
||||
case 0xe:
|
||||
return new WarnUnimplemented("vqabs", machInst);
|
||||
case 0xf:
|
||||
return new WarnUnimplemented("vqneg", machInst);
|
||||
default:
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
case 0x1:
|
||||
switch (bits(b, 3, 1)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("vcgt (imm #0)", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("vcge (imm #0)", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("vceq (imm #0)", machInst);
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("vcle (imm #0)", machInst);
|
||||
case 0x4:
|
||||
return new WarnUnimplemented("vclt (imm #0)", machInst);
|
||||
case 0x6:
|
||||
return new WarnUnimplemented("vabs (imm #0)", machInst);
|
||||
case 0x7:
|
||||
return new WarnUnimplemented("vneg (imm #0)", machInst);
|
||||
}
|
||||
case 0x2:
|
||||
switch (bits(b, 4, 1)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("vswp", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("vtrn", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("vuzp", machInst);
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("vzip", machInst);
|
||||
case 0x4:
|
||||
if (b == 0x8) {
|
||||
return new WarnUnimplemented("vmovn", machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vqmovun", machInst);
|
||||
}
|
||||
case 0x5:
|
||||
return new WarnUnimplemented("vqmovn", machInst);
|
||||
case 0x6:
|
||||
if (b == 0xc) {
|
||||
return new WarnUnimplemented("vshll", machInst);
|
||||
} else {
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
case 0xc:
|
||||
case 0xe:
|
||||
if (b == 0x18) {
|
||||
return new WarnUnimplemented("vcvt (single to half)",
|
||||
machInst);
|
||||
} else if (b == 0x1c) {
|
||||
return new WarnUnimplemented("vcvt (half to single)",
|
||||
machInst);
|
||||
} else {
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
default:
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
case 0x3:
|
||||
if (bits(b, 4, 3) == 0x3) {
|
||||
return new WarnUnimplemented("vcvt (fp and int)", machInst);
|
||||
} else if ((b & 0x1a) == 0x10) {
|
||||
return new WarnUnimplemented("vrecpe", machInst);
|
||||
} else if ((b & 0x1a) == 0x12) {
|
||||
return new WarnUnimplemented("vrsqrte", machInst);
|
||||
} else {
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
}
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
|
||||
StaticInstPtr
|
||||
decodeNeonData(ExtMachInst machInst)
|
||||
{
|
||||
const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
|
||||
const uint32_t a = bits(machInst, 23, 19);
|
||||
const uint32_t b = bits(machInst, 11, 8);
|
||||
const uint32_t c = bits(machInst, 7, 4);
|
||||
if (bits(a, 4) == 0) {
|
||||
return decodeNeonThreeRegistersSameLength(machInst);
|
||||
} else if ((c & 0x9) == 1) {
|
||||
if ((a & 0x7) == 0) {
|
||||
return decodeNeonOneRegModImm(machInst);
|
||||
} else {
|
||||
return decodeNeonTwoRegAndShift(machInst);
|
||||
}
|
||||
} else if ((c & 0x9) == 9) {
|
||||
return decodeNeonTwoRegAndShift(machInst);
|
||||
} else if ((c & 0x5) == 0) {
|
||||
if (bits(a, 3, 2) != 0x3) {
|
||||
return decodeNeonThreeRegDiffLengths(machInst);
|
||||
}
|
||||
} else if ((c & 0x5) == 4) {
|
||||
if (bits(a, 3, 2) != 0x3) {
|
||||
return decodeNeonTwoRegScalar(machInst);
|
||||
}
|
||||
} else if ((a & 0x16) == 0x16) {
|
||||
if (!u) {
|
||||
if (bits(c, 0) == 0) {
|
||||
return new WarnUnimplemented("vext", machInst);
|
||||
}
|
||||
} else if (bits(b, 3) == 0 && bits(c, 0) == 0) {
|
||||
return decodeNeonTwoRegMisc(machInst);
|
||||
} else if (bits(b, 3, 2) == 0x2 && bits(c, 0) == 0) {
|
||||
if (bits(machInst, 6) == 0) {
|
||||
return new WarnUnimplemented("vtbl", machInst);
|
||||
} else {
|
||||
return new WarnUnimplemented("vtbx", machInst);
|
||||
}
|
||||
} else if (b == 0xc && (c & 0x9) == 0) {
|
||||
return new WarnUnimplemented("vdup (scalar)", machInst);
|
||||
}
|
||||
}
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format ThumbNeonMem() {{
|
||||
decode_block = '''
|
||||
return decodeNeonMem(machInst);
|
||||
'''
|
||||
}};
|
||||
|
||||
def format ThumbNeonData() {{
|
||||
decode_block = '''
|
||||
return decodeNeonMem(machInst);
|
||||
'''
|
||||
}};
|
||||
|
||||
let {{
|
||||
header_output = '''
|
||||
StaticInstPtr
|
||||
|
|
|
|||
|
|
@ -54,13 +54,10 @@ def format ArmUnconditional() {{
|
|||
return new Cps(machInst, mods);
|
||||
}
|
||||
} else if (bits(op1, 6, 5) == 0x1) {
|
||||
return new WarnUnimplemented(
|
||||
"Advanced SIMD data-processing", machInst);
|
||||
return decodeNeonData(machInst);
|
||||
} else if (bits(op1, 6, 4) == 0x4) {
|
||||
if (bits(op1, 0) == 0) {
|
||||
return new WarnUnimplemented(
|
||||
"Advanced SIMD element or structure load/store",
|
||||
machInst);
|
||||
return decodeNeonMem(machInst);
|
||||
} else if (bits(op1, 2, 0) == 1) {
|
||||
// Unallocated memory hint
|
||||
return new NopInst(machInst);
|
||||
|
|
|
|||
Loading…
Reference in a new issue