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ARM: Implement signed add/subtract and subtract/add.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:06 -05:00
parent a895514d35
commit 8ba812f1fb
1 changed files with 40 additions and 0 deletions
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40
src/arch/arm/isa/insts/data.isa
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@ -428,6 +428,46 @@ let {{
Dest = resTemp;
resTemp = geBits;
''', flagType="ge", buildNonCc=False)
buildRegDataInst("sasx", '''
int32_t midRes, geBits = 0;
resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
midRes = arg1Low - arg2High;
if (midRes >= 0) {
geBits = geBits | 0x3;
}
replaceBits(resTemp, 15, 0, midRes);
midRes = arg1High + arg2Low;
if (midRes >= 0) {
geBits = geBits | 0xc;
}
replaceBits(resTemp, 31, 16, midRes);
Dest = resTemp;
resTemp = geBits;
''', flagType="ge", buildNonCc=True)
buildRegDataInst("ssax", '''
int32_t midRes, geBits = 0;
resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
midRes = arg1Low + arg2High;
if (midRes >= 0) {
geBits = geBits | 0x3;
}
replaceBits(resTemp, 15, 0, midRes);
midRes = arg1High - arg2Low;
if (midRes >= 0) {
geBits = geBits | 0xc;
}
replaceBits(resTemp, 31, 16, midRes);
Dest = resTemp;
resTemp = geBits;
''', flagType="ge", buildNonCc=True)
buildRegDataInst("uqadd16", '''
uint32_t midRes;