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ARM: Implement the VFP version of vneg.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:14 -05:00
parent 65f5204325
commit cd0a6a1303
2 changed files with 39 additions and 1 deletions
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16
src/arch/arm/isa/formats/fp.isa
View file

@ -558,7 +558,21 @@ let {{
}
case 0x1:
if (opc3 == 1) {
return new WarnUnimplemented("vneg", machInst);
uint32_t vd;
uint32_t vm;
if (bits(machInst, 8) == 0) {
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
return new VnegS(machInst,
(IntRegIndex)vd, (IntRegIndex)vm);
} else {
vd = (bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1);
vm = (bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1);
return new VnegD(machInst,
(IntRegIndex)vd, (IntRegIndex)vm);
}
} else {
return new WarnUnimplemented("vsqrt", machInst);
}

24
src/arch/arm/isa/insts/fp.isa
View file

@ -258,4 +258,28 @@ let {{
header_output += RegRegRegOpDeclare.subst(vmulDIop);
decoder_output += RegRegRegOpConstructor.subst(vmulDIop);
exec_output += PredOpExecute.subst(vmulDIop);
vnegSCode = '''
FpDest = -FpOp1;
'''
vnegSIop = InstObjParams("vnegs", "VnegS", "RegRegOp",
{ "code": vnegSCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vnegSIop);
decoder_output += RegRegOpConstructor.subst(vnegSIop);
exec_output += PredOpExecute.subst(vnegSIop);
vnegDCode = '''
IntDoubleUnion cOp1, cDest;
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
cDest.fp = -cOp1.fp;
FpDestP0.uw = cDest.bits;
FpDestP1.uw = cDest.bits >> 32;
'''
vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp",
{ "code": vnegDCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vnegDIop);
decoder_output += RegRegOpConstructor.subst(vnegDIop);
exec_output += PredOpExecute.subst(vnegDIop);
}};