gem5/src/arch
2008-11-09 21:55:43 -08:00
..
alpha Add in Context IDs to the simulator. From now on, cpuId is almost never used, 2008-11-02 21:57:07 -05:00
mips get rid of all instances of readTid() and getThreadNum(). Unify and eliminate 2008-11-04 11:35:42 -05:00
sparc Fix a few more places where the context stuff wasn't changed 2008-11-05 07:20:03 -08:00
x86 X86: Fix completeAcc get call. 2008-11-09 21:55:43 -08:00
isa_parser.py style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
isa_specific.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
micro_asm.py Microcode: Fix a silent typo error in the microcode assembler. 2008-10-09 00:07:38 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00