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ARM: Fix the implementation of BX to work in thumbEE mode.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent bb0d390105
commit eb0823c4f2
2 changed files with 13 additions and 15 deletions
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4
src/arch/arm/insts/static_inst.hh
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@ -238,9 +238,9 @@ class ArmStaticInst : public StaticInst
Addr newPc = (val & ~PcModeMask);
if (thumbEE) {
if (bits(newPc, 0)) {
warn("Bad thumbEE interworking branch address %#x.\n", newPc);
} else {
newPc = newPc & ~mask(1);
} else {
panic("Bad thumbEE interworking branch address %#x.\n", newPc);
}
} else {
if (bits(newPc, 0)) {

24
src/arch/arm/isa/insts/branch.isa
View file

@ -69,15 +69,8 @@ let {{
blxCode = '''
Addr PC = readPC(xc);
Addr tBit = PC & (ULL(1) << PcTBitShift);
// Other than the assert below, jBit isn't used.
#if !defined(NDEBUG)
Addr jBit = PC & (ULL(1) << PcJBitShift);
#endif
// X isn't permitted in ThumbEE mode. We shouldn't be in jazzelle mode?
assert(!jBit);
bool arm = !tBit;
arm = arm; // In case it's not used otherwise.
Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
%(link)s
// Switch modes
%(branch)s
@ -89,11 +82,6 @@ let {{
for (mnem, imm, link) in blxList:
Name = mnem.capitalize()
if imm and link: #blx with imm
branchStr = "FNPC = tempPc ^ (ULL(1) << PcTBitShift);"
else:
branchStr = "IWNPC = tempPc ^ (ULL(1) << PcTBitShift);"
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
@ -104,7 +92,7 @@ let {{
constructor = BranchImmConstructor
else:
Name += "Reg"
newPC = '(PC & PcModeMask) | Op1'
newPC = 'Op1'
base = "BranchRegCond"
declare = BranchRegCondDeclare
constructor = BranchRegCondConstructor
@ -127,6 +115,16 @@ let {{
'''
else:
linkStr = ""
if imm and link: #blx with imm
branchStr = '''
Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
FNPC = tempPc ^ (ULL(1) << PcTBitShift);
'''
else:
branchStr = "IWNPC = %(newPC)s;"
branchStr = branchStr % { "newPC" : newPC }
code = blxCode % {"link": linkStr,
"newPC": newPC,
"branch": branchStr}