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ARM: Ignore accesses to DCCIMVAC.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 6ae4d34a12
commit 7932b86298
2 changed files with 14 additions and 9 deletions
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16
src/arch/arm/isa/formats/misc.isa
View file

@ -90,14 +90,18 @@ def format McrMrc15() {{
const bool isRead = bits(machInst, 20);
if (miscReg == MISCREG_NOP) {
switch (miscReg) {
case MISCREG_NOP:
return new NopInst(machInst);
} else if (miscReg == NUM_MISCREGS) {
case NUM_MISCREGS:
return new Unknown(machInst);
} else if (miscReg == MISCREG_DCCISW) {
return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
machInst);
} else {
case MISCREG_DCCISW:
return new WarnUnimplemented(
isRead ? "mrc dccisw" : "mcr dcisw", machInst);
case MISCREG_DCCIMVAC:
return new WarnUnimplemented(
isRead ? "mrc dccimvac" : "mcr dcimvac", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
} else {

7
src/arch/arm/miscregs.hh
View file

@ -83,6 +83,7 @@ namespace ArmISA
MISCREG_CP15_START,
MISCREG_SCTLR = MISCREG_CP15_START,
MISCREG_DCCISW,
MISCREG_DCCIMVAC,
MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
@ -140,7 +141,6 @@ namespace ArmISA
MISCREG_CP15DSB,
MISCREG_CP15DMB,
MISCREG_DCCMVAU,
MISCREG_DCCIMVAC,
MISCREG_CP15_END,
@ -158,7 +158,8 @@ namespace ArmISA
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
"spsr_mon", "spsr_und", "spsr_abt",
"fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@ -168,7 +169,7 @@ namespace ArmISA
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
"cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
"cp15dsb", "cp15dmb", "dccmvau",
"nop", "raz"
};