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ARM: Decode to specialized conditional/unconditional versions of instructions.

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This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
This commit is contained in:
Gabe Black 2010-06-02 12:58:17 -05:00
parent 596cbe19d4
commit 358fdc2a40
9 changed files with 38 additions and 30 deletions
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4
src/arch/arm/insts/pred_inst.hh
View file

@ -176,7 +176,9 @@ class PredOp : public ArmStaticInst
/// Constructor
PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
ArmStaticInst(mnem, _machInst, __opClass),
condCode((ConditionCode)(unsigned)machInst.condCode)
condCode(machInst.itstateMask ?
(ConditionCode)(uint8_t)machInst.itstateCond :
(ConditionCode)(unsigned)machInst.condCode)
{
}
};

6
src/arch/arm/isa/formats/pred.isa
View file

@ -150,10 +150,10 @@ def format DataOp(code, flagtype = logic) {{
"predicate_test": predicateTest})
regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
{"code": regCode + regCcCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
{"code": immCode + immCcCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
header_output = BasicDeclare.subst(regIop) + \
BasicDeclare.subst(immIop) + \
BasicDeclare.subst(regCcIop) + \
@ -176,7 +176,7 @@ def format DataImmOp(code, flagtype = logic) {{
"predicate_test": predicateTest})
ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
{"code": code + getImmCcCode(flagtype),
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
header_output = BasicDeclare.subst(iop) + \
BasicDeclare.subst(ccIop)
decoder_output = BasicConstructor.subst(iop) + \

6
src/arch/arm/isa/insts/data.isa
View file

@ -129,7 +129,7 @@ let {{
immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
"DataImmOp",
{"code" : immCode + immCcCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
def subst(iop):
global header_output, decoder_output, exec_output
@ -166,7 +166,7 @@ let {{
regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
"DataRegOp",
{"code" : regCode + regCcCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
def subst(iop):
global header_output, decoder_output, exec_output
@ -206,7 +206,7 @@ let {{
mnem.capitalize() + suffix + "Cc",
"DataRegRegOp",
{"code" : regRegCode + regRegCcCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
def subst(iop):
global header_output, decoder_output, exec_output

2
src/arch/arm/isa/insts/macromem.isa
View file

@ -77,7 +77,7 @@ let {{
{'memacc_code': microLdrRetUopCode,
'ea_code':
'EA = Rb + (up ? imm : -imm);',
'predicate_test': predicateTest},
'predicate_test': condPredicateTest},
['IsMicroop'])
microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"

22
src/arch/arm/isa/insts/mem.isa
View file

@ -97,21 +97,27 @@ let {{
+ initiateAccTemplate.subst(iop)
+ completeAccTemplate.subst(iop))
def pickPredicate(blobs):
for val in blobs.values():
if re.search('(?<!Opt)CondCodes', val):
return condPredicateTest
return predicateTest
def loadStoreBase(name, Name, imm, eaCode, accCode, postAccCode,
memFlags, instFlags, double, strex, base = 'Memory',
execTemplateBase = ''):
codeBlobs = { "ea_code": eaCode,
"memacc_code": accCode,
"postacc_code": postAccCode,
"predicate_test": predicateTest }
"postacc_code": postAccCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
return loadStoreBaseWork(name, Name, imm, False, False, False,
codeBlobs, memFlags, instFlags, double,
strex, base, execTemplateBase)
def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
codeBlobs = { "ea_code": eaCode,
"memacc_code": accCode,
"predicate_test": predicateTest }
"memacc_code": accCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
return loadStoreBaseWork(name, Name, False, False, True, False,
codeBlobs, memFlags, instFlags, False, False,
'RfeOp', 'Load')
@ -119,8 +125,8 @@ let {{
def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags):
codeBlobs = { "ea_code": eaCode,
"memacc_code": accCode,
"postacc_code": "",
"predicate_test": predicateTest }
"postacc_code": "" }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
return loadStoreBaseWork(name, Name, False, False, False, True,
codeBlobs, memFlags, instFlags, False, False,
'SrsOp', 'Store')
@ -129,8 +135,8 @@ let {{
instFlags):
codeBlobs = { "ea_code": eaCode,
"preacc_code": preAccCode,
"postacc_code": postAccCode,
"predicate_test": predicateTest }
"postacc_code": postAccCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
return loadStoreBaseWork(name, Name, False, True, False, False,
codeBlobs, memFlags, instFlags, False, False,
'Swap', 'Swap')

16
src/arch/arm/isa/insts/misc.isa
View file

@ -63,7 +63,7 @@ let {{
mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
{ "code": mrsCpsrCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += MrsDeclare.subst(mrsCpsrIop)
decoder_output += MrsConstructor.subst(mrsCpsrIop)
exec_output += PredOpExecute.subst(mrsCpsrIop)
@ -85,7 +85,7 @@ let {{
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
{ "code": msrCpsrRegCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += MsrRegDeclare.subst(msrCpsrRegIop)
decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
exec_output += PredOpExecute.subst(msrCpsrRegIop)
@ -107,7 +107,7 @@ let {{
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
{ "code": msrCpsrImmCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += MsrImmDeclare.subst(msrCpsrImmIop)
decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
exec_output += PredOpExecute.subst(msrCpsrImmIop)
@ -197,7 +197,7 @@ let {{
'''
ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
{ "code": ssatCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
exec_output += PredOpExecute.subst(ssatIop)
@ -213,7 +213,7 @@ let {{
'''
usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
{ "code": usatCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += RegImmRegShiftOpDeclare.subst(usatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
exec_output += PredOpExecute.subst(usatIop)
@ -234,7 +234,7 @@ let {{
'''
ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
{ "code": ssat16Code,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += RegImmRegOpDeclare.subst(ssat16Iop)
decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
exec_output += PredOpExecute.subst(ssat16Iop)
@ -255,7 +255,7 @@ let {{
'''
usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
{ "code": usat16Code,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += RegImmRegOpDeclare.subst(usat16Iop)
decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
exec_output += PredOpExecute.subst(usat16Iop)
@ -415,7 +415,7 @@ let {{
'''
selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
{ "code": selCode,
"predicate_test": predicateTest }, [])
"predicate_test": condPredicateTest }, [])
header_output += RegRegRegOpDeclare.subst(selIop)
decoder_output += RegRegRegOpConstructor.subst(selIop)
exec_output += PredOpExecute.subst(selIop)

2
src/arch/arm/isa/insts/mult.isa
View file

@ -92,7 +92,7 @@ let {{
if doCc:
iopCc = InstObjParams(mnem + "s", Name + "Cc", base,
{"code" : code + ccCode,
"predicate_test": predicateTest})
"predicate_test": condPredicateTest})
if regs == 3:
declare = Mult3Declare

3
src/arch/arm/isa/operands.isa
View file

@ -154,6 +154,9 @@ def operands {{
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
'OptCondCodes': ('IntReg', 'uw',
'''(condCode == COND_AL || condCode == COND_UC) ?
INTREG_ZERO : INTREG_CONDCODES''', None, 2),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),

7
src/arch/arm/isa/templates/pred.isa
View file

@ -46,11 +46,8 @@
//
let {{
predicateTest = '''
testPredicate(CondCodes, machInst.itstateMask ?
(ConditionCode)(uint8_t)machInst.itstateCond :
condCode)
'''
predicateTest = 'testPredicate(OptCondCodes, condCode)'
condPredicateTest = 'testPredicate(CondCodes, condCode)'
}};
def template DataImmDeclare {{