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ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.

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Gabe Black 2010-06-02 12:58:08 -05:00
parent 6aa229386d
commit f9d1bba22a
1 changed files with 2 additions and 0 deletions
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2
src/arch/arm/isa/operands.isa
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@ -94,12 +94,14 @@ def operands {{
maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybeAIWPCWrite),
'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
maybePCRead, maybePCWrite),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,