Nilay Vaish
fe5deb4a22
x86 Regressions: Update stats due to register predication
2012-09-11 09:34:40 -05:00
Nilay Vaish
5cdf221d8c
Regression: Updates due to changes to Ruby memory controller
2012-09-10 12:44:03 -05:00
Andreas Hansson
0b1108c7a3
Ruby: Bump the stats after recent memory controller changes
...
This patch simply bumps the stats to avoid having failing
regressions. Someone with more insight in the changes should verify
that these differences all make sense.
2012-09-10 11:57:47 -04:00
Andreas Hansson
d628344574
Device: Update stats for PIO and PCI latency change
...
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
2012-09-10 11:57:37 -04:00
Joel Hestness
4124ea09f8
stats: Update Ruby regressions for memory controller fix
2012-09-05 20:53:34 -05:00
Andreas Hansson
fb5dd28420
Checker: Bump the realview-o3-checker regression
...
This patch bumps the stats for the realview-o3-checker after fixing
the checker CPU in the previous patch.
2012-08-28 14:30:25 -04:00
Nilay Vaish
1032bc72ed
Regression: updates ruby.stats due to change in virtual network
2012-08-25 15:49:07 -05:00
Andreas Hansson
a6074016e2
Bridge: Remove NACKs in the bridge and unify with packet queue
...
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 11:39:58 -04:00
Ali Saidi
73e9e923d0
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 10:38:05 -04:00
Ali Saidi
6a70ef30a3
stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update
2012-07-30 12:11:25 -04:00
Ali Saidi
19cc023cf5
stats: fix some miss-committed changes from the icache change
2012-07-28 13:48:04 -04:00
Ali Saidi
b1a58933e0
stats: update stats for icache change not allowing dirty data
2012-07-27 16:08:05 -04:00
Steve Reinhardt
42596d27e9
test: Update eio ref outputs due to recent changes
...
Actual stats updates covering period since original ref outputs
were clobbered.
2012-07-23 00:39:12 -04:00
Steve Reinhardt
882a4b65bd
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
...
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
2012-07-23 00:33:05 -04:00
Nilay Vaish
2590a7dd0a
Regression: Update stats due to changes to x86 cpuid instruction
2012-07-22 20:31:24 -05:00
Andreas Hansson
5e7f174b74
Regression: Fix topologies path in failing pc-simple-timing-ruby
...
This patch updates the path to the Ruby topologies and thus fixes a
failing regression.
2012-07-21 17:24:01 -04:00
Andreas Hansson
f00cba34eb
Mem: Make SimpleMemory single ported
...
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
2012-07-12 12:56:13 -04:00
Nilay Vaish
019ced8d85
Regression: update ruby.stats file
2012-07-12 08:39:20 -05:00
Brad Beckmann
b00fe08cc9
regress: ruby stat additions and config changes
2012-07-10 22:51:55 -07:00
Andreas Hansson
fda338f8d3
Stats: Updates due to bus changes
...
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
2012-07-09 12:35:41 -04:00
Ali Saidi
3965ecc36b
Stats: Update stats for RAS and LRU fixes.
2012-06-29 11:19:03 -04:00
Marc Orr
02f8178b44
Regression: Fix some bugs in simple-timing-mp-ruby.py.
2012-06-11 03:16:43 -04:00
Ali Saidi
c49e739352
all: Update stats for memory per master and total fix.
2012-06-05 01:23:16 -04:00
Gabe Black
6437f3f4ee
X86: Update stats for the CPUID change.
2012-06-04 10:43:11 -07:00
Andreas Hansson
0d32940711
Bus: Split the bus into a non-coherent and coherent bus
...
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00
Andreas Hansson
fb9bfb9cfc
Stats: Fix stats to match output after changeset 8800b05e1cb3
...
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of 8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.
changeset: 8983:8800b05e1cb3
user: Nathan Binkert <nate@binkert.org>
summary: stats: update stats for no_value -> nan
2012-05-09 11:52:14 -07:00
Gabe Black
f91b06e20e
X86: Add a 32 bit hello world test binary.
2012-05-27 19:01:09 -07:00
Nilay Vaish
0bff8eb210
X86 Regression: update stats due to cc register split
2012-05-22 11:38:04 -05:00
Ali Saidi
e62beaaa8f
ARM: update stats for clock frequency fix.
2012-05-10 18:04:29 -05:00
Nathan Binkert
4a644767c5
stats: update stats for no_value -> nan
...
Lots of accumulated older changes too.
2012-05-09 11:52:14 -07:00
Nilay Vaish
e8f56bdf45
Regression: Move x86 fs ruby simulation from quick to long
...
--HG--
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
2012-05-03 23:18:13 -05:00
Nilay Vaish
8966e6d36d
Regression: Stats update for X86 Ruby FS test
...
The kernel originally used to generate the stats is different from the one
at use on zizzer. This patch updates the stats with the correct kernel in
use.
2012-04-30 03:47:22 -05:00
Nilay Vaish
86f248e2a7
Regression: Add a test for x86 timing full system ruby simulation
2012-04-25 22:43:36 -05:00
Gabe Black
312b6fe43b
X86: Update stats for the slightly changed TLB behavior.
2012-04-24 00:48:57 -07:00
Andreas Hansson
b9bc530ad2
Regression: Add ANSI colours to highlight test status
...
This patch adds a very basic pretty-printing of the test status
(passed or failed) to highlight failing tests even more: green for
passed, and red for failed. The printing only uses ANSI it the target
output is a tty and supports ANSI colours. Hence, any regression
scripts that are outputting to files or sending e-mails etc should
still be fine.
2012-04-14 05:44:27 -04:00
Andreas Hansson
4bd61abb51
Stats: Update with use of std::map for ordered iteration in Ruby
...
This patch updates the stats to reflect the changes due to the use of
std::map instead of the hash map order-dependent iteration in Ruby.
2012-04-12 08:35:56 -04:00
Brad Beckmann
697fd8987b
regress: ruby random tester and hammer stats updates
2012-04-06 16:16:24 -07:00
Brad Beckmann
f050ebe3a8
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality
2012-04-06 13:47:06 -07:00
Andreas Hansson
b00949d88b
MEM: Enable multiple distributed generalized memories
...
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.
All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.
Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-06 13:46:31 -04:00
Nilay Vaish
390cfc7be9
Config: Change the way options are added
...
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
2012-03-28 11:01:53 -05:00
Ali Saidi
3c666083c6
ARM: Update stats for IT and conditional branch changes
2012-03-21 10:36:45 -05:00
Ali Saidi
470051345a
ARM: Update stats for CBNZ fix.
2012-03-09 15:33:07 -05:00
Ali Saidi
927bba9d60
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 09:59:29 -05:00
Geoffrey Blake
da0d67c3d6
CheckerCPU: Make some basic regression tests for CheckerCPU
...
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
2012-03-09 09:59:28 -05:00
Ali Saidi
eaa994e7f6
cache: Allow main memory to be at disjoint address ranges.
2012-03-09 09:59:25 -05:00
Gabe Black
cda4c2d280
Fix the SPARC fs regression by adding a call to createInterruptController.
2012-03-08 02:10:03 -08:00
Andreas Hansson
75681d3c1b
Stats: Update stats for changeset 8868
...
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
2012-03-06 11:14:54 -05:00
Andreas Hansson
32eae8094d
CPU: Check that the interrupt controller is created when needed
...
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number
of the regression scripts.
2012-03-02 09:21:48 -05:00
Andreas Hansson
c0b9f324bf
Stats: Fix the realview regression stats after nvmem move
...
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
2012-03-02 09:18:50 -05:00
Steve Reinhardt
13e14ba93c
EIO: update stats (mostly order change, some renames)
2012-02-29 01:51:39 -05:00
Andreas Hansson
ac91f90145
Script: Fix the scripts that use the num_cpus cache parameter
...
This patch merely removes the use of the num_cpus cache parameter
which no longer exists after the introduction of the masterIds. The
affected scripts fail when trying to set the parameter. Note that this
patch does not update the regression stats.
2012-02-14 12:11:18 -05:00
Ali Saidi
0d46708dc2
bp: fix up stats for changes to branch predictor
2012-02-13 12:30:30 -06:00
Andreas Hansson
5a9a743cfc
MEM: Introduce the master/slave port roles in the Python classes
...
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Ali Saidi
8cb4a2208d
tests: fix diff-out script for op/inst stat changes.
2012-02-12 18:35:59 -06:00
Ali Saidi
4f8d1a4cef
stats: update stats for insts/ops and master id changes
2012-02-12 16:07:43 -06:00
Dam Sunwoo
230540e655
mem: fix cache stats to use request ids correctly
...
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
2012-02-12 16:07:39 -06:00
Nilay Vaish
b7cf64398f
Regressions: Update stats due to change in MESI protocol
2012-02-12 13:22:04 -06:00
Nilay Vaish
26ca8b8747
Regressions: Update stats due to O3 CPU changes
2012-02-10 09:51:37 -06:00
Gabe Black
e88165a431
Merge with main repository.
2012-01-30 21:07:57 -08:00
Andreas Hansson
ade53def92
Ruby: Connect system port in Ruby network test
...
This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.
2012-01-30 09:37:06 -05:00
Gabe Black
39f314cc15
Yet another merge with the main repository.
...
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
2012-01-29 03:27:15 -08:00
Nilay Vaish
f19b3f30b4
X86 Regressions: Update stats due to introduction of TSO
2012-01-28 19:09:17 -06:00
Gabe Black
57e07ac2d2
SE/FS: Make both SE and FS tests available all the time.
...
--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
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rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simout => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
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rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
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rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
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rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
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rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
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rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
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rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
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rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
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rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
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rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
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rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
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rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
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rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/test.py => tests/long/se/70.twolf/test.py
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
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rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
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rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simout => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
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rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
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rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
2012-01-28 07:24:45 -08:00
Gabe Black
ec20ee2f7c
SE/FS: Make SE vs. FS mode a runtime parameter.
2012-01-28 07:24:34 -08:00
Gabe Black
c3d41a2def
Merge with the main repo.
...
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-28 07:24:01 -08:00
Gabe Black
da2a4acc26
Merge yet again with the main repository.
2012-01-16 04:27:10 -08:00
Ali Saidi
a17dbdf883
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 17:19:50 +00:00
Andreas Hansson
2208ea049f
MEM: Make the bus bridge unidirectional and fixed address range
...
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.
In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de
MEM: Add port proxies instead of non-structural ports
...
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Andreas Hansson
06c39a154c
Ruby: Change the access permissions for MOESI hammer
...
Regression statistics update.
2012-01-17 12:55:07 -06:00
Ali Saidi
8c7936c40c
stats: undo parser change from initparam change
2012-01-16 22:37:05 -05:00
Nilay Vaish
d272bdb1bf
MOESI Hammer: Update regression test output
2012-01-10 17:28:49 -06:00
Nilay Vaish
a5a2b9ecbd
X86 Regressions: Update stats due to fence instruction
2012-01-10 09:59:01 -06:00
Ali Saidi
8d757038b5
stats: Update stats for ARM init param changes.
2012-01-09 18:08:20 -06:00
Gabe Black
ec936364b7
Merge with the main repository again.
2012-01-07 02:15:35 -08:00
Gabe Black
36a822f08e
Merge with main repository.
2012-01-07 02:10:34 -08:00
Brad Beckmann
cb6ea0492f
regress: updated hammer memtest and rubytest outputs
...
--HG--
extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694
2011-12-01 11:54:30 -08:00
Ali Saidi
d1dd7a24db
imported patch ext/stats_updates.patch
...
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
2011-12-01 00:15:23 -08:00
Chander Sudanthi
61c14da751
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
...
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Ali Saidi
e436d187e7
SPARC: update SE stats for FP fix
...
--HG--
extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85
2011-11-30 18:57:11 -05:00
Gabe Black
0e621fd136
SPARC: Update the FS stats for the recent FP fix.
...
--HG--
extra : rebase_source : 643e3541507576e30d9cd4dec045e5b94532c342
2011-11-28 04:19:57 -05:00
Nilay Vaish
f171a29118
Regression: Update statistics for x86 long regression tests
...
This patch updates reference statistics for the regression tests. This
update was necessitated by a recent change in behavior of some instructions
in the x86 architecture.
2011-11-17 22:53:56 -06:00
Nilay Vaish
472645d62a
Tests: Update stats due to addition of fence microop
2011-11-05 15:32:23 -05:00
Steve Reinhardt
c6dd122fee
tests: fix spurious scons "Error 1" messages
...
Turns out these are due to diff reporting that files
acutally differed via a non-zero exit code.
2011-10-22 16:52:07 -07:00
Gabe Black
020e923ba7
Configs: Use connectAllPorts to connect ports for simple-timing-ruby.
2011-10-08 23:24:34 -07:00
Ali Saidi
ae62d97158
MIPS: Fix regressions tests
2011-09-17 12:34:03 -04:00
Ali Saidi
28a2236ec1
O3: Update stats for new ordering fix.
2011-09-13 12:58:09 -04:00
Gabe Black
c5fd6f4fec
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 01:35:05 -07:00
Ali Saidi
ba265abbfd
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 15:08:09 -05:00
Ali Saidi
999cd8aef5
StoreSet: Update stats for store-set clearing
2011-08-19 15:08:08 -05:00
Ali Saidi
f125ef22b9
O3: Update stats for LSQ changes.
2011-08-19 15:08:06 -05:00
Gabe Black
cbf7982081
X86: Add an X86_FS o3 regression.
2011-08-14 18:34:17 -07:00
Gabe Black
a81d4a8fcd
Stats: Small update to stats for change to x86 inst flags.
2011-08-13 23:03:21 -07:00
Gabe Black
6bbd74e2d9
SCons,tests: Tell scons about pc-o3-timing regressions.
2011-08-09 11:33:12 -07:00
Gabe Black
c3e7b57fe7
Stats: Update stats for the end of macroop O3 fix.
2011-08-09 11:31:48 -07:00
Gabe Black
8586a800b7
Stats: Update stats for the recent O3 interrupt change.
2011-08-09 03:37:45 -07:00
Nilay Vaish
821dfc1289
BuildEnv: Eliminate RUBY as build environment variable
...
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
2011-08-08 10:50:13 -05:00
Gabe Black
9c806fe65a
Stats: Update stats for the previous change.
2011-08-07 15:41:09 -07:00
Gabe Black
a1aaeac2f9
Stats: Update the stats after the uninitialized branch predictor variable fix.
2011-08-07 09:22:18 -07:00
Nilay Vaish
1b49c56679
Scons: Drop RUBY as compile time option.
...
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Gabe Black
6308ca27ff
Stats: Update stats for the recent fix to fetch.
2011-07-30 23:23:01 -07:00
Korey Sewell
145deb7c88
inorder-fs: temp. regression removal
...
remove this regression till the fix for the hwrei instruction is put in
2011-07-15 21:26:18 -04:00
Ali Saidi
09914cdf8f
ARM: Update stats for better miscreg support for MP configurations.
2011-07-15 11:53:35 -05:00
Ali Saidi
3ebfe2eb01
O3: Update stats for fetch and bp changes.
2011-07-10 12:56:09 -05:00
Gabe Black
a4bd05dc37
X86: Add a config for an FS regression on O3.
2011-07-05 17:46:46 -07:00
Gabe Black
d42e471baa
Stats: Update stats for the x86 store fault fix.
2011-07-02 22:31:42 -07:00
Brad Beckmann
12dc51ff0d
Regression: Updates regression outputs for Ruby memtest
...
This patch updates the regression outputs for Ruby memtest. This was
required because of the changes carried out by the addition of functional
access support to Ruby.
2011-06-30 19:57:26 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a
Ruby: Add support for functional accesses
...
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Korey Sewell
6630d4c64b
inorder: sparc: add 02.insttest regression
2011-06-20 22:44:24 -04:00
Korey Sewell
d1e8be9a73
inorder: sparc: add hello world regression
...
- add InOrderCPU compile option to SPARC
- add hello regression for SPARC
2011-06-20 22:44:22 -04:00
Korey Sewell
08c1a6f41b
merge regression updates
2011-06-20 18:58:31 -04:00
Korey Sewell
b5736ba4ef
alpha:o3:simple: update simout/err files
...
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
2011-06-20 18:57:14 -04:00
Korey Sewell
9124f46587
inorder: alpha-hello regression update
2011-06-20 12:21:10 -04:00
Korey Sewell
97449ef3da
inorder: update eon regr w/eon info
...
previous commit copied over O3 stats, this one puts the inorder ones in the right place
2011-06-19 21:54:53 -04:00
Korey Sewell
d16b0dc319
inorder: add 10.linux-boot regression
2011-06-19 21:43:43 -04:00
Korey Sewell
60da569846
inorder: add eon regression
2011-06-19 21:43:43 -04:00
Korey Sewell
55dce6419d
inorder: update SE regressions
2011-06-19 21:43:42 -04:00
Korey Sewell
e8b7df072b
inorder: make InOrder CPU FS compilable/visible
...
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
2011-06-19 21:43:39 -04:00
Korey Sewell
1aa4869ff0
sparc: update long regressions
2011-06-12 21:35:03 -04:00
Korey Sewell
fb8c958241
sparc: update o3 regressions
2011-06-10 22:15:34 -04:00
Korey Sewell
9331b5d26a
sparc: update simple cpu regressions
...
use stats file generated by zizzer
2011-06-10 03:45:24 -04:00
Steve Reinhardt
8a652f9871
config: tweak ruby configs to clean up hierarchy
...
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.
1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.
2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.
3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.
2011-05-23 14:29:23 -07:00
Ali Saidi
5d5b0f49cc
Stats: Update stats for minor O3 changes below.
2011-05-23 10:59:13 -05:00
Ali Saidi
44e599a1a4
ARM: Fix up stats for previous changes to condition codes
2011-05-13 17:29:27 -05:00
Ali Saidi
fea2c26402
ARM: Update ARM_FS stats for mp changes
2011-05-04 20:38:28 -05:00
Ali Saidi
307f089e7f
O3/ARM: Update stats for recent changes.
2011-05-04 20:38:27 -05:00
Brad Beckmann
001c16bc6d
regress: updates after changing ruby network bandwidth
2011-04-28 17:18:16 -07:00
Nathan Binkert
3d93439ee0
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 14:18:08 -07:00
Nathan Binkert
a7e27f9a82
tests: updates for stat name change
2011-04-22 10:18:51 -07:00
Nathan Binkert
8c1563096c
tests: update stats for name changes
2011-04-19 18:45:23 -07:00
Ali Saidi
d50d0152d0
ARM: Fix stats for ARM_SE checkpoint restore fix.
...
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
2011-04-12 16:09:20 -04:00
Ali Saidi
afa897403d
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 11:42:32 -05:00
Ali Saidi
b20e92e1ca
ARM: Update stats for previous changes.
2011-04-04 11:42:31 -05:00
Ali Saidi
1114be4b78
O3: Update stats for memory order violation checking patch.
2011-04-04 11:42:25 -05:00
Steve Reinhardt
bb67c706d6
tests: update reference outputs for ruby cache index change
...
MOESI_CMP_token is the only protocol that showed noticeable stats
differences.
2011-03-26 22:24:36 -07:00
Ali Saidi
63eb337b3b
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-17 19:20:22 -05:00
Ali Saidi
845f791f37
Stats: Update the statistics for rfe patch.
2011-03-17 19:20:20 -05:00
Ali Saidi
7112b44362
O3: Update regressions for mem block caching change.
2011-03-17 19:20:19 -05:00
Ali Saidi
a432d8e085
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
...
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Ali Saidi
3a44307e94
X86: Update the stats for parser on x86 O3.
2011-03-17 00:43:54 -04:00
Gabe Black
27f5a8c812
X86: Update the stats for gzip on x86 O3.
2011-03-16 19:08:41 -07:00
Gabe Black
47615d06bd
Regressions: Move the X86_FS regressions to "quick" instead of "long".
...
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
2011-03-12 14:41:30 -08:00
Gabe Black
fa448129b1
SCons: Turn some scons variables into command line options.
2011-03-03 23:54:31 -08:00
Gabe Black
e8b982e247
X86: Update stats for the x86 o3 hello world regression.
2011-03-01 23:18:00 -08:00
Gabe Black
b84ae9bd40
X86: Update X86_FS stats.
2011-02-27 16:24:54 -08:00
Korey Sewell
8135b81ae4
inorder: bzip2 regression update
2011-02-27 14:17:26 -05:00
Brad Beckmann
ae52ff631f
regress: MOESI_hammer memtest updates
2011-02-23 16:41:59 -08:00
Korey Sewell
72fb282ab1
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 16:35:25 -05:00
Ali Saidi
73603c2b17
ARM: Update regression tests for preceeding changes.
2011-02-23 15:10:50 -06:00
Ali Saidi
79dac89552
ARM: Clarifies creation of Linux and baremetal ARM systems.
...
makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified. Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
2011-02-23 15:10:48 -06:00
Korey Sewell
66bb732c04
m5: merge inorder/release-notes/make_release changes
2011-02-18 14:35:15 -05:00
Korey Sewell
ab9c20cc78
inorder: regr-update: reduce dynamic mem. use to speedup sims
...
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid
dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions
that were run, the sims are about 2x speedup from changeset 7726 which is the last change
since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 14:31:37 -05:00
Gabe Black
5ec5794456
X86: Update stats for the improved branch detection/prediction.
2011-02-13 17:46:04 -08:00
Gabe Black
44306e8114
X86: Update stats now that the dest reg isn't read unnecessarily to set flags.
2011-02-13 17:45:30 -08:00
Gabe Black
b046f3feb6
X86: Update stats for the reduced register reads.
2011-02-13 17:44:32 -08:00
Korey Sewell
2971b8401a
inorder:regress: host-inst-rate improved ~58%
...
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext)
the latest changes to how instruction scheduling (how instructions figure out what they want to
do on each pipeline stage in the inorder model) were able to improve performance by a nice
amount... The latest results for the inorder model process about 100k insts/second
(note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-12 10:14:52 -05:00
Ali Saidi
2055df8322
Stats: Update the statistics for vnc patch.
2011-02-11 18:29:36 -06:00
Brad Beckmann
4eab18fd06
regess: protocol regression tester updates
2011-02-08 18:07:54 -08:00
Brad Beckmann
ea9d4c3a97
memtest: due to contention increase, increased deadlock threshold
2011-02-08 15:53:33 -08:00
Gabe Black
0851580aad
Stats: Re update stats.
2011-02-07 19:23:13 -08:00
Gabe Black
1b64bfa933
Stats: Back out broken update.
2011-02-07 19:23:11 -08:00
Gabe Black
2107258d24
X86: Add stats for the new x86 fs regressions.
2011-02-07 01:23:16 -08:00
Gabe Black
dd53743797
X86: Add scripts to support X86 FS configurations in the regressions.
2011-02-07 01:23:02 -08:00
Brad Beckmann
45f881919f
regress: Regression Tester output updates
2011-02-06 22:14:23 -08:00
Gabe Black
55df9e348c
X86: Add o3 regressions in SE mode.
...
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 00:16:09 -08:00
Gabe Black
0aafbe4098
X86: Update ruby stats for stupd change.
2011-02-04 03:47:23 -08:00
Korey Sewell
a48fe2729a
imported patch regression_updates
2011-02-04 00:09:22 -05:00
Gabe Black
00f24ae92c
Config: Keep track of uncached and cached ports separately.
...
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
2011-02-03 20:23:00 -08:00
Gabe Black
54f88d84c2
Stats: Update the x86 stats to reflect changing stupd to a store and update.
2011-02-02 19:56:49 -08:00
Ali Saidi
f7885b8f26
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 16:30:06 -06:00
Ali Saidi
9b67f3723e
Stats: Update stats for previous set of patches.
2011-01-18 16:30:06 -06:00
Gabe Black
6fb521faba
SPARC: Update stats for the call r15 as source change.
2011-01-15 15:30:34 -08:00
Nilay Vaish
bec0103bb4
Regression Tests: Update the output for MESI_CMP_directory
...
This patch updates the output for regression tests that are carried out on
MESI_CMP_directory protocol. The changes made to the protocol in order to
remove the bugs present result in regression failure for the 60.rubytest.
Since the earlier protocol was incorrect, so we certainly cannot relay on the
earlier reference output. Hence, the update.
2011-01-13 22:48:03 -06:00
Ali Saidi
1cfe2c8820
Stats: Fix stats for cumulative flags change.
2010-12-07 16:19:57 -08:00
Gabe Black
0e41d4e5ea
Stats: Update the O3 fetch stats for SPARC.
2010-11-15 19:37:15 -08:00
Ali Saidi
371110fb0a
Regressions: Update regressions for SIMD opclass changes
2010-11-15 14:04:05 -06:00
Ali Saidi
c370866331
ARM: Update regressions for CLCD and KMI additions
2010-11-15 14:04:03 -06:00
Ali Saidi
0b7967d606
Update EIO regressions for last set of patches
2010-11-10 00:48:03 -06:00
Ali Saidi
06c5283930
ARM: Update SE stats for TLB stats additions
2010-11-08 13:59:35 -06:00
Ali Saidi
fe300c6de2
ARM: Add full-system regressions
2010-11-08 13:58:25 -06:00
Ali Saidi
b4b6a2338a
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
2010-11-08 13:58:24 -06:00
Gabe Black
b53231e7fe
Ref output: Update refs for PCState change.
2010-10-31 00:07:48 -07:00
Steve Reinhardt
13a15c55a4
stats: update stats for previous cset
...
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt
0bd9cea340
diff-out: clean up options
...
Make diff-out sort stats changes by percentage
by default, with '-a' to use current alpha sort
(instead of requiring '-p' to sort by percentage).
Other minor options cleanup too.
2010-09-21 23:07:34 -07:00
Steve Reinhardt
db2f226834
tests: print if output files match
...
Add '-s' flag to diff command generating outdiff
file so we have positive confirmation when
outputs match.
2010-09-21 23:07:34 -07:00
Steve Reinhardt
9e45ada171
stats: update stats for preceding coherence changes
...
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Ali Saidi
e6d3fe8a0c
ARM: Update regression tests for ldr/str microcode changes.
2010-08-25 19:10:42 -05:00
Ali Saidi
03584ad439
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 11:18:42 -05:00
Brad Beckmann
3d93afe348
regress: Regression tester updates
...
Regression tester updates required by the following patches:
brad/moved_python_protocol_files: config: moved python protocol config files
brad/ruby_options_movement: config: reorganized how ruby specifies command-line options
brad/config_token_bcast: ruby: added token broadcast config params to cmd options
brad/topology_name: config: Added the topology description to m5 config.ini
brad/ruby_system_names: config: Improve ruby simobject names
brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing
brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh
brad/memtest_dma_extension: memtest: Memtester support for DMA
brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs
brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling
brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats
brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token
brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling
brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes
brad/ruby_latency_fixes: ruby: Reduced ruby latencies
brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior
brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests
brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes
brad/ruby_cmd_options: config: added cmd options to control ruby debug
brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts
brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation
brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks
brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining
brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling
brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer
brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize
brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration
brad/hammer_probe_filter: ruby: added probe filter support to hammer
brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles
brad/recycle_latency_fix: ruby: Recycle latency fix for hammer
brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling
brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type
brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer
brad/regress_updates: regress: Regression tester updates
2010-08-20 17:44:26 -07:00
Steve Reinhardt
5577048bcf
test: Update stats for python object iteration.
...
Small changes in tests with data races due to new object creation
order.
2010-08-17 05:14:03 -07:00
Steve Reinhardt
c2cce96a0b
sim: fail on implicit creation of orphans via ports
...
Orphan SimObjects (not in the config hierarchy) could get
created implicitly if they have a port connection to a SimObject
that is in the hierarchy. This means that there are objects on
the C++ SimObject list (created via the C++ SimObject
constructor call) that are unknown to Python and will get
skipped if we walk the hierarchy from the Python side (as we are
about to do). This patch detects this situation and prints an
error message.
Also fix the rubytester config script which happened to rely on
this behavior.
2010-08-17 05:06:22 -07:00
Steve Reinhardt
1fbe466345
sim: make Python Root object a singleton
...
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Steve Reinhardt
0f8b5afd7a
tests: update reference config.ini files for previous cset
...
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Ali Saidi
1b73376b0b
ARM: Add regression tests
2010-07-27 01:03:44 -04:00
Korey Sewell
f2eba81f50
inorder: update regressions from RAS fix
2010-06-25 17:42:55 -04:00
Korey Sewell
0135cdab8d
inorder: update regressions
2010-06-24 15:34:21 -04:00
Korey Sewell
e17c41c176
inorder: update regressions
2010-06-23 18:21:44 -04:00
Steve Reinhardt
625854785b
stats: update stats for SC protocol change
...
Some subset of UpgradeReq messages shifted to the
new SCUpgradeReq type. Other than that there
are no significant differences.
2010-06-16 15:25:57 -07:00
Nathan Binkert
86a93fe7b9
stats: only consider a formula initialized if there is a formula
2010-06-15 01:18:36 -07:00
m5test
744b59d6de
tests: Update O3 ref outputs to reflect Lisa's dist format change.
2010-06-06 18:39:10 -04:00
Steve Reinhardt
30deac9050
stats: fix stats diff script
...
Previously the return value ignored missing/added stats,
making the regressions not tell you when you needed to
update the reference stats because of these changes.
Also stop filtering distributions when reporting these;
not sure why we did that in the first place.
Also get rid of obsolete hacks for the "fetch-loss" stats
that have been gone for a long time.
2010-06-06 01:22:14 -04:00
Ali Saidi
f703e9c975
ARM: Updated regressions for changes in SE mode stack
2010-06-02 12:58:17 -05:00
Gabe Black
caa95639ec
ARM: Update the stats for the new syscall behavior.
2010-06-02 12:58:05 -05:00
Gabe Black
d8294575e1
ARM: Update the stats now that VFP load/store multiple is implemented.
2010-06-02 12:58:04 -05:00
Ali Saidi
a990335b32
BPRED: Update one missing regression
2010-05-19 00:36:05 -04:00
Ali Saidi
e63c73b45d
BPRED: Update regressions for tournament predictor fix.
2010-05-13 23:45:59 -04:00
Gabe Black
81e68287bb
X86: Update the stats for the new aux vectors in the ruby regression.
...
I forgot to turn on ruby when updating the stats before.
2010-05-06 13:41:08 -07:00
Gabe Black
8b0c83008e
X86: Update stats for the updated auxilliary vectors.
2010-05-03 00:45:01 -07:00
Korey Sewell
c90ee27283
inorder: update regressions for fwd-ing patch
2010-04-11 00:21:49 -04:00
Korey Sewell
941399728f
inorder: update twolf/vortex regressions
2010-03-27 02:21:22 -04:00
Korey Sewell
70308bc835
inorder: update hello world for alpha and mips
2010-03-23 00:26:53 -04:00
Korey Sewell
6364fbac39
inorder: update twolf regression
2010-03-23 00:14:52 -04:00
Korey Sewell
ef0fb9bee4
inorder: update vortex regression
2010-03-22 23:39:23 -04:00
Brad Beckmann
7aba8d7db0
ruby: Regression updates for new ruby config locations
2010-03-21 21:22:22 -07:00
Lisa Hsu
ee20a7c0bd
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 10:08:41 -08:00
Lisa Hsu
1d3228481f
cache: Make caches sharing aware and add occupancy stats.
...
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Korey Sewell
04466ab4ca
inorder: update hello world mips
2010-01-31 18:31:28 -05:00
Korey Sewell
a3c635f777
inorder: vortex alpha regression
2010-01-31 18:31:20 -05:00
Korey Sewell
81c9fdad24
inorder: twolf alpha regression
2010-01-31 18:31:14 -05:00
Korey Sewell
7712740b5f
inorder: update hello world alpha
2010-01-31 18:31:09 -05:00
Brad Beckmann
ab2f864af2
m5: Regression Tester Update
...
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
2010-01-29 20:29:40 -08:00
Brad Beckmann
26cce73e97
ruby: memtest-ruby updated to the new config system
2010-01-29 20:29:33 -08:00
Steve Reinhardt
2f567f69cf
tests: added M5_TEST_PROGS environment variable
...
to allow override of global location for regression test binaries.
2010-01-29 20:29:14 -08:00
Derek Hower
5a4ebd6d12
config: changed default ruby config file for regression
2010-01-25 11:51:16 -06:00
Derek Hower
589218168c
Automated merge with ssh://hg@m5sim.org/m5
2010-01-22 17:23:21 -06:00
Derek Hower
f7de30ab1a
memtest differences from Derek's changes
2010-01-19 17:17:19 -06:00
Derek Hower
279f179bab
merge
2010-01-19 15:48:12 -06:00
Gabe Black
4f4e6fc099
MIPS: Update the stats of the RUBY version of the regressions.
2010-01-02 07:06:26 -05:00
Gabe Black
47a1f11381
MIPS: Update stats for updated initial environment.
2009-12-31 15:30:51 -05:00
Brad Beckmann
295516a590
m5: refreshed the ruby memtest regression stats
2009-11-18 18:00:41 -08:00
Brad Beckmann
90d6e2652f
ruby: included ruby config parameter ports per core
...
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716
ruby: Support for merging ALPHA_FS and ruby
...
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Nathan Binkert
14b5169750
tests: update statistics for change caused by vsyscall support in x86
...
Caused by a slight change in memory layout.
2009-11-08 20:15:23 -08:00
Steve Reinhardt
934ba5265e
stats: update memtest-ruby
...
I don't know if the new stats are right or not, but we've
been too long with a useless regression so I'm just going
to update them.
2009-11-04 14:23:24 -08:00
Timothy M. Jones
2b232e11a8
test: Hello world test program for Power
...
includes reference outputs for the Hello World tests on simple-atomic
and o3-timing.
2009-10-27 09:24:40 -07:00
Nathan Binkert
5fe0762ee4
tests: update test for slight change due to the change in brk.
2009-10-24 10:53:58 -07:00
Korey Sewell
2b181fc3e7
mips: update hello-ruby stats
2009-10-06 20:54:04 -04:00
Korey Sewell
eb1bd7a2e6
mips-stats: update regressions of arguments fix
2009-09-24 12:30:53 -04:00
Nathan Binkert
9a8cb7db7e
python: Move more code into m5.util allow SCons to use that code.
...
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Derek Hower
6fc2a4cadc
ruby: cleaned up unified MESI/MOESI configuration
2009-09-11 16:22:59 -05:00
Gabe Black
70251bbb1a
X86: Update stats for new SSE instructions.
2009-08-17 22:27:30 -07:00
Tushar Krishna
35082a67b6
ruby/network data_msg_size bug fix with updated stats
2009-08-11 15:19:04 -07:00
Gabe Black
33b063a2a7
X86: Update the stats on the ruby x86 regressions for the new CMOVcc implementation.
2009-08-09 04:01:56 -07:00
Gabe Black
bcfc4178f5
X86: Update the stats for the slightly lengthened cmov.
2009-08-08 17:23:25 -07:00
Derek Hower
867269bc96
regression: updated stats
2009-08-05 14:20:53 -05:00
Derek Hower
ac15e42c17
Automated merge with ssh://hg@m5sim.org/m5
2009-08-03 11:39:08 -05:00
Derek Hower
8623b4b6ea
regression: updated stats
2009-07-31 00:43:09 -05:00
Gabe Black
9e292c950a
ARM: Update the stats for the EABI version of hello world.
2009-07-27 00:55:14 -07:00
Gabe Black
a343e33699
ARM: Update the reference outputs for the new binary and fstat64 struct.
2009-07-27 00:51:27 -07:00
Gabe Black
70dedd1d35
ARM: Replace hello world with an EABI version.
2009-07-27 00:51:15 -07:00
Korey Sewell
d4813236d6
regress: edit 2t hello smt file to specify numThreads
2009-07-25 22:22:13 -04:00
Derek Hower
e59d0e3e89
ruby: moved cache stats from Profiler to CacheMemory
...
Caches are now responsible for their own statistic gathering. This
requires a direct callback from the protocol on misses, and so all
future protocols need to take this into account.
2009-07-20 09:40:43 -05:00
Polina Dudnik
e557b4beb5
merge
2009-07-16 15:40:48 -05:00
Polina Dudnik
23a405f5d8
Tester update
2009-07-15 10:46:22 -05:00
Derek Hower
d51445490d
regression: updated memtest-ruby stats
...
This also includes a change to the default Ruby random seed, which was
previously set using the wall clock. It is now set to 1234 so that
the stat files don't change for the regression tester.
2009-07-13 14:45:15 -05:00
Steve Reinhardt
d7f9c86981
Add ability to skip tests by adding 'skip' file to test dir,
...
and skip simple-timing-mp-ruby test for now (until we fix ruby atomics).
2009-07-06 22:45:58 -07:00
Nathan Binkert
e3e509b31a
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-06 15:49:48 -07:00
Nathan Binkert
0c1a69e768
tests: update regression tests for changes in stats output and changes in ruby.
2009-07-06 15:49:48 -07:00
Nathan Binkert
da704f52e5
ruby: Fix RubyMemory to work with the newer ruby.
2009-07-06 15:49:47 -07:00
Gabe Black
5ae983f8da
inorder: Fix up some reference stats.
2009-07-04 21:46:23 -07:00
Gabe Black
85ca502611
ARM: Add a hello world regression.
2009-06-09 23:55:53 -07:00
Gabe Black
d91a3cf53d
ARM: Add a hello world binary.
2009-06-09 23:42:43 -07:00
Korey Sewell
c94944e257
inorder-regress: add hello MIPS_SE
2009-05-13 01:55:04 -04:00
Korey Sewell
373e55c7b9
inorder-regress: missing regress config file
...
regressions need to access this file to setup the InOrderCPU object
2009-05-12 20:30:40 -04:00
Korey Sewell
b5959124e1
inorder-regress: add vortex ALPHA_SE
2009-05-12 15:01:17 -04:00
Korey Sewell
39010b990d
inorder-regress: add twolf ALPHA-SE
2009-05-12 15:01:16 -04:00
Korey Sewell
ca20d1dd23
inorder-regress: add hello world
2009-05-12 15:01:16 -04:00
Nathan Binkert
cf6b4ef734
ruby: add RUBY sticky option that must be set to add ruby to the build
...
Default is false
2009-05-11 10:38:46 -07:00
Steve Reinhardt
b174ec065e
ruby: Initial references for ruby regressions
2009-05-11 10:38:46 -07:00
Steve Reinhardt
6df61e1f24
ruby: Set up Ruby regression tests.
2009-05-11 10:38:46 -07:00
Nathan Binkert
567cab6859
stats: update reference outputs now that compatibility is gone
...
Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 10:25:17 -07:00
Steve Reinhardt
7b40c36fbd
Update stats for new single bad-address responder.
...
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00
Steve Reinhardt
6629d9b2bc
mem: use single BadAddr responder per system.
...
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Steve Reinhardt
7b2f8e6857
Set up m5threads tests on classic (non-ruby) memory system.
...
Just one test (40.m5threads-test-atomic) is set up for now.
These tests require that the m5threads SPARC binaries are present
in /dist or in test-progs.
2009-04-21 08:37:50 -07:00
Gabe Black
b4ad233c0c
X86: Update the stats for the fix for CPUID.
2009-04-19 03:14:33 -07:00
Korey Sewell
a25aa00522
o3-mips-regress: add hello word regression.
2009-04-18 10:42:29 -04:00
Steve Reinhardt
48d4ca522a
Update stats after elimination of Unallocated state.
...
Somehow ending threads with halt() instead of deallocate()
reduces the squash count on o3 by 1 (and a few other
similarly trivial changes).
2009-04-15 13:13:58 -07:00
Nathan Binkert
18a30524d6
alpha: get rid of all turbolaser remnants
2009-04-08 22:22:49 -07:00
Nathan Binkert
374ba9bae3
tests: update tests for TLB unification
2009-04-08 22:21:30 -07:00
Steve Reinhardt
15f0e44060
Very minor regression stats updates due top previous changeset.
...
Setting dirty bit on swaps added a handful of writebacks in a
few of the longer-running SPARC_SE benchmarks.
2009-03-16 11:01:23 -04:00
Steve Reinhardt
17cb191c98
tests: use env.Execute instead of Execute to pick up env vars.
2009-03-11 10:54:42 -07:00
Steve Reinhardt
4c902714f7
Minor tweak to regression exit status message.
2009-03-07 17:24:13 -08:00
Steve Reinhardt
4f1855484c
Fix up regression execution to better handle tests that end abnormally.
...
E.g., mark aborts due to assertion failures as failed tests,
but those that get killed by the user as needing to be rerun, etc.
2009-03-07 16:58:51 -08:00
Nathan Binkert
5cf0605766
tests: update tests because of changes in stat names and in the stats package
2009-03-07 14:30:55 -08:00
Gabe Black
5d5e001ac3
X86: Update stats now that prefetch is implemented.
2009-02-25 10:19:28 -08:00
Gabe Black
1bfab291f1
CPU: Update stats now that there's no fetch in the middle of macroops.
2009-02-25 10:18:45 -08:00
Gabe Black
f02df8cb74
X86: Update stats for in place TLB miss handling.
2009-02-25 10:16:29 -08:00
Steve Reinhardt
89ea323250
Update stats for new prefetching fixes.
...
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
2009-02-16 12:09:45 -05:00
Gabe Black
d824af340e
X86: Update stats now that the micropc isn't always reset on faults.
2009-02-01 17:02:16 -08:00
Ali Saidi
fb572a1d74
Stats: Update parser statistics for Linux special files update (parser runs should now be deterministic).
2009-01-17 18:57:39 -05:00
Gabe Black
ab5eeb4b62
Update the stats for the fixes to the PCI device class.
2008-12-15 00:47:15 -08:00
Nathan Binkert
19273164da
output: Change default output directory and files and update tests.
...
--HG--
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout
rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
2008-12-08 07:16:40 -08:00
Lisa Hsu
f1430941cf
This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
2008-12-05 12:09:29 -05:00
Steve Reinhardt
47789cc974
Update stats for brk fix (cset f28f020f3006).
2008-11-17 14:11:09 -05:00
Gabe Black
bcfd284d24
X86: Update the mcf stats.
...
I must have missed updating these for the change to send both parts of a split
packet at the same time.
2008-11-13 23:30:15 -08:00
Gabe Black
c981b7ed50
X86: Add x86 reference output for the timing CPU.
2008-11-09 21:57:15 -08:00
Lisa Hsu
92714e529f
Automated merge with ssh://daystrom.m5sim.org//repo/m5
2008-11-06 11:11:50 -05:00
Lisa Hsu
ddd179a418
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 11:11:42 -05:00
Lisa Hsu
2435918ac2
new mp eio test
2008-11-05 18:10:30 -05:00
Ali Saidi
aac93b7d0c
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-20 19:00:07 -04:00
Gabe Black
8384ff7d6c
X86: Update the stats for cpuid's new implementation
2008-10-12 15:31:37 -07:00
Nathan Binkert
d2fae026a8
tests: Update all tests for small outstanding changes.
...
Little differences have accumulated over time and it's worth getting things
back in sync for the stable release.
2008-09-28 14:16:26 -07:00
Nathan Binkert
602faeb47c
tests: rename the terminal files for solaris.
...
I forgot to do this when I renamed everything else.
--HG--
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.hconsole => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
2008-09-28 14:16:24 -07:00
Nathan Binkert
f2f40bcb77
tests: perlbmk now works. Commit stats and assume the're right.
...
Kevin fixed how O3 handles syscalls that change NextPC (longjump).
2008-09-28 14:15:50 -07:00
Nathan Binkert
bb3ab0f474
tests: Kevin fixed how writebacks are handled in SMT and that changed stats.
2008-09-28 14:15:37 -07:00
Gabe Black
30bc897613
X86: Fix the microcode for sign/zero extending moves that use high byte registers.
2008-09-03 00:52:54 -04:00
Steve Reinhardt
ab6e522032
Minor fix for test/SConscript... forgot to 'qref' before 'qdel', argh.
2008-08-04 01:01:35 -04:00
Steve Reinhardt
6f92e9b8d4
Make test/SConscript use new redirection options.
2008-08-04 00:48:11 -04:00
Nathan Binkert
50ef39af82
sockets: Add a function to disable all listening sockets.
...
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb. Expose a function to disable those ports, and have the
regression scripts disable them. There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
2008-08-03 18:19:55 -07:00
Steve Reinhardt
62c08a75ad
Make default PhysicalMemory latency slightly more realistic.
...
Also update stats to reflect change.
2008-08-03 18:13:29 -04:00
Nathan Binkert
0622eec53a
regress: update regressions for tty emulation fix.
2008-07-24 16:31:54 -07:00
Nathan Binkert
9389ede894
tests: There's a small unknown stats difference in 20.parser, accept it.
...
Hopefully if the difference pops back up, we can figure out what it was
2008-07-22 17:01:33 -04:00
Nathan Binkert
771dfecf14
Mips was missing a few stats
2008-07-22 17:00:45 -04:00
Nathan Binkert
a8df952dd3
tests: update config.ini and stdout for the various tests.
...
These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 17:00:18 -04:00
Nathan Binkert
f24f2c57b6
tests: update tests for slight changes in nsgige posted interrupts
2008-06-18 11:00:53 -04:00
Nathan Binkert
6ff4539901
Change the default output filename for the terminal so it's more obvious.
...
--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
2008-06-17 20:30:37 -07:00
Gabe Black
f58f99935a
X86: Update the regressions for the new string instructions.
2008-06-12 00:48:33 -04:00
Gabe Black
9ebd244991
X86: Update the regressions for the fact that rdtsc does something now.
2008-06-12 00:42:52 -04:00
Steve Reinhardt
3de8a78a04
Update long regression stats for semi-recent cache changes.
...
--HG--
extra : convert_revision : 7fef1e4f684ced37479ed363ebbb3a7485bc0d52
2008-03-17 23:07:22 -04:00
Steve Reinhardt
2f41006e44
Update outputs for quick tests to reflect fixed cache stats.
...
Will update long tests later.
--HG--
extra : convert_revision : 79f66b5761a574f0c8049c1c771c353b42942993
2008-02-27 18:17:37 -05:00
Gabe Black
8833b4cd44
Bus: Update the stats for the recent bus fix.
...
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 02:20:40 -05:00
Steve Reinhardt
3204f96809
Update stats for new writeback behavior.
...
--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
2008-02-16 14:58:37 -05:00
Steve Reinhardt
69ce7f953b
Update stats for some unknown minor x86 changes
...
(assuming someone just forgot to do this... tsk tsk).
--HG--
extra : convert_revision : 303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
2008-02-16 13:53:12 -05:00
Ali Saidi
48295aa514
Update long o3 regressions for o3 change in previous changeset
...
--HG--
extra : convert_revision : 00242105076eb4466cce21038858f2b9d20b2fe2
2008-01-16 11:11:55 -05:00
Steve Reinhardt
a1d5beab95
Update O3 ref outputs: very minor stats change due to previous cset.
...
(from Steve on behalf of m5test).
--HG--
extra : convert_revision : 696efdaa3dd7680dfc9c797a6a46a5053238c7d2
2008-01-15 13:13:08 -05:00
Steve Reinhardt
d4cca11bdb
Very minor memtest regression stats changes from recent coherence bug fixes.
...
--HG--
extra : convert_revision : 5e7f8ce91ea8f98e6503ac9e10aae68c62f9e510
2008-01-02 15:35:09 -08:00
Gabe Black
948269d8aa
X86: Update the parser reference output which has mysteriously changed again?
...
--HG--
extra : convert_revision : 9b1439096509633d6e9b5bc0c661608f40a63c5f
2007-12-03 14:33:33 -08:00
Gabe Black
fa5e3b47c8
SPARC: Fix the initial stack to match what the Linux kernel does.
...
--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
2007-11-29 00:00:26 -08:00
Gabe Black
16e99e4677
SPARC: Combine the 64 and 32 bit process initialization code.
...
Alignment is done as it was for 32 bit processes.
--HG--
extra : convert_revision : 9368ad40dcc7911f8fc7ec1468c6a28aa92d196f
2007-11-29 00:00:02 -08:00
Steve Reinhardt
21a99af009
Update memtest results due to new deferred-target-promotion fix.
...
Turned out this scenario was happening, but due to other activity,
the writable block returned by the ReadResp would get downgraded
or invalidated before the "unnecessary" ReadExResp/UpgradeResp
returned, thus avoiding triggering the assertion that led us to
catch this.
--HG--
extra : convert_revision : 19dd0dbedb0227aed29da31a868ddf5ca4c50519
2007-11-16 20:10:33 -08:00
Gabe Black
851c4bc960
X86: Forgot to update the hello world stats after adding cda microops.
...
--HG--
extra : convert_revision : d3dd6545d3f8b91adfc03d2e0150996672f4e29b
2007-10-26 13:53:03 -07:00
Gabe Black
7d396b1bf6
X86: Use the cda microop where appropriate. The ENTER instruction still needs these.
...
--HG--
extra : convert_revision : c5a1a6d66c454f252d3b798c38a6798e7dd486f0
2007-10-22 14:39:40 -07:00
Gabe Black
43cb78004b
X86: Start using the stupd microop, and update statistics accordingly.
...
--HG--
extra : convert_revision : 4aa9daa4e19acfb3e6840ce5d83cf199e30c2f19
2007-10-21 18:45:46 -07:00
Gabe Black
6010f350a4
X86: Add a bzip2 regression.
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--HG--
extra : convert_revision : 4bf3f68dbef033e5d4984299bb4aa728fa0d1f8d
2007-10-16 18:06:17 -07:00
Gabe Black
e87336cc60
X86: Fix the parser stats which myseriously differ even for the revision they came from.
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--HG--
extra : convert_revision : bd5fbeeea319bffbc60dcd45ef19603b09fc71ce
2007-10-16 18:04:46 -07:00
Gabe Black
8b35bd6fe7
X86: Add 5 new x86 regressions.
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--HG--
extra : convert_revision : 02f93ab039144b4586983ab76d27b7d051643e0e
2007-10-12 13:16:24 -07:00
Gabe Black
917d82eab9
Regressions: Make mcf have 256MB which it needs for 64 bit builds.
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--HG--
extra : convert_revision : 42851d60a4c1e709d79bbd3187227b6e220a253e
2007-10-10 17:12:40 -07:00
Ali Saidi
272d867402
Update statistics for the last three revisions
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--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24
2007-09-28 13:22:34 -04:00
Gabe Black
b84704173e
SPARC: Update the statistics for the SPARC gzip benchmark in o3.
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--HG--
extra : convert_revision : fd4709351b929e6a9e13dd27c17188616e4d86bb
2007-08-27 18:31:36 -07:00
Gabe Black
a51e2fd8bd
Stats: Update the stats.
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--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-26 20:27:53 -07:00
Ali Saidi
0cb32aadb1
Regression: Update EIO simple-timing test for new cache.
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--HG--
extra : convert_revision : b64f407f7735706b1162f6a0e7676590bda3ba5d
2007-08-14 14:02:22 -04:00
Ali Saidi
b634e81496
Regression: Update insttest regressions for new cache.
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--HG--
extra : convert_revision : 100478b2ae00d9d3464c41d940276843a226422f
2007-08-14 00:16:08 -04:00
Ali Saidi
51ac4d1fb5
Regression: Use test-progs in /dist instead of tests/test-progs since they all aren't there.
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--HG--
extra : convert_revision : 558b970f522f95e3492b7225f227c96cd5e003c3
2007-08-14 00:14:03 -04:00
Ali Saidi
d114e5fae6
Regression: Update stats for cache changes.
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--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
2007-08-12 19:43:55 -04:00
Ali Saidi
9493501fdb
Regression: Add an I/O Cache to the full system regressions that have a cache.
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--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
2007-08-10 16:14:02 -04:00
Steve Reinhardt
bb3f7dc83b
tests: new ref outputs for new cache model
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--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-03 18:04:30 -04:00
Steve Reinhardt
851e3c852b
tests: replace all dest ref files on upgrade (if possible).
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Originally we were copying all source files in, but this caused
problems when (large) inputs were copied along with outputs.
Then we switched to just copying the standard files (m5stats.txt,
etc.) but that was missing things like the *.console files.
This fix should catch all the non-standard files too as long as
they are copied in manually once when the test is set up.
Also get a lot nicer about warning when files are ignored,
and warn when expected files are missing.
Those new Python sets sure are handy.
--HG--
extra : convert_revision : 55c046de124522499af74a471968677c020bbf38
2007-08-03 18:04:26 -04:00
Steve Reinhardt
a0bf2535a8
tests: config.out no longer exists, eliminate ref copy.
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--HG--
extra : convert_revision : e2d6aa61aa2ffd1a9d16260244512eeb1fe4d5a3
2007-08-03 18:03:59 -04:00
Gabe Black
8da3e0548e
Merge with head.
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--HG--
extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
2007-08-01 15:12:07 -07:00
Gabe Black
c1fa2b156b
Fix for new parameter stuff.
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--HG--
extra : convert_revision : 49d8df7235a02b71db9d309e6b2029587c3d0c8b
2007-08-01 12:02:08 -07:00