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tests: update tests for TLB unification

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This commit is contained in:
Nathan Binkert 2009-04-08 22:21:30 -07:00
parent e0de2c3443
commit 374ba9bae3
197 changed files with 1885 additions and 1171 deletions
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4
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:15:58
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:37:48
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 309694 # Simulator instruction rate (inst/s)
host_mem_usage 206028 # Number of bytes of host memory used
host_seconds 1826.17 # Real time elapsed on the host
host_tick_rate 91491135 # Simulator tick rate (ticks/s)
host_inst_rate 312901 # Simulator instruction rate (inst/s)
host_mem_usage 206004 # Number of bytes of host memory used
host_seconds 1807.45 # Real time elapsed on the host
host_tick_rate 92438667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.167078 # Number of seconds simulated
@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 123896058 # Nu
system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 163077390 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 163013880 # DTB hits
system.cpu.dtb.misses 63510 # DTB misses
system.cpu.dtb.data_accesses 163077390 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 163013880 # DTB hits
system.cpu.dtb.data_misses 63510 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 122284109 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 122260496 # DTB read hits
@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 53519286 # Nu
system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 66014446 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 66014406 # ITB hits
system.cpu.itb.misses 40 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 66014446 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 66014406 # ITB hits
system.cpu.itb.fetch_misses 40 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency

4
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:34:49
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 6175770 # Simulator instruction rate (inst/s)
host_mem_usage 195684 # Number of bytes of host memory used
host_seconds 97.45 # Real time elapsed on the host
host_tick_rate 3087904278 # Simulator tick rate (ticks/s)
host_inst_rate 5975527 # Simulator instruction rate (inst/s)
host_mem_usage 197448 # Number of bytes of host memory used
host_seconds 100.72 # Real time elapsed on the host
host_tick_rate 2987780856 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
system.cpu.dtb.accesses 153970296 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 153965363 # DTB hits
system.cpu.dtb.misses 4933 # DTB misses
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 601861917 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 601861897 # ITB hits
system.cpu.itb.misses 20 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 601861917 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 601861897 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed

4
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

10
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:34:42
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1969135 # Simulator instruction rate (inst/s)
host_mem_usage 203124 # Number of bytes of host memory used
host_seconds 305.65 # Real time elapsed on the host
host_tick_rate 2545444210 # Simulator tick rate (ticks/s)
host_inst_rate 3011769 # Simulator instruction rate (inst/s)
host_mem_usage 204988 # Number of bytes of host memory used
host_seconds 199.84 # Real time elapsed on the host
host_tick_rate 3893225431 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated
@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4094.195523 # Cy
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.dtb.accesses 153970296 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 153965363 # DTB hits
system.cpu.dtb.misses 4933 # DTB misses
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
@ -137,10 +141,22 @@ system.cpu.icache.total_refs 601861103 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 601861918 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 601861898 # ITB hits
system.cpu.itb.misses 20 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 601861918 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 601861898 # ITB hits
system.cpu.itb.fetch_misses 20 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency

4
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.l2cache]

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 16 2009 00:51:12
M5 revision 208de84f046d 6013 default tip
M5 started Mar 16 2009 00:51:29
M5 executing on zizzer
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:04
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 159348 # Simulator instruction rate (inst/s)
host_mem_usage 206344 # Number of bytes of host memory used
host_seconds 8821.04 # Real time elapsed on the host
host_tick_rate 125003315 # Simulator tick rate (ticks/s)
host_inst_rate 150366 # Simulator instruction rate (inst/s)
host_mem_usage 208016 # Number of bytes of host memory used
host_seconds 9347.96 # Real time elapsed on the host
host_tick_rate 117957212 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618365 # Number of instructions simulated
sim_seconds 1.102659 # Number of seconds simulated

4
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.tracer]

10
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:46:25
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:31:00
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3714547 # Simulator instruction rate (inst/s)
host_mem_usage 197792 # Number of bytes of host memory used
host_seconds 401.00 # Real time elapsed on the host
host_tick_rate 1857278454 # Simulator tick rate (ticks/s)
host_inst_rate 3659022 # Simulator instruction rate (inst/s)
host_mem_usage 199544 # Number of bytes of host memory used
host_seconds 407.08 # Real time elapsed on the host
host_tick_rate 1829515892 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated

4
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.l2cache]

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 16 2009 00:51:12
M5 revision 208de84f046d 6013 default tip
M5 started Mar 16 2009 00:51:29
M5 executing on zizzer
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:32:24
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1328193 # Simulator instruction rate (inst/s)
host_mem_usage 205396 # Number of bytes of host memory used
host_seconds 1121.47 # Real time elapsed on the host
host_tick_rate 1851148785 # Simulator tick rate (ticks/s)
host_inst_rate 1898996 # Simulator instruction rate (inst/s)
host_mem_usage 207084 # Number of bytes of host memory used
host_seconds 784.37 # Real time elapsed on the host
host_tick_rate 2646697045 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.076001 # Number of seconds simulated

4
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.tracer]

10
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2009 22:05:32
M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
M5 started Feb 24 2009 22:07:57
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:59:49
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1045935 # Simulator instruction rate (inst/s)
host_mem_usage 197296 # Number of bytes of host memory used
host_seconds 1548.25 # Real time elapsed on the host
host_tick_rate 621947296 # Simulator tick rate (ticks/s)
host_inst_rate 2819266 # Simulator instruction rate (inst/s)
host_mem_usage 199720 # Number of bytes of host memory used
host_seconds 574.39 # Real time elapsed on the host
host_tick_rate 1676428354 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 0.962929 # Number of seconds simulated

4
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.l2cache]

10
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2009 22:05:32
M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
M5 started Feb 24 2009 22:07:57
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 13:09:59
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 660241 # Simulator instruction rate (inst/s)
host_mem_usage 204740 # Number of bytes of host memory used
host_seconds 2452.69 # Real time elapsed on the host
host_tick_rate 739961389 # Simulator tick rate (ticks/s)
host_inst_rate 1747793 # Simulator instruction rate (inst/s)
host_mem_usage 207260 # Number of bytes of host memory used
host_seconds 926.52 # Real time elapsed on the host
host_tick_rate 1958830620 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 1.814897 # Number of seconds simulated

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -158,7 +158,7 @@ cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu0.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu0.fuPool]
@ -334,7 +334,7 @@ mem_side=system.toL2Bus.port[1]
type=AlphaInterrupts
[system.cpu0.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu0.tracer]
@ -465,7 +465,7 @@ cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
[system.cpu1.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu1.fuPool]
@ -641,7 +641,7 @@ mem_side=system.toL2Bus.port[3]
type=AlphaInterrupts
[system.cpu1.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu1.tracer]

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:39
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:15:43
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:05
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...

72
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 195579 # Simulator instruction rate (inst/s)
host_mem_usage 296668 # Number of bytes of host memory used
host_seconds 287.30 # Real time elapsed on the host
host_tick_rate 6640015618 # Simulator tick rate (ticks/s)
host_inst_rate 198409 # Simulator instruction rate (inst/s)
host_mem_usage 296696 # Number of bytes of host memory used
host_seconds 283.21 # Real time elapsed on the host
host_tick_rate 6736112914 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56190549 # Number of instructions simulated
sim_seconds 1.907705 # Number of seconds simulated
@ -146,10 +146,14 @@ system.cpu0.decode.DECODE:RunCycles 9143957 # Nu
system.cpu0.decode.DECODE:SquashCycles 1094068 # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking
system.cpu0.dtb.accesses 812672 # DTB accesses
system.cpu0.dtb.acv 801 # DTB access violations
system.cpu0.dtb.hits 11625470 # DTB hits
system.cpu0.dtb.misses 28525 # DTB misses
system.cpu0.dtb.data_accesses 812672 # DTB accesses
system.cpu0.dtb.data_acv 801 # DTB access violations
system.cpu0.dtb.data_hits 11625470 # DTB hits
system.cpu0.dtb.data_misses 28525 # DTB misses
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.read_accesses 605265 # DTB read accesses
system.cpu0.dtb.read_acv 596 # DTB read access violations
system.cpu0.dtb.read_hits 7063685 # DTB read hits
@ -343,10 +347,22 @@ system.cpu0.iq.iqSquashedInstsExamined 5737873 # Nu
system.cpu0.iq.iqSquashedInstsIssued 23379 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined 3058467 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.accesses 875811 # ITB accesses
system.cpu0.itb.acv 900 # ITB acv
system.cpu0.itb.hits 845925 # ITB hits
system.cpu0.itb.misses 29886 # ITB misses
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.fetch_accesses 875811 # ITB accesses
system.cpu0.itb.fetch_acv 900 # ITB acv
system.cpu0.itb.fetch_hits 845925 # ITB hits
system.cpu0.itb.fetch_misses 29886 # ITB misses
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.kern.callpal 129578 # number of callpals executed
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed
@ -596,10 +612,14 @@ system.cpu1.decode.DECODE:RunCycles 4724229 # Nu
system.cpu1.decode.DECODE:SquashCycles 641522 # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking
system.cpu1.dtb.accesses 433929 # DTB accesses
system.cpu1.dtb.acv 77 # DTB access violations
system.cpu1.dtb.hits 6280849 # DTB hits
system.cpu1.dtb.misses 17153 # DTB misses
system.cpu1.dtb.data_accesses 433929 # DTB accesses
system.cpu1.dtb.data_acv 77 # DTB access violations
system.cpu1.dtb.data_hits 6280849 # DTB hits
system.cpu1.dtb.data_misses 17153 # DTB misses
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.read_accesses 314117 # DTB read accesses
system.cpu1.dtb.read_acv 13 # DTB read access violations
system.cpu1.dtb.read_hits 3872885 # DTB read hits
@ -793,10 +813,22 @@ system.cpu1.iq.iqSquashedInstsExamined 3483485 # Nu
system.cpu1.iq.iqSquashedInstsIssued 16725 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined 1773520 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.accesses 525294 # ITB accesses
system.cpu1.itb.acv 109 # ITB acv
system.cpu1.itb.hits 518481 # ITB hits
system.cpu1.itb.misses 6813 # ITB misses
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.fetch_accesses 525294 # ITB accesses
system.cpu1.itb.fetch_acv 109 # ITB acv
system.cpu1.itb.fetch_hits 518481 # ITB hits
system.cpu1.itb.fetch_misses 6813 # ITB misses
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.kern.callpal 87355 # number of callpals executed
system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed

4
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -158,7 +158,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -334,7 +334,7 @@ mem_side=system.toL2Bus.port[1]
type=AlphaInterrupts
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:39
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:15:42
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:19
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...

40
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 203131 # Simulator instruction rate (inst/s)
host_mem_usage 294692 # Number of bytes of host memory used
host_seconds 261.36 # Real time elapsed on the host
host_tick_rate 7144744614 # Simulator tick rate (ticks/s)
host_inst_rate 201864 # Simulator instruction rate (inst/s)
host_mem_usage 294704 # Number of bytes of host memory used
host_seconds 263.00 # Real time elapsed on the host
host_tick_rate 7100171671 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53090630 # Number of instructions simulated
sim_seconds 1.867363 # Number of seconds simulated
@ -146,10 +146,14 @@ system.cpu.decode.DECODE:RunCycles 13077120 # Nu
system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 1236420 # DTB accesses
system.cpu.dtb.acv 825 # DTB access violations
system.cpu.dtb.hits 16772347 # DTB hits
system.cpu.dtb.misses 44495 # DTB misses
system.cpu.dtb.data_accesses 1236420 # DTB accesses
system.cpu.dtb.data_acv 825 # DTB access violations
system.cpu.dtb.data_hits 16772347 # DTB hits
system.cpu.dtb.data_misses 44495 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 910052 # DTB read accesses
system.cpu.dtb.read_acv 586 # DTB read access violations
system.cpu.dtb.read_hits 10174508 # DTB read hits
@ -343,10 +347,22 @@ system.cpu.iq.iqSquashedInstsExamined 8738375 # Nu
system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 1303895 # ITB accesses
system.cpu.itb.acv 943 # ITB acv
system.cpu.itb.hits 1264480 # ITB hits
system.cpu.itb.misses 39415 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1303895 # ITB accesses
system.cpu.itb.fetch_acv 943 # ITB acv
system.cpu.itb.fetch_hits 1264480 # ITB hits
system.cpu.itb.fetch_misses 39415 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal 192656 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed

4
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.tracer]

10
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:51:47
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py long/10.mcf/sparc/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:33
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2414989 # Simulator instruction rate (inst/s)
host_mem_usage 329980 # Number of bytes of host memory used
host_seconds 100.97 # Real time elapsed on the host
host_tick_rate 1210444801 # Simulator tick rate (ticks/s)
host_inst_rate 3425998 # Simulator instruction rate (inst/s)
host_mem_usage 331732 # Number of bytes of host memory used
host_seconds 71.17 # Real time elapsed on the host
host_tick_rate 1717182841 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated

4
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.l2cache]

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 16 2009 00:51:12
M5 revision 208de84f046d 6013 default tip
M5 started Mar 16 2009 00:51:29
M5 executing on zizzer
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:42
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1212571 # Simulator instruction rate (inst/s)
host_mem_usage 337588 # Number of bytes of host memory used
host_seconds 201.09 # Real time elapsed on the host
host_tick_rate 1822248337 # Simulator tick rate (ticks/s)
host_inst_rate 1860125 # Simulator instruction rate (inst/s)
host_mem_usage 339272 # Number of bytes of host memory used
host_seconds 131.09 # Real time elapsed on the host
host_tick_rate 2795388911 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366435 # Number of seconds simulated

4
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.tracer]

10
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 13:07:56
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 738696 # Simulator instruction rate (inst/s)
host_mem_usage 331676 # Number of bytes of host memory used
host_seconds 365.09 # Real time elapsed on the host
host_tick_rate 451120089 # Simulator tick rate (ticks/s)
host_inst_rate 2496453 # Simulator instruction rate (inst/s)
host_mem_usage 334252 # Number of bytes of host memory used
host_seconds 108.03 # Real time elapsed on the host
host_tick_rate 1524575559 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.164697 # Number of seconds simulated

4
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.l2cache]

10
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2009 01:30:29
M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
M5 started Feb 24 2009 01:36:40
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:50:00
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 587866 # Simulator instruction rate (inst/s)
host_mem_usage 339232 # Number of bytes of host memory used
host_seconds 458.76 # Real time elapsed on the host
host_tick_rate 831860032 # Simulator tick rate (ticks/s)
host_inst_rate 1552325 # Simulator instruction rate (inst/s)
host_mem_usage 341792 # Number of bytes of host memory used
host_seconds 173.73 # Real time elapsed on the host
host_tick_rate 2196615579 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.381620 # Number of seconds simulated

4
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.tracer]

10
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:52:55
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 954040 # Simulator instruction rate (inst/s)
host_mem_usage 200820 # Number of bytes of host memory used
host_seconds 1567.53 # Real time elapsed on the host
host_tick_rate 554042856 # Simulator tick rate (ticks/s)
host_inst_rate 2610049 # Simulator instruction rate (inst/s)
host_mem_usage 203408 # Number of bytes of host memory used
host_seconds 572.97 # Real time elapsed on the host
host_tick_rate 1515741316 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 0.868476 # Number of seconds simulated

4
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.l2cache]

10
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2009 01:30:29
M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
M5 started Feb 24 2009 01:46:46
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:55:56
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 782704 # Simulator instruction rate (inst/s)
host_mem_usage 208376 # Number of bytes of host memory used
host_seconds 1910.66 # Real time elapsed on the host
host_tick_rate 901442913 # Simulator tick rate (ticks/s)
host_inst_rate 1776301 # Simulator instruction rate (inst/s)
host_mem_usage 210956 # Number of bytes of host memory used
host_seconds 841.91 # Real time elapsed on the host
host_tick_rate 2045771672 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 1.722352 # Number of seconds simulated

4
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:25:10
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:46:50
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 243217 # Simulator instruction rate (inst/s)
host_mem_usage 213460 # Number of bytes of host memory used
host_seconds 1544.20 # Real time elapsed on the host
host_tick_rate 87422028 # Simulator tick rate (ticks/s)
host_inst_rate 244825 # Simulator instruction rate (inst/s)
host_mem_usage 213432 # Number of bytes of host memory used
host_seconds 1534.05 # Real time elapsed on the host
host_tick_rate 88000012 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.134997 # Number of seconds simulated
@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 101952317 # Nu
system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 185115437 # DTB accesses
system.cpu.dtb.acv 1 # DTB access violations
system.cpu.dtb.hits 185076670 # DTB hits
system.cpu.dtb.misses 38767 # DTB misses
system.cpu.dtb.data_accesses 185115437 # DTB accesses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_hits 185076670 # DTB hits
system.cpu.dtb.data_misses 38767 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 104449499 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 104412186 # DTB read hits
@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 89615992 # Nu
system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 63866476 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 63866189 # ITB hits
system.cpu.itb.misses 287 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 63866476 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 63866189 # ITB hits
system.cpu.itb.fetch_misses 287 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency

4
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

10
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:41:56
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3515833 # Simulator instruction rate (inst/s)
host_mem_usage 203260 # Number of bytes of host memory used
host_seconds 113.39 # Real time elapsed on the host
host_tick_rate 1757913715 # Simulator tick rate (ticks/s)
host_inst_rate 5193663 # Simulator instruction rate (inst/s)
host_mem_usage 205028 # Number of bytes of host memory used
host_seconds 76.76 # Real time elapsed on the host
host_tick_rate 2596825201 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
system.cpu.dtb.accesses 168275274 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 168275218 # DTB hits
system.cpu.dtb.misses 56 # DTB misses
system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 168275218 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 94754489 # DTB read hits
@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 398664824 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 398664651 # ITB hits
system.cpu.itb.misses 173 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.num_insts 398664595 # Number of instructions executed

4
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

10
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:52
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:44:12
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1674592 # Simulator instruction rate (inst/s)
host_mem_usage 210700 # Number of bytes of host memory used
host_seconds 238.07 # Real time elapsed on the host
host_tick_rate 2383160323 # Simulator tick rate (ticks/s)
host_inst_rate 2545334 # Simulator instruction rate (inst/s)
host_mem_usage 212560 # Number of bytes of host memory used
host_seconds 156.63 # Real time elapsed on the host
host_tick_rate 3622337158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated
@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 3288.899192 # Cy
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.dtb.accesses 168275276 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 168275220 # DTB hits
system.cpu.dtb.misses 56 # DTB misses
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 168275220 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 94754490 # DTB read hits
@ -137,10 +141,22 @@ system.cpu.icache.total_refs 398660993 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 398664839 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 398664666 # ITB hits
system.cpu.itb.misses 173 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 398664839 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 398664666 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency

4
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:24:11
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:41:37
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 233158 # Simulator instruction rate (inst/s)
host_mem_usage 213372 # Number of bytes of host memory used
host_seconds 7818.92 # Real time elapsed on the host
host_tick_rate 90186298 # Simulator tick rate (ticks/s)
host_inst_rate 236247 # Simulator instruction rate (inst/s)
host_mem_usage 213344 # Number of bytes of host memory used
host_seconds 7716.70 # Real time elapsed on the host
host_tick_rate 91380999 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.705159 # Number of seconds simulated
@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 561391036 # Nu
system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 775959987 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 775335043 # DTB hits
system.cpu.dtb.misses 624944 # DTB misses
system.cpu.dtb.data_accesses 775959987 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 775335043 # DTB hits
system.cpu.dtb.data_misses 624944 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 516992085 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 516404963 # DTB read hits
@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 562621267 # Nu
system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 348448092 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 348447899 # ITB hits
system.cpu.itb.misses 193 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 348448092 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 348447899 # ITB hits
system.cpu.itb.fetch_misses 193 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency

4
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

10
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:38:04
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3467416 # Simulator instruction rate (inst/s)
host_mem_usage 202428 # Number of bytes of host memory used
host_seconds 579.39 # Real time elapsed on the host
host_tick_rate 1734081372 # Simulator tick rate (ticks/s)
host_inst_rate 5314394 # Simulator instruction rate (inst/s)
host_mem_usage 204196 # Number of bytes of host memory used
host_seconds 378.03 # Real time elapsed on the host
host_tick_rate 2657768720 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated
sim_ticks 1004710587000 # Number of ticks simulated
system.cpu.dtb.accesses 722298387 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 721864922 # DTB hits
system.cpu.dtb.misses 433465 # DTB misses
system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 721864922 # DTB hits
system.cpu.dtb.data_misses 433465 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 511070026 # DTB read hits
@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 210794896 # DTB write hits
system.cpu.dtb.write_misses 14581 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2009421175 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2009421070 # ITB hits
system.cpu.itb.misses 105 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 2009421175 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 2009421070 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.num_insts 2008987605 # Number of instructions executed

4
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

10
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:29:29
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:45:29
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2199489 # Simulator instruction rate (inst/s)
host_mem_usage 209876 # Number of bytes of host memory used
host_seconds 913.39 # Real time elapsed on the host
host_tick_rate 3081877276 # Simulator tick rate (ticks/s)
host_inst_rate 2595694 # Simulator instruction rate (inst/s)
host_mem_usage 211736 # Number of bytes of host memory used
host_seconds 773.97 # Real time elapsed on the host
host_tick_rate 3637030411 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated
@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4095.198740 # Cy
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.dtb.accesses 722298387 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 721864922 # DTB hits
system.cpu.dtb.misses 433465 # DTB misses
system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 721864922 # DTB hits
system.cpu.dtb.data_misses 433465 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 511070026 # DTB read hits
@ -137,10 +141,22 @@ system.cpu.icache.total_refs 2009410475 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2009421176 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2009421071 # ITB hits
system.cpu.itb.misses 105 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 2009421071 # ITB hits
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency

4
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:23:18
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:36:30
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 261905 # Simulator instruction rate (inst/s)
host_mem_usage 216920 # Number of bytes of host memory used
host_seconds 303.90 # Real time elapsed on the host
host_tick_rate 89289765 # Simulator tick rate (ticks/s)
host_inst_rate 259851 # Simulator instruction rate (inst/s)
host_mem_usage 216888 # Number of bytes of host memory used
host_seconds 306.30 # Real time elapsed on the host
host_tick_rate 88589448 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated
@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 19520694 # Nu
system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 36599689 # DTB accesses
system.cpu.dtb.acv 39 # DTB access violations
system.cpu.dtb.hits 36425481 # DTB hits
system.cpu.dtb.misses 174208 # DTB misses
system.cpu.dtb.data_accesses 36599689 # DTB accesses
system.cpu.dtb.data_acv 39 # DTB access violations
system.cpu.dtb.data_hits 36425481 # DTB hits
system.cpu.dtb.data_misses 174208 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 21541288 # DTB read accesses
system.cpu.dtb.read_acv 37 # DTB read access violations
system.cpu.dtb.read_hits 21383020 # DTB read hits
@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 9777311 # Nu
system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 13412237 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 13386072 # ITB hits
system.cpu.itb.misses 26165 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 13412237 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 13386072 # ITB hits
system.cpu.itb.fetch_misses 26165 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency

4
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

10
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:31:50
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:43:53
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5386925 # Simulator instruction rate (inst/s)
host_mem_usage 205832 # Number of bytes of host memory used
host_seconds 16.40 # Real time elapsed on the host
host_tick_rate 2696520513 # Simulator tick rate (ticks/s)
host_inst_rate 5274353 # Simulator instruction rate (inst/s)
host_mem_usage 207596 # Number of bytes of host memory used
host_seconds 16.75 # Real time elapsed on the host
host_tick_rate 2640164541 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44221003000 # Number of ticks simulated
system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 34890015 # DTB hits
system.cpu.dtb.misses 97400 # DTB misses
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 88442007 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 88438073 # ITB hits
system.cpu.itb.misses 3934 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 88442007 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 88438073 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed

4
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

10
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:32:07
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:03
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2514121 # Simulator instruction rate (inst/s)
host_mem_usage 213276 # Number of bytes of host memory used
host_seconds 35.14 # Real time elapsed on the host
host_tick_rate 3846798027 # Simulator tick rate (ticks/s)
host_inst_rate 2447162 # Simulator instruction rate (inst/s)
host_mem_usage 215136 # Number of bytes of host memory used
host_seconds 36.10 # Real time elapsed on the host
host_tick_rate 3744340356 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated
@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4078.872537 # Cy
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 34890015 # DTB hits
system.cpu.dtb.misses 97400 # DTB misses
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
@ -137,10 +141,22 @@ system.cpu.icache.total_refs 88361638 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 88442008 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 88438074 # ITB hits
system.cpu.itb.misses 3934 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 88442008 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 88438074 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency

4
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.tracer]

10
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:53:28
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:31:45
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3821272 # Simulator instruction rate (inst/s)
host_mem_usage 206688 # Number of bytes of host memory used
host_seconds 35.63 # Real time elapsed on the host
host_tick_rate 1912846403 # Simulator tick rate (ticks/s)
host_inst_rate 3453262 # Simulator instruction rate (inst/s)
host_mem_usage 208432 # Number of bytes of host memory used
host_seconds 39.42 # Real time elapsed on the host
host_tick_rate 1728626295 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated

4
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
type=SparcTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
type=SparcTLB
size=64
[system.cpu.l2cache]

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 16 2009 00:51:12
M5 revision 208de84f046d 6013 default tip
M5 started Mar 16 2009 00:51:29
M5 executing on zizzer
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:34
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1347607 # Simulator instruction rate (inst/s)
host_mem_usage 214288 # Number of bytes of host memory used
host_seconds 101.02 # Real time elapsed on the host
host_tick_rate 2013168641 # Simulator tick rate (ticks/s)
host_inst_rate 1887759 # Simulator instruction rate (inst/s)
host_mem_usage 215972 # Number of bytes of host memory used
host_seconds 72.12 # Real time elapsed on the host
host_tick_rate 2820090693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.203377 # Number of seconds simulated

4
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:18:05
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:33:27
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 226973 # Simulator instruction rate (inst/s)
host_mem_usage 205820 # Number of bytes of host memory used
host_seconds 7648.67 # Real time elapsed on the host
host_tick_rate 97050740 # Simulator tick rate (ticks/s)
host_inst_rate 226919 # Simulator instruction rate (inst/s)
host_mem_usage 205788 # Number of bytes of host memory used
host_seconds 7650.48 # Real time elapsed on the host
host_tick_rate 97027777 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.742309 # Number of seconds simulated
@ -131,10 +131,14 @@ system.cpu.decode.DECODE:RunCycles 549143104 # Nu
system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 768331639 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 752318838 # DTB hits
system.cpu.dtb.misses 16012801 # DTB misses
system.cpu.dtb.data_accesses 768331639 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 752318838 # DTB hits
system.cpu.dtb.data_misses 16012801 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 566617551 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 557381525 # DTB read hits
@ -327,10 +331,22 @@ system.cpu.iq.iqSquashedInstsExamined 739697610 # Nu
system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 355180552 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 355180518 # ITB hits
system.cpu.itb.misses 34 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 355180552 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 355180518 # ITB hits
system.cpu.itb.fetch_misses 34 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency

4
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

10
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:32:58
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:44:24
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3629734 # Simulator instruction rate (inst/s)
host_mem_usage 195600 # Number of bytes of host memory used
host_seconds 501.35 # Real time elapsed on the host
host_tick_rate 1821446907 # Simulator tick rate (ticks/s)
host_inst_rate 5417867 # Simulator instruction rate (inst/s)
host_mem_usage 197364 # Number of bytes of host memory used
host_seconds 335.89 # Real time elapsed on the host
host_tick_rate 2718753958 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 913189263000 # Number of ticks simulated
system.cpu.dtb.accesses 611922547 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 605324165 # DTB hits
system.cpu.dtb.misses 6598382 # DTB misses
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 444595663 # DTB read hits
@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 1826378527 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 1826378509 # ITB hits
system.cpu.itb.misses 18 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1826378527 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 1826378509 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed

4
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

10
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:36:09
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py long/60.bzip2/alpha/tru64/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:43:13
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2148631 # Simulator instruction rate (inst/s)
host_mem_usage 203048 # Number of bytes of host memory used
host_seconds 846.95 # Real time elapsed on the host
host_tick_rate 3220962828 # Simulator tick rate (ticks/s)
host_inst_rate 2385042 # Simulator instruction rate (inst/s)
host_mem_usage 204904 # Number of bytes of host memory used
host_seconds 763.00 # Real time elapsed on the host
host_tick_rate 3575360927 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.727991 # Number of seconds simulated
@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4079.892573 # Cy
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks
system.cpu.dtb.accesses 611922547 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 605324165 # DTB hits
system.cpu.dtb.misses 6598382 # DTB misses
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 444595663 # DTB read hits
@ -137,10 +141,22 @@ system.cpu.icache.total_refs 1826377708 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 1826378528 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 1826378510 # ITB hits
system.cpu.itb.misses 18 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency

4
tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.tracer]

10
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 13:09:24
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1367500 # Simulator instruction rate (inst/s)
host_mem_usage 197040 # Number of bytes of host memory used
host_seconds 3402.69 # Real time elapsed on the host
host_tick_rate 831449663 # Simulator tick rate (ticks/s)
host_inst_rate 2554726 # Simulator instruction rate (inst/s)
host_mem_usage 199616 # Number of bytes of host memory used
host_seconds 1821.40 # Real time elapsed on the host
host_tick_rate 1553291459 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176258 # Number of instructions simulated
sim_seconds 2.829164 # Number of seconds simulated

4
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=X86DTB
type=X86TLB
size=64
[system.cpu.icache]
@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=X86ITB
type=X86TLB
size=64
[system.cpu.l2cache]

10
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2009 01:30:29
M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
M5 started Feb 24 2009 01:30:32
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 13:02:28
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 929786 # Simulator instruction rate (inst/s)
host_mem_usage 204596 # Number of bytes of host memory used
host_seconds 5004.56 # Real time elapsed on the host
host_tick_rate 1196520405 # Simulator tick rate (ticks/s)
host_inst_rate 1632111 # Simulator instruction rate (inst/s)
host_mem_usage 207156 # Number of bytes of host memory used
host_seconds 2851.02 # Real time elapsed on the host
host_tick_rate 2100325473 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176258 # Number of instructions simulated
sim_seconds 5.988064 # Number of seconds simulated

4
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.fuPool]
@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.l2cache]

8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 6 2009 18:15:46
M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
M5 started Mar 6 2009 18:16:08
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:37:03
M5 executing on maize
command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

40
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 205423 # Simulator instruction rate (inst/s)
host_mem_usage 211084 # Number of bytes of host memory used
host_seconds 409.79 # Real time elapsed on the host
host_tick_rate 99609545 # Simulator tick rate (ticks/s)
host_inst_rate 205890 # Simulator instruction rate (inst/s)
host_mem_usage 211060 # Number of bytes of host memory used
host_seconds 408.86 # Real time elapsed on the host
host_tick_rate 99836021 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040819 # Number of seconds simulated
@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 29917869 # Nu
system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 31911121 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 31454022 # DTB hits
system.cpu.dtb.misses 457099 # DTB misses
system.cpu.dtb.data_accesses 31911121 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 31454022 # DTB hits
system.cpu.dtb.data_misses 457099 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 24718123 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 24262026 # DTB read hits
@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 50669408 # Nu
system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 19230073 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 19230003 # ITB hits
system.cpu.itb.misses 70 # ITB misses
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 19230073 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 19230003 # ITB hits
system.cpu.itb.fetch_misses 70 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency

4
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
type=AlphaTLB
size=64
[system.cpu.itb]
type=AlphaITB
type=AlphaTLB
size=48
[system.cpu.tracer]

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