217 lines
24 KiB
Text
217 lines
24 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1860125 # Simulator instruction rate (inst/s)
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host_mem_usage 339272 # Number of bytes of host memory used
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host_seconds 131.09 # Real time elapsed on the host
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host_tick_rate 2795388911 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 243835278 # Number of instructions simulated
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sim_seconds 0.366435 # Number of seconds simulated
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sim_ticks 366435406000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 104134565 # number of overall hits
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system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 987820 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 935475 # number of replacements
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system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use
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system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 94877 # number of writebacks
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system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
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system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 244420630 # number of overall hits
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system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 882 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 25 # number of replacements
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system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use
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system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 892653 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 47800 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 891 # number of replacements
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system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 41 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 732870812 # number of cpu cycles simulated
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system.cpu.num_insts 243835278 # Number of instructions executed
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system.cpu.num_refs 105711442 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
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---------- End Simulation Statistics ----------
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