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Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.

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This commit is contained in:
Lisa Hsu 2008-11-06 11:11:42 -05:00
parent 46b56bb7b6
commit ddd179a418
208 changed files with 884 additions and 1160 deletions
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9
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4206850 # Nu
global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted
global.BPredUnit.lookups 76039028 # Number of BP lookups
global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
host_inst_rate 225803 # Simulator instruction rate (inst/s)
host_mem_usage 201396 # Number of bytes of host memory used
host_seconds 2504.62 # Real time elapsed on the host
host_tick_rate 66707870 # Simulator tick rate (ticks/s)
host_inst_rate 204243 # Simulator instruction rate (inst/s)
host_mem_usage 202188 # Number of bytes of host memory used
host_seconds 2769.01 # Real time elapsed on the host
host_tick_rate 60338522 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit.

1
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:09:41
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 21:40:15
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2906348 # Simulator instruction rate (inst/s)
host_mem_usage 174252 # Number of bytes of host memory used
host_seconds 207.08 # Real time elapsed on the host
host_tick_rate 1453183573 # Simulator tick rate (ticks/s)
host_inst_rate 3818661 # Simulator instruction rate (inst/s)
host_mem_usage 193720 # Number of bytes of host memory used
host_seconds 157.61 # Real time elapsed on the host
host_tick_rate 1909343313 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated

1
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:12:32
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:05:35
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

9
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1676744 # Simulator instruction rate (inst/s)
host_mem_usage 200380 # Number of bytes of host memory used
host_seconds 358.94 # Real time elapsed on the host
host_tick_rate 2167478980 # Simulator tick rate (ticks/s)
host_inst_rate 1993278 # Simulator instruction rate (inst/s)
host_mem_usage 201176 # Number of bytes of host memory used
host_seconds 301.94 # Real time elapsed on the host
host_tick_rate 2576653236 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated

1
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:14:02
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:08:13
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

9
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 83681535 # Nu
global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
global.BPredUnit.lookups 254458067 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 99984 # Simulator instruction rate (inst/s)
host_mem_usage 203500 # Number of bytes of host memory used
host_seconds 14058.38 # Real time elapsed on the host
host_tick_rate 78434309 # Simulator tick rate (ticks/s)
host_inst_rate 116972 # Simulator instruction rate (inst/s)
host_mem_usage 204276 # Number of bytes of host memory used
host_seconds 12016.73 # Real time elapsed on the host
host_tick_rate 91760367 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.

2
tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: be nice to actually delete the event here

11
tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:21:26
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:55:58
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 4187360 # Simulator instruction rate (inst/s)
host_mem_usage 206704 # Number of bytes of host memory used
host_seconds 355.72 # Real time elapsed on the host
host_tick_rate 2093685937 # Simulator tick rate (ticks/s)
host_inst_rate 2833353 # Simulator instruction rate (inst/s)
host_mem_usage 195884 # Number of bytes of host memory used
host_seconds 525.71 # Real time elapsed on the host
host_tick_rate 1416680719 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated

2
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: be nice to actually delete the event here

11
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:22:26
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:45:38
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

9
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1927863 # Simulator instruction rate (inst/s)
host_mem_usage 202560 # Number of bytes of host memory used
host_seconds 772.63 # Real time elapsed on the host
host_tick_rate 2692643700 # Simulator tick rate (ticks/s)
host_inst_rate 2121797 # Simulator instruction rate (inst/s)
host_mem_usage 203340 # Number of bytes of host memory used
host_seconds 702.01 # Real time elapsed on the host
host_tick_rate 2963511011 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.080416 # Number of seconds simulated

2
tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: be nice to actually delete the event here

11
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:25:17
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:41:13
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1864345 # Simulator instruction rate (inst/s)
host_mem_usage 194404 # Number of bytes of host memory used
host_seconds 868.62 # Real time elapsed on the host
host_tick_rate 1108605034 # Simulator tick rate (ticks/s)
host_inst_rate 1613706 # Simulator instruction rate (inst/s)
host_mem_usage 195008 # Number of bytes of host memory used
host_seconds 1003.53 # Real time elapsed on the host
host_tick_rate 959566027 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619398860 # Number of instructions simulated
sim_seconds 0.962952 # Number of seconds simulated

2
tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'prefetch_t0' unimplemented
@ -7,3 +6,4 @@ warn: instruction 'prefetch_t0' unimplemented
warn: instruction 'prefetch_t0' unimplemented
warn: instruction 'prefetch_t0' unimplemented
warn: Increasing stack size by one page.
warn: be nice to actually delete the event here

11
tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 8 2008 20:20:37
M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617
M5 commit date Wed Oct 08 20:18:02 2008 -0700
M5 started Oct 8 2008 20:20:39
M5 executing on tater
M5 compiled Nov 5 2008 23:03:02
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 23:03:28
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Duplicating 262144 bytes

18
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -132,7 +132,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -150,8 +149,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -309,7 +306,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -327,8 +323,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -446,7 +440,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -464,8 +457,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -623,7 +614,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -641,8 +631,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -722,7 +710,6 @@ block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
@ -740,8 +727,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
@ -758,7 +743,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
@ -776,8 +760,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=4194304
split=false
split_size=0
subblock_size=0
tgts_per_mshr=16
trace_addr=0

102
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt
View file

@ -16,10 +16,10 @@ global.BPredUnit.lookups 10092697 # Nu
global.BPredUnit.lookups 5530798 # Number of BP lookups
global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target.
global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target.
host_inst_rate 132625 # Simulator instruction rate (inst/s)
host_mem_usage 292844 # Number of bytes of host memory used
host_seconds 423.41 # Real time elapsed on the host
host_tick_rate 4505618304 # Simulator tick rate (ticks/s)
host_inst_rate 130617 # Simulator instruction rate (inst/s)
host_mem_usage 292856 # Number of bytes of host memory used
host_seconds 429.91 # Real time elapsed on the host
host_tick_rate 4437424208 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores.
@ -211,13 +211,13 @@ system.cpu0.fetch.rateDist.end_dist
system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.489789 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency 7526812999 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked
@ -230,13 +230,13 @@ system.cpu0.icache.blocked_cycles_no_targets 0
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses
system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 7526812999 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
@ -244,14 +244,14 @@ system.cpu0.icache.mshr_cap_events 0 # nu
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12131.489789 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits 5806036 # number of overall hits
system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses
system.cpu0.icache.overall_misses 650298 # number of overall misses
system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 7526812999 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -272,7 +272,7 @@ system.cpu0.icache.tagsinuse 509.829045 # Cy
system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
system.cpu0.idleCycles 30377938 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed
system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed
system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate
@ -413,9 +413,9 @@ system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # nu
system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0 1871607297000 98.13% 98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22 397999500 0.02% 98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl
@ -467,7 +467,7 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu
system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed
system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed
system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.numCycles 100900934 # number of cpu cycles simulated
system.cpu0.numCycles 100900932 # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full
@ -490,9 +490,9 @@ system.cpu1.commit.COM:branches 2941268 # Nu
system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle.samples 37417437
system.cpu1.commit.COM:committed_per_cycle.samples 37417436
system.cpu1.commit.COM:committed_per_cycle.min_value 0
0 29372798 7850.03%
0 29372797 7850.03%
1 3570649 954.27%
2 1730450 462.47%
3 1048421 280.20%
@ -552,15 +552,15 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000
system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency 49361.667333 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.267300 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency 34265289889 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency 7736833634 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles
@ -573,29 +573,29 @@ system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 #
system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 33109.914913 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 44248421389 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 12908645134 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 33109.914913 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.982803 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits 4480566 # number of overall hits
system.cpu1.dcache.overall_miss_latency 44248421389 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 1336410 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 12908645134 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles
@ -616,11 +616,11 @@ system.cpu1.dcache.tagsinuse 486.799078 # Cy
system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 158256 # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles 17763600 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles 14707751 # Number of cycles decode is idle
system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode
@ -649,9 +649,9 @@ system.cpu1.fetch.icacheStallCycles 3081765 # Nu
system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle
system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist.samples 38058468
system.cpu1.fetch.rateDist.samples 38058467
system.cpu1.fetch.rateDist.min_value 0
0 33027825 8678.18%
0 33027824 8678.18%
1 336540 88.43%
2 683303 179.54%
3 398795 104.78%
@ -664,14 +664,14 @@ system.cpu1.fetch.rateDist.max_value 8
system.cpu1.fetch.rateDist.end_dist
system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14557.233772 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.243441 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency 6814080999 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency 5188832000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked
@ -683,29 +683,29 @@ system.cpu1.icache.blocked_cycles_no_mshrs 287500 #
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency 14557.233772 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency
system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 6814080999 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses
system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 5188832000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14557.233772 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11605.243441 # average overall mshr miss latency
system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits 2613676 # number of overall hits
system.cpu1.icache.overall_miss_latency 6814080999 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles
system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses
system.cpu1.icache.overall_misses 468089 # number of overall misses
system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 5188832000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -726,7 +726,7 @@ system.cpu1.icache.tagsinuse 504.476146 # Cy
system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idleCycles 4701181 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed
system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed
system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate
@ -807,9 +807,9 @@ system.cpu1.iq.ISSUE:fu_full.start_dist
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full.end_dist
system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058468
system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467
system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0
0 28368883 7454.03%
0 28368882 7454.03%
1 4650018 1221.81%
2 1988549 522.50%
3 1356758 356.49%
@ -904,7 +904,7 @@ system.cpu1.numCycles 42759649 # nu
system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles 15176070 # Number of cycles rename is idle
system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made
@ -914,11 +914,11 @@ system.cpu1.rename.RENAME:RunCycles 4323376 # Nu
system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles 12475543 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed
system.cpu1.timesIdled 480243 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@ -1084,7 +1084,7 @@ system.l2c.prefetcher.num_hwpf_squashed_from_miss 0
system.l2c.replacements 402113 # number of replacements
system.l2c.sampled_refs 433643 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 31146.703912 # Cycle average of tags in use
system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use
system.l2c.total_refs 2097138 # Total number of references to valid blocks.
system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 124275 # number of writebacks

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 20 2008 18:39:58
M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6
M5 commit date Sun Oct 19 22:50:53 2008 -0400
M5 started Oct 20 2008 18:47:58
M5 compiled Nov 5 2008 22:27:11
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:30:16
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -132,7 +132,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -150,8 +149,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -309,7 +306,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
@ -327,8 +323,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=32768
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -408,7 +402,6 @@ block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
@ -426,8 +419,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
@ -444,7 +435,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
@ -462,8 +452,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=4194304
split=false
split_size=0
subblock_size=0
tgts_per_mshr=16
trace_addr=0

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828381 # Nu
global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted
global.BPredUnit.lookups 14559443 # Number of BP lookups
global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target.
host_inst_rate 211094 # Simulator instruction rate (inst/s)
host_mem_usage 290796 # Number of bytes of host memory used
host_seconds 251.32 # Real time elapsed on the host
host_tick_rate 7430116049 # Simulator tick rate (ticks/s)
host_inst_rate 200905 # Simulator instruction rate (inst/s)
host_mem_usage 290800 # Number of bytes of host memory used
host_seconds 264.07 # Real time elapsed on the host
host_tick_rate 7071490969 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit.

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 20 2008 18:39:58
M5 revision 5701:8ba6b8d32acac2674657b9f414b60d23fcb41fe6
M5 commit date Sun Oct 19 22:50:53 2008 -0400
M5 started Oct 20 2008 18:47:58
M5 compiled Nov 5 2008 22:27:11
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:28:27
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3434883 # Simulator instruction rate (inst/s)
host_mem_usage 338884 # Number of bytes of host memory used
host_seconds 70.99 # Real time elapsed on the host
host_tick_rate 1721637062 # Simulator tick rate (ticks/s)
host_inst_rate 2390204 # Simulator instruction rate (inst/s)
host_mem_usage 328072 # Number of bytes of host memory used
host_seconds 102.01 # Real time elapsed on the host
host_tick_rate 1198022319 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated

2
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: be nice to actually delete the event here

11
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:28:02
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:56:43
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel

9
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1384402 # Simulator instruction rate (inst/s)
host_mem_usage 334744 # Number of bytes of host memory used
host_seconds 176.13 # Real time elapsed on the host
host_tick_rate 2080531769 # Simulator tick rate (ticks/s)
host_inst_rate 1337728 # Simulator instruction rate (inst/s)
host_mem_usage 335528 # Number of bytes of host memory used
host_seconds 182.28 # Real time elapsed on the host
host_tick_rate 2010386962 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366446 # Number of seconds simulated

2
tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: be nice to actually delete the event here

11
tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:28:38
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:52:55
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1324719 # Simulator instruction rate (inst/s)
host_mem_usage 328816 # Number of bytes of host memory used
host_seconds 203.59 # Real time elapsed on the host
host_tick_rate 814052041 # Simulator tick rate (ticks/s)
host_inst_rate 1935457 # Simulator instruction rate (inst/s)
host_mem_usage 329540 # Number of bytes of host memory used
host_seconds 139.35 # Real time elapsed on the host
host_tick_rate 1189355805 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269697303 # Number of instructions simulated
sim_seconds 0.165732 # Number of seconds simulated

2
tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr
View file

@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: be nice to actually delete the event here

11
tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 8 2008 20:20:37
M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617
M5 commit date Wed Oct 08 20:18:02 2008 -0700
M5 started Oct 8 2008 20:20:39
M5 executing on tater
M5 compiled Nov 5 2008 23:03:02
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 23:20:12
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel

16
tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt
View file

@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1855549 # Simulator instruction rate (inst/s)
host_mem_usage 197988 # Number of bytes of host memory used
host_seconds 805.96 # Real time elapsed on the host
host_tick_rate 1077833305 # Simulator tick rate (ticks/s)
host_inst_rate 1589069 # Simulator instruction rate (inst/s)
host_mem_usage 198676 # Number of bytes of host memory used
host_seconds 941.11 # Real time elapsed on the host
host_tick_rate 923042875 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495492697 # Number of instructions simulated
sim_insts 1495492702 # Number of instructions simulated
sim_seconds 0.868687 # Number of seconds simulated
sim_ticks 868687488000 # Number of ticks simulated
sim_ticks 868687490500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1737374977 # number of cpu cycles simulated
system.cpu.num_insts 1495492697 # Number of instructions executed
system.cpu.numCycles 1737374982 # number of cpu cycles simulated
system.cpu.num_insts 1495492702 # Number of instructions executed
system.cpu.num_refs 533549000 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls

2
tests/long/20.parser/ref/x86/linux/simple-atomic/stderr
View file

@ -1,7 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
warn: be nice to actually delete the event here

13
tests/long/20.parser/ref/x86/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 8 2008 20:20:37
M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617
M5 commit date Wed Oct 08 20:18:02 2008 -0700
M5 started Oct 8 2008 20:20:39
M5 executing on tater
M5 compiled Nov 5 2008 23:03:02
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 23:22:32
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@ -71,4 +72,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 868687488000 because target called exit()
Exiting @ tick 868687490500 because target called exit()

9
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu
global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
global.BPredUnit.lookups 62209737 # Number of BP lookups
global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
host_inst_rate 169173 # Simulator instruction rate (inst/s)
host_mem_usage 208828 # Number of bytes of host memory used
host_seconds 2220.07 # Real time elapsed on the host
host_tick_rate 60807494 # Simulator tick rate (ticks/s)
host_inst_rate 185748 # Simulator instruction rate (inst/s)
host_mem_usage 209620 # Number of bytes of host memory used
host_seconds 2021.96 # Real time elapsed on the host
host_tick_rate 66765374 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.

1
tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
View file

@ -5,12 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:14:55
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 18:33:01
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Eon, Version 1.1
OO-style eon Time= 0.133333

8
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2526947 # Simulator instruction rate (inst/s)
host_mem_usage 181828 # Number of bytes of host memory used
host_seconds 157.77 # Real time elapsed on the host
host_tick_rate 1263471125 # Simulator tick rate (ticks/s)
host_inst_rate 3323718 # Simulator instruction rate (inst/s)
host_mem_usage 201288 # Number of bytes of host memory used
host_seconds 119.95 # Real time elapsed on the host
host_tick_rate 1661856596 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated

1
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook

11
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
View file

@ -5,12 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:59
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:13:17
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Eon, Version 1.1
OO-style eon Time= 0.183333

9
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1657758 # Simulator instruction rate (inst/s)
host_mem_usage 207956 # Number of bytes of host memory used
host_seconds 240.48 # Real time elapsed on the host
host_tick_rate 2359203743 # Simulator tick rate (ticks/s)
host_inst_rate 1753697 # Simulator instruction rate (inst/s)
host_mem_usage 208744 # Number of bytes of host memory used
host_seconds 227.33 # Real time elapsed on the host
host_tick_rate 2495737915 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated

1
tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook

11
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
View file

@ -5,12 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:19:23
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 18:58:04
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Eon, Version 1.1
OO-style eon Time= 0.566667

9
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 29107758 # Nu
global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
global.BPredUnit.lookups 349424732 # Number of BP lookups
global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target.
host_inst_rate 256177 # Simulator instruction rate (inst/s)
host_mem_usage 209160 # Number of bytes of host memory used
host_seconds 7116.35 # Real time elapsed on the host
host_tick_rate 99090030 # Simulator tick rate (ticks/s)
host_inst_rate 250324 # Simulator instruction rate (inst/s)
host_mem_usage 209520 # Number of bytes of host memory used
host_seconds 7282.75 # Real time elapsed on the host
host_tick_rate 96826033 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit.

1
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.

11
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 28 2008 07:36:20
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:15:35
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2579952 # Simulator instruction rate (inst/s)
host_mem_usage 180972 # Number of bytes of host memory used
host_seconds 778.69 # Real time elapsed on the host
host_tick_rate 1290253991 # Simulator tick rate (ticks/s)
host_inst_rate 5368625 # Simulator instruction rate (inst/s)
host_mem_usage 200452 # Number of bytes of host memory used
host_seconds 374.21 # Real time elapsed on the host
host_tick_rate 2684890322 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated

1
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:15:46
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:06:43
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

9
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1695111 # Simulator instruction rate (inst/s)
host_mem_usage 207112 # Number of bytes of host memory used
host_seconds 1185.17 # Real time elapsed on the host
host_tick_rate 2375153470 # Simulator tick rate (ticks/s)
host_inst_rate 2795907 # Simulator instruction rate (inst/s)
host_mem_usage 207904 # Number of bytes of host memory used
host_seconds 718.55 # Real time elapsed on the host
host_tick_rate 3917565207 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated

1
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:24
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 21:28:15
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

9
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 452707 # Nu
global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted
global.BPredUnit.lookups 16249458 # Number of BP lookups
global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
host_inst_rate 176565 # Simulator instruction rate (inst/s)
host_mem_usage 212168 # Number of bytes of host memory used
host_seconds 450.78 # Real time elapsed on the host
host_tick_rate 60195419 # Simulator tick rate (ticks/s)
host_inst_rate 272001 # Simulator instruction rate (inst/s)
host_mem_usage 212988 # Number of bytes of host memory used
host_seconds 292.62 # Real time elapsed on the host
host_tick_rate 92731689 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit.

1
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout
View file

@ -5,10 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:23
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 18:42:31
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2496642 # Simulator instruction rate (inst/s)
host_mem_usage 184388 # Number of bytes of host memory used
host_seconds 35.38 # Real time elapsed on the host
host_tick_rate 1249741953 # Simulator tick rate (ticks/s)
host_inst_rate 5277091 # Simulator instruction rate (inst/s)
host_mem_usage 203864 # Number of bytes of host memory used
host_seconds 16.74 # Real time elapsed on the host
host_tick_rate 2641544350 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated

1
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout
View file

@ -5,10 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:32
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:13:00
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

9
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1478736 # Simulator instruction rate (inst/s)
host_mem_usage 210524 # Number of bytes of host memory used
host_seconds 59.74 # Real time elapsed on the host
host_tick_rate 2262580844 # Simulator tick rate (ticks/s)
host_inst_rate 1704355 # Simulator instruction rate (inst/s)
host_mem_usage 211324 # Number of bytes of host memory used
host_seconds 51.83 # Real time elapsed on the host
host_tick_rate 2607795037 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated

1
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.

11
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout
View file

@ -5,10 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:24
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 21:27:23
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3368510 # Simulator instruction rate (inst/s)
host_mem_usage 185484 # Number of bytes of host memory used
host_seconds 40.42 # Real time elapsed on the host
host_tick_rate 1686201794 # Simulator tick rate (ticks/s)
host_inst_rate 2431097 # Simulator instruction rate (inst/s)
host_mem_usage 204768 # Number of bytes of host memory used
host_seconds 56.00 # Real time elapsed on the host
host_tick_rate 1216955986 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated

2
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: ignoring syscall time(4026527848, 4026528248, ...)
warn: ignoring syscall time(4026527400, 1375098, ...)
warn: ignoring syscall time(4026527312, 1, ...)
@ -562,3 +561,4 @@ warn: ignoring syscall time(4026525968, 4026526436, ...)
warn: ignoring syscall time(4026526056, 7004192, ...)
warn: ignoring syscall time(4026527512, 4, ...)
warn: ignoring syscall time(4026525760, 0, ...)
warn: be nice to actually delete the event here

11
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,11 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:29:09
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:55:47
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 68148678500 because target called exit()

9
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1368614 # Simulator instruction rate (inst/s)
host_mem_usage 211448 # Number of bytes of host memory used
host_seconds 99.47 # Real time elapsed on the host
host_tick_rate 2062044712 # Simulator tick rate (ticks/s)
host_inst_rate 1344201 # Simulator instruction rate (inst/s)
host_mem_usage 212228 # Number of bytes of host memory used
host_seconds 101.28 # Real time elapsed on the host
host_tick_rate 2025263348 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.205117 # Number of seconds simulated

2
tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: ignoring syscall time(4026527848, 4026528248, ...)
warn: ignoring syscall time(4026527400, 1375098, ...)
warn: ignoring syscall time(4026527312, 1, ...)
@ -562,3 +561,4 @@ warn: ignoring syscall time(4026525968, 4026526436, ...)
warn: ignoring syscall time(4026526056, 7004192, ...)
warn: ignoring syscall time(4026527512, 4, ...)
warn: ignoring syscall time(4026525760, 0, ...)
warn: be nice to actually delete the event here

11
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
View file

@ -5,11 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:21:24
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:30:05
M5 executing on piton
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:43:57
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 205116920000 because target called exit()

9
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

332
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 312845728 # Number of BTB hits
global.BPredUnit.BTBLookups 319575550 # Number of BTB lookups
global.BPredUnit.BTBHits 312845737 # Number of BTB hits
global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups
global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 19647323 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 266741487 # Number of conditional branches predicted
global.BPredUnit.lookups 345502581 # Number of BP lookups
global.BPredUnit.usedRAS 23750301 # Number of times the RAS was used to get a target.
host_inst_rate 237180 # Simulator instruction rate (inst/s)
host_mem_usage 201180 # Number of bytes of host memory used
host_seconds 7319.53 # Real time elapsed on the host
host_tick_rate 101414942 # Simulator tick rate (ticks/s)
global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted
global.BPredUnit.lookups 345502589 # Number of BP lookups
global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target.
host_inst_rate 152874 # Simulator instruction rate (inst/s)
host_mem_usage 201972 # Number of bytes of host memory used
host_seconds 11356.03 # Real time elapsed on the host
host_tick_rate 65366964 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 67515290 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 621608429 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 234046219 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.742309 # Number of seconds simulated
sim_ticks 742309410500 # Number of ticks simulated
sim_ticks 742309425500 # Number of ticks simulated
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 62782580 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1379215313
system.cpu.commit.COM:committed_per_cycle.samples 1379215338
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 736540795 5340.29%
1 260049510 1885.49%
0 736540830 5340.29%
1 260049504 1885.49%
2 126970462 920.60%
3 77723430 563.53%
4 51327443 372.15%
3 77723426 563.53%
4 51327439 372.15%
5 27759546 201.27%
6 26179569 189.81%
6 26179568 189.81%
7 9881978 71.65%
8 62782580 455.21%
8 62782585 455.21%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,10 +43,10 @@ system.cpu.commit.COM:loads 445666361 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19646822 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 627314196 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction
@ -61,62 +61,62 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 523259958 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16887.800030 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.117004 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 512954318 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 174039587500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 10305640 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 3030506 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 81969786000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7275134 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 33917.186217 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824413 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155297499 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 184204340094 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 5431003 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 83541340193 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2248526 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 73.053389 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 683988460 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22764.952321 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668251817 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 358243927594 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses
system.cpu.dcache.demand_misses 15736643 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6212983 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 165511126193 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9523660 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 683988460 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22764.952321 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 668251817 # number of overall hits
system.cpu.dcache.overall_miss_latency 358243927594 # number of overall miss cycles
system.cpu.dcache.overall_hits 668251814 # number of overall hits
system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses
system.cpu.dcache.overall_misses 15736643 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6212983 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 165511126193 # number of overall MSHR miss cycles
system.cpu.dcache.overall_misses 15736652 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9523660 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -128,63 +128,63 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 9155770 # number of replacements
system.cpu.dcache.sampled_refs 9159866 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 9155775 # number of replacements
system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4082.023671 # Cycle average of tags in use
system.cpu.dcache.total_refs 669159252 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use
system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2245448 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 98604485 # Number of cycles decode is blocked
system.cpu.dcache.writebacks 2245449 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2810650716 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 726334598 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 549143095 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 93084197 # Number of cycles decode is squashing
system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 768331628 # DTB accesses
system.cpu.dtb.accesses 768331639 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 752318827 # DTB hits
system.cpu.dtb.hits 752318838 # DTB hits
system.cpu.dtb.misses 16012801 # DTB misses
system.cpu.dtb.read_accesses 566617541 # DTB read accesses
system.cpu.dtb.read_accesses 566617551 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 557381515 # DTB read hits
system.cpu.dtb.read_hits 557381525 # DTB read hits
system.cpu.dtb.read_misses 9236026 # DTB read misses
system.cpu.dtb.write_accesses 201714087 # DTB write accesses
system.cpu.dtb.write_accesses 201714088 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 194937312 # DTB write hits
system.cpu.dtb.write_hits 194937313 # DTB write hits
system.cpu.dtb.write_misses 6776775 # DTB write misses
system.cpu.fetch.Branches 345502581 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355180514 # Number of cache lines fetched
system.cpu.fetch.Cycles 920206753 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 7941780 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2863046416 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28103164 # Number of cycles fetch has spent squashing
system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched
system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355180514 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 336596029 # Number of branches that fetch has predicted taken
system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 1472299511
system.cpu.fetch.rateDist.samples 1472299541
system.cpu.fetch.rateDist.min_value 0
0 907273306 6162.29%
0 907273323 6162.29%
1 47886355 325.25%
2 34613457 235.10%
2 34613456 235.10%
3 52095475 353.84%
4 125971052 855.61%
4 125971058 855.61%
5 69335096 470.93%
6 50458684 342.72%
7 40993758 278.43%
8 143672328 975.84%
8 143672336 975.84%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 355180514 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355179280 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses
@ -194,16 +194,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # ms
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 393768.603104 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355180514 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
system.cpu.icache.demand_hits 355179280 # number of demand (read+write) hits
system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses
@ -214,11 +214,11 @@ system.cpu.icache.demand_mshr_misses 902 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 355180514 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355179280 # number of overall hits
system.cpu.icache.overall_hits 355179284 # number of overall hits
system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_misses 1234 # number of overall misses
@ -240,59 +240,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 711.425376 # Cycle average of tags in use
system.cpu.icache.total_refs 355179280 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use
system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 282186317 # Number of branches executed
system.cpu.iew.EXEC:branches 282186314 # Number of branches executed
system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate
system.cpu.iew.EXEC:refs 769619313 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 201925300 # Number of stores executed
system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 201925301 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1531990742 # num instructions consuming a value
system.cpu.iew.WB:count 2240290220 # cumulative count of insts written-back
system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value
system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1243717846 # num instructions producing a value
system.cpu.iew.WB:producers 1243717865 # num instructions producing a value
system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle
system.cpu.iew.WB:sent 2261678921 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21342133 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 621608429 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 234046219 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2621719070 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 567694013 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 36858072 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2278986798 # Number of executed instructions
system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 93084197 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 33889592 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 175942068 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 73141237 # Number of stores squashed
system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 20638337 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2315844870 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 1532920234 66.19% # Type of FU issued
IntAlu 1532920254 66.19% # Type of FU issued
IntMult 99 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 234 0.00% # Type of FU issued
@ -301,8 +301,8 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 16 0.00% # Type of FU issued
FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 577889725 24.95% # Type of FU issued
MemWrite 205034375 8.85% # Type of FU issued
MemRead 577889733 24.95% # Type of FU issued
MemWrite 205034377 8.85% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
@ -325,31 +325,31 @@ system.cpu.iq.ISSUE:fu_full.start_dist
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299511
system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 577695747 3923.77%
1 271543753 1844.35%
2 242868164 1649.58%
3 139713871 948.95%
4 122021081 828.78%
5 69652696 473.09%
6 39670195 269.44%
7 8017830 54.46%
0 577695763 3923.77%
1 271543756 1844.35%
2 242868170 1649.58%
3 139713874 948.95%
4 122021082 828.78%
5 69652698 473.09%
6 39670196 269.44%
7 8017828 54.46%
8 1116174 7.58%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate
system.cpu.iq.iqInstsAdded 2492922470 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2315844870 # Number of instructions issued
system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 739697575 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1501742 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 329349436 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 355180548 # ITB accesses
system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 355180552 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 355180514 # ITB hits
system.cpu.itb.hits 355180518 # ITB hits
system.cpu.itb.misses 34 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
@ -360,39 +360,39 @@ system.cpu.l2cache.ReadExReq_misses 1884731 # nu
system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7276037 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5387449 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 363810 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.097532 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459886 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 12488541353 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 363810 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373231721 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 363810 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245448 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2245448 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.417948 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9160768 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5387449 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses
@ -403,11 +403,11 @@ system.cpu.l2cache.demand_mshr_misses 3773319 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 9160768 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5387449 # number of overall hits
system.cpu.l2cache.overall_hits 5387454 # number of overall hits
system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3773319 # number of overall misses
@ -429,27 +429,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 2759426 # number of replacements
system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25902.034995 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6731616 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1195718 # number of writebacks
system.cpu.numCycles 1484618822 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 68342800 # Number of cycles rename is blocking
system.cpu.numCycles 1484618852 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 744648223 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20682073 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3556218268 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2749142878 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2059304818 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 535957515 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 93084197 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 30265718 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 683101855 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 60936720 # count of insts added to the skid buffer
system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed
system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls

1
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.

11
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:54
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 19:13:16
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length

8
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2729023 # Simulator instruction rate (inst/s)
host_mem_usage 174164 # Number of bytes of host memory used
host_seconds 666.82 # Real time elapsed on the host
host_tick_rate 1369458693 # Simulator tick rate (ticks/s)
host_inst_rate 3454414 # Simulator instruction rate (inst/s)
host_mem_usage 193640 # Number of bytes of host memory used
host_seconds 526.80 # Real time elapsed on the host
host_tick_rate 1733469179 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.913189 # Number of seconds simulated

1
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.

11
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:46
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 18:32:56
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length

9
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,7 +40,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -58,8 +57,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -80,7 +77,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -98,8 +94,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -120,7 +114,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -138,8 +131,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2488083 # Simulator instruction rate (inst/s)
host_mem_usage 200292 # Number of bytes of host memory used
host_seconds 731.40 # Real time elapsed on the host
host_tick_rate 3729826518 # Simulator tick rate (ticks/s)
host_inst_rate 2843037 # Simulator instruction rate (inst/s)
host_mem_usage 201092 # Number of bytes of host memory used
host_seconds 640.08 # Real time elapsed on the host
host_tick_rate 4261930074 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.727991 # Number of seconds simulated

1
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.

11
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 27 2008 21:08:21
M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
M5 commit date Sat Sep 27 21:03:50 2008 -0700
M5 started Sep 27 2008 21:08:57
M5 executing on piton
M5 compiled Nov 5 2008 18:30:06
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 18:47:24
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length

8
tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1763085 # Simulator instruction rate (inst/s)
host_mem_usage 194072 # Number of bytes of host memory used
host_seconds 2639.25 # Real time elapsed on the host
host_tick_rate 1074249302 # Simulator tick rate (ticks/s)
host_inst_rate 2012716 # Simulator instruction rate (inst/s)
host_mem_usage 194900 # Number of bytes of host memory used
host_seconds 2311.91 # Real time elapsed on the host
host_tick_rate 1226349708 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653219791 # Number of instructions simulated
sim_seconds 2.835211 # Number of seconds simulated

2
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr
View file

@ -1,7 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
warn: be nice to actually delete the event here

11
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 8 2008 20:20:37
M5 revision 5641:1033c9f7de3f63b99accb1f06962921c3b61b617
M5 commit date Wed Oct 08 20:18:02 2008 -0700
M5 started Oct 8 2008 20:55:01
M5 executing on tater
M5 compiled Nov 5 2008 23:03:02
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 23:38:14
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length

9
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,7 +104,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -122,8 +121,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -281,7 +278,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -299,8 +295,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
split=false
split_size=0
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -321,7 +315,6 @@ block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
@ -339,8 +332,6 @@ prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
split=false
split_size=0
subblock_size=0
tgts_per_mshr=5
trace_addr=0

8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1946248 # Nu
global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
global.BPredUnit.lookups 19468548 # Number of BP lookups
global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
host_inst_rate 157592 # Simulator instruction rate (inst/s)
host_mem_usage 206456 # Number of bytes of host memory used
host_seconds 534.16 # Real time elapsed on the host
host_tick_rate 76416157 # Simulator tick rate (ticks/s)
host_inst_rate 134854 # Simulator instruction rate (inst/s)
host_mem_usage 207240 # Number of bytes of host memory used
host_seconds 624.23 # Real time elapsed on the host
host_tick_rate 65390701 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.

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