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Very minor memtest regression stats changes from recent coherence bug fixes.

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--HG--
extra : convert_revision : 5e7f8ce91ea8f98e6503ac9e10aae68c62f9e510
This commit is contained in:
Steve Reinhardt 2008-01-02 15:35:09 -08:00
parent 6c5a3ab8b2
commit d4cca11bdb
2 changed files with 12 additions and 12 deletions
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20
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
View file

@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
host_mem_usage 366088 # Number of bytes of host memory used
host_seconds 156.35 # Real time elapsed on the host
host_tick_rate 1042333 # Simulator tick rate (ticks/s)
host_mem_usage 368552 # Number of bytes of host memory used
host_seconds 153.46 # Real time elapsed on the host
host_tick_rate 1061945 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000163 # Number of seconds simulated
sim_ticks 162969030 # Number of ticks simulated
@ -78,7 +78,7 @@ system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu0.l1c.replacements 27517 # number of replacements
system.cpu0.l1c.sampled_refs 27861 # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.l1c.tagsinuse 345.687561 # Cycle average of tags in use
system.cpu0.l1c.tagsinuse 345.121888 # Cycle average of tags in use
system.cpu0.l1c.total_refs 11484 # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l1c.writebacks 10876 # number of writebacks
@ -157,7 +157,7 @@ system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu1.l1c.replacements 27839 # number of replacements
system.cpu1.l1c.sampled_refs 28200 # Sample count of references to valid blocks.
system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.l1c.tagsinuse 345.864238 # Cycle average of tags in use
system.cpu1.l1c.tagsinuse 344.387684 # Cycle average of tags in use
system.cpu1.l1c.total_refs 11496 # Total number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l1c.writebacks 10966 # number of writebacks
@ -236,7 +236,7 @@ system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu2.l1c.replacements 27813 # number of replacements
system.cpu2.l1c.sampled_refs 28149 # Sample count of references to valid blocks.
system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu2.l1c.tagsinuse 347.648591 # Cycle average of tags in use
system.cpu2.l1c.tagsinuse 346.292399 # Cycle average of tags in use
system.cpu2.l1c.total_refs 11687 # Total number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.l1c.writebacks 11045 # number of writebacks
@ -315,7 +315,7 @@ system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu3.l1c.replacements 28133 # number of replacements
system.cpu3.l1c.sampled_refs 28477 # Sample count of references to valid blocks.
system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu3.l1c.tagsinuse 348.344200 # Cycle average of tags in use
system.cpu3.l1c.tagsinuse 347.262699 # Cycle average of tags in use
system.cpu3.l1c.total_refs 11422 # Total number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.l1c.writebacks 11005 # number of writebacks
@ -473,7 +473,7 @@ system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu5.l1c.replacements 27880 # number of replacements
system.cpu5.l1c.sampled_refs 28223 # Sample count of references to valid blocks.
system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu5.l1c.tagsinuse 348.509117 # Cycle average of tags in use
system.cpu5.l1c.tagsinuse 348.223192 # Cycle average of tags in use
system.cpu5.l1c.total_refs 11787 # Total number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu5.l1c.writebacks 11039 # number of writebacks
@ -552,7 +552,7 @@ system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu6.l1c.replacements 27468 # number of replacements
system.cpu6.l1c.sampled_refs 27829 # Sample count of references to valid blocks.
system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu6.l1c.tagsinuse 345.752626 # Cycle average of tags in use
system.cpu6.l1c.tagsinuse 345.245640 # Cycle average of tags in use
system.cpu6.l1c.total_refs 11434 # Total number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu6.l1c.writebacks 10779 # number of writebacks
@ -631,7 +631,7 @@ system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu7.l1c.replacements 27895 # number of replacements
system.cpu7.l1c.sampled_refs 28241 # Sample count of references to valid blocks.
system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu7.l1c.tagsinuse 347.065724 # Cycle average of tags in use
system.cpu7.l1c.tagsinuse 346.417041 # Cycle average of tags in use
system.cpu7.l1c.total_refs 11691 # Total number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu7.l1c.writebacks 10935 # number of writebacks

4
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
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@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 13 2007 20:22:15
M5 started Tue Nov 13 20:22:26 2007
M5 compiled Jan 2 2008 15:26:07
M5 started Wed Jan 2 15:26:09 2008
M5 executing on vm1
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second