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inorder-regress: add vortex ALPHA_SE

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This commit is contained in:
Korey Sewell 2009-05-12 15:01:17 -04:00
parent 39010b990d
commit b5959124e1
6 changed files with 928 additions and 0 deletions
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223
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=InOrderCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
dataMemPort=dcache_port
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchMemPort=icache_port
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
progress_interval=0
stageTracing=false
stageWidth=1
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/n/poolfs/z/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.port[0]

6
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetching currently unimplemented
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b

15
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Executable file
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M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 12 2009 12:20:30
M5 revision 2eebd457f8fc 6197 default qtip tip inorder-vortex-regress
M5 started May 12 2009 12:20:31
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

158
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg Normal file
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SYSTEM TYPE...
__ZTC__ := False
__UNIX__ := True
__RISC__ := True
SPEC_CPU2000_LP64 := True
__MAC__ := False
__BCC__ := False
__BORLANDC__ := False
__GUI__ := False
__WTC__ := False
__HP__ := False
CODE OPTIONS...
__MACROIZE_HM__ := True
__MACROIZE_MEM__ := True
ENV01 := True
USE_HPP_STYPE_HDRS := False
USE_H_STYPE_HDRS := False
CODE INCLUSION PARAMETERS...
INCLUDE_ALL_CODE := False
INCLUDE_DELETE_CODE := True
__SWAP_GRP_POS__ := True
__INCLUDE_MTRX__ := False
__BAD_CODE__ := False
API_INCLUDE := False
BE_CAREFUL := False
OLDWAY := False
NOTUSED := False
SYSTEM PARAMETERS...
EXT_ENUM := 999999999L
CHUNK_CONSTANT := 55555555
CORE_CONSTANT := 55555555
CORE_LIMIT := 20971520
CorePage_Size := 384000
ALIGN_BYTES := True
CORE_BLOCK_ALIGN := 8
FAR_MEM := False
MEMORY MANAGEMENT PARAMETERS...
SYSTEM_ALLOC := True
SYSTEM_FREESTORE := True
__NO_DISKCACHE__ := False
__FREEZE_VCHUNKS__ := True
__FREEZE_GRP_PACKETS__ := True
__MINIMIZE_TREE_CACHE__:= True
SYSTEM STD PARAMETERS...
__STDOUT__ := False
NULL := 0
LPTR := False
False_Status := 1
True_Status := 0
LARGE := True
TWOBYTE_BOOL := False
__NOSTR__ := False
MEMORY VALIDATION PARAMETERS...
CORE_CRC_CHECK := False
VALIDATE_MEM_CHUNKS := False
SYSTEM DEBUG OPTIONS...
DEBUG := False
MCSTAT := False
TRACKBACK := False
FLUSH_FILES := False
DEBUG_CORE0 := False
DEBUG_RISC := False
__TREE_BUG__ := False
__TRACK_FILE_READS__ := False
PAGE_SPACE := False
LEAVE_NO_TRACE := True
NULL_TRACE_STRS := False
TIME PARAMETERS...
CLOCK_IS_LONG := False
__DISPLAY_TIME__ := False
__TREE_TIME__ := False
__DISPLAY_ERRORS__ := False
API MACROS...
__BMT01__ := True
OPTIMIZE := True
END OF DEFINES.
... IMPLODE MEMORY ...
SWAP to DiskCache := False
FREEZE_GRP_PACKETS:= True
QueBug := 1000
sizeof(boolean) = 4
sizeof(sizetype) = 4
sizeof(chunkstruc) = 32
sizeof(shorttype ) = 2
sizeof(idtype ) = 2
sizeof(sizetype ) = 4
sizeof(indextype ) = 4
sizeof(numtype ) = 4
sizeof(handletype) = 4
sizeof(tokentype ) = 8
sizeof(short ) = 2
sizeof(int ) = 4
sizeof(lt64 ) = 4
sizeof(farlongtype) = 4
sizeof(long ) = 8
sizeof(longaddr ) = 8
sizeof(float ) = 4
sizeof(double ) = 8
sizeof(addrtype ) = 8
sizeof(char * ) = 8
ALLOC CORE_1 :: 16
BHOOLE NATH
OPEN File ./input/lendian.rnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 2030c0
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
DB Handle Chunk's StackPtr = 20797
DB[ 1] LOADED; Handles= 20797
KERNEL in CORE[ 1] Restored @ 4005c800
OPEN File ./input/lendian.wnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 21c40
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
DB Handle Chunk's StackPtr = 17
DB[ 2] LOADED; Handles= 17
VORTEx_Status == -8 || fffffff8
BE HERE NOW !!!
... VORTEx ON LINE ...
... END OF SESSION ...

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tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out Normal file
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CREATE Db Header and Db Primal ...
NEW DB [ 3] Created.
VORTEX INPUT PARAMETERS::
MESSAGE FileName: smred.msg
OUTPUT FileName: smred.out
DISK CACHE FileName: NULL
PART DB FileName: parts.db
DRAW DB FileName: draw.db
PERSON DB FileName: emp.db
PERSONS Data FileName: ./input/persons.250
PARTS Count : 100
OUTER Loops : 1
INNER Loops : 1
LOOKUP Parts : 25
DELETE Parts : 10
STUFF Parts : 10
DEPTH Traverse: 5
% DECREASE Parts : 0
% INCREASE LookUps : 0
% INCREASE Deletes : 0
% INCREASE Stuffs : 0
FREEZE_PACKETS : 1
ALLOC_CHUNKS : 10000
EXTEND_CHUNKS : 5000
DELETE Draw objects : True
DELETE Part objects : False
QUE_BUG : 1000
VOID_BOUNDARY : 67108864
VOID_RESERVE : 1048576
COMMIT_DBS : False
BMT TEST :: files...
EdbName := PartLib
EdbFileName := parts.db
DrwName := DrawLib
DrwFileName := draw.db
EmpName := PersonLib
EmpFileName := emp.db
Swap to DiskCache := False
Freeze the cache := True
BMT TEST :: parms...
DeBug modulo := 1000
Create Parts count:= 100
Outer Loops := 1
Inner Loops := 1
Look Ups := 25
Delete Parts := 10
Stuff Parts := 10
Traverse Limit := 5
Delete Draws := True
Delete Parts := False
Delete ALL Parts := after every <mod 0>Outer Loop
INITIALIZE LIBRARY ::
INITIALIZE SCHEMA ::
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 4] Created.
PartLibCreate:: Db[ 4]; VpartsDir= 1
Part Count= 1
Initialize the Class maps
LIST HEADS loaded ... DbListHead_Class = 207
DbListNode_Class = 206
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 5] Created.
DrawLibCreate:: Db[ 5]; VpartsDir= 1
Initialize the Class maps of this schema.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 6] Created.
***NOTE*** Persons Library Extended!
Create <131072> Persons.
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
LAST Person Read::
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
BUILD <Query0> for <Part2> class::
if (link[1].length >= 5) ::
Build Query2 for <Address> class::
if (State == CA || State == T*)
Build Query1 for <Person> class::
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
BUILD <Query3> for <DrawObj> class::
if (Id >= 3000
&& (Id >= 3000 && Id <= 3001)
&& Id >= 3002)
BUILD <Query4> for <NamedDrawObj> class::
if (Nam == Pre*
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
&& Id <= 7)
SEED := 1008; Swap = False; RgnEntries = 135
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
Create 100 New Parts
Create Part 1. Token[ 4: 2].
< 100> Parts Created. CurrentId= 100
Connect each instantiated Part TO 3 unique Parts
Connect Part 1. Token[ 4: 2]
Connect Part 25. Token[ 4: 26] FromList= 26.
Connect Part 12. Token[ 4: 13] FromList= 13.
Connect Part 59. Token[ 4: 60] FromList= 60.
SET <DrawObjs> entries::
1. [ 5: 5] := <1 >; @[: 6]
Iteration count = 100
SET <NamedDrawObjs> entries::
1. [ 5: 39] := <14 >;
Iteration count = 12
SET <LibRectangles> entries::
1. [ 5: 23] := <8 >; @[: 24]
Iteration count = 12
LIST <DbRectangles> entries::
1. [ 5: 23]
Iteration count = 12
SET <PersonNames > entries::
Iteration count = 250
COMMIT All Image copies:: Release=<True>; Max Parts= 100
< 100> Part images' Committed.
< 0> are Named.
< 50> Point images' Committed.
< 81> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. TestObj Committed.
< 0> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
< 0> CartesianPoint images' Committed.
BEGIN Inner Loop Sequence::.
INNER LOOP [ 1: 1] :
LOOK UP 25 Random Parts and Export each Part.
LookUp for 26 parts; Asserts = 8
<Part2 > Asserts = 2; NULL Asserts = 3.
<DrawObj > Asserts = 0; NULL Asserts = 5.
<NamedObj > Asserts = 0; NULL Asserts = 0.
<Person > Asserts = 0; NULL Asserts = 5.
<TestObj > Asserts = 60; NULL Asserts = 0.
DELETE 10 Random Parts.
PartDelete :: Token[ 4: 91].
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
Vlists[ 89] := 100;
Delete for 11 parts;
Traverse Count= 0
TRAVERSE PartId[ 6] and all Connections to 5 Levels
SEED In Traverse Part [ 4: 65] @ Level = 4.
Traverse Count= 357
Traverse Asserts = 5. True Tests = 1
< 5> DrawObj objects DELETED.
< 2> are Named.
< 2> Point objects DELETED.
CREATE 10 Additional Parts
Create 10 New Parts
Create Part 101. Token[ 4: 102].
< 10> Parts Created. CurrentId= 110
Connect each instantiated Part TO 3 unique Parts
COMMIT All Image copies:: Release=<True>; Max Parts= 110
< 81> Part images' Committed.
< 0> are Named.
< 38> Point images' Committed.
< 31> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Committed.
< 15> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
< 16> CartesianPoint images' Committed.
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Deleted.
< 15> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
< 16> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
END INNER LOOP [ 1: 1].
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
< 0> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
< 0> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
STATUS= -201
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!

268
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
host_inst_rate 51305 # Simulator instruction rate (inst/s)
host_mem_usage 216648 # Number of bytes of host memory used
host_seconds 1721.87 # Real time elapsed on the host
host_tick_rate 63437429 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.109231 # Number of seconds simulated
sim_ticks 109230836500 # Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.instReqsProcessed 88340674 # Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.predictedNotTaken 10443271 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 3311206 # Number of Branches Predicted As Taken (True).
system.cpu.Decode-Unit.instReqsProcessed 88340674 # Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.instReqsProcessed 53075554 # Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.predictedNotTakenIncorrect 4515835 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 1659774 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
system.cpu.Fetch-Seq-Unit.instReqsProcessed 184507615 # Number of Instructions Requests that completed in this resource.
system.cpu.Graduation-Unit.instReqsProcessed 88340673 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed.
system.cpu.RegFile-Manager.instReqsProcessed 158796488 # Number of Instructions Requests that completed in this resource.
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.cpi 2.472946 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.472946 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 38182.186102 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.874601 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215854 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2320866000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002998 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60784 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2131056000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56050.509703 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53050.509703 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 8395974000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7946595000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741509 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 50892.737573 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 47861.411766 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34679438 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10716840000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
system.cpu.dcache.demand_misses 210577 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10077651000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50892.737573 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47861.411766 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34679438 # number of overall hits
system.cpu.dcache.overall_miss_latency 10716840000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
system.cpu.dcache.overall_misses 210577 # number of overall misses
system.cpu.dcache.overall_mshr_hits 18 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10077651000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4077.186045 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685659 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 848449000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.dcache_port.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource.
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 96166938 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 19084.255120 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15849.213376 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96087744 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1511358500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000824 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 79194 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1266 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1235097500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000810 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 77928 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1233.032338 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 96166938 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 19084.255120 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15849.213376 # average overall mshr miss latency
system.cpu.icache.demand_hits 96087744 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1511358500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000824 # miss rate for demand accesses
system.cpu.icache.demand_misses 79194 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1266 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1235097500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000810 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 77928 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 96166938 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 19084.255120 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15849.213376 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 96087744 # number of overall hits
system.cpu.icache.overall_miss_latency 1511358500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000824 # miss rate for overall accesses
system.cpu.icache.overall_misses 79194 # number of overall misses
system.cpu.icache.overall_mshr_hits 1266 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1235097500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000810 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 77928 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 75882 # number of replacements
system.cpu.icache.sampled_refs 77928 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1874.324882 # Cycle average of tags in use
system.cpu.icache.total_refs 96087744 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache_port.instReqsProcessed 96166940 # Number of Instructions Requests that completed in this resource.
system.cpu.ipc 0.404376 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.404376 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 96170872 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 96166938 # ITB hits
system.cpu.itb.fetch_misses 3934 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52039.532519 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.083578 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 7471732000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743132000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 138694 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52317.460317 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40003.485162 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 95224 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2274240000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.313424 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43470 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1738951500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313424 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43470 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.529364 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000.884956 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 323146000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248605500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.637832 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 282272 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52104.123006 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000.874107 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 95224 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9745972000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.662652 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 187048 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 7482083500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.662652 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 187048 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 282272 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52104.123006 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000.874107 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 95224 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9745972000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.662652 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 187048 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 7482083500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.662652 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 187048 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 147733 # number of replacements
system.cpu.l2cache.sampled_refs 172939 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18262.964194 # Cycle average of tags in use
system.cpu.l2cache.total_refs 110306 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120636 # number of writebacks
system.cpu.numCycles 218461674 # number of cpu cycles simulated
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.threadCycles 218461674 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------