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inorder-regress: add twolf ALPHA-SE

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This commit is contained in:
Korey Sewell 2009-05-12 15:01:16 -04:00
parent ca20d1dd23
commit 39010b990d
11 changed files with 900 additions and 0 deletions
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223
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Normal file
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[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=InOrderCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0
cachePorts=2
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
cpu_id=0
dataMemPort=dcache_port
defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchMemPort=icache_port
functionTrace=false
functionTraceStart=0
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
phase=0
predType=tournament
progress_interval=0
stageTracing=false
stageWidth=1
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaTLB
size=64
[system.cpu.icache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/n/poolfs/z/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.port[0]

6
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr Executable file
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warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetching currently unimplemented
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b

31
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Executable file
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M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 12 2009 10:42:48
M5 revision 40b296e9f790 6196 default qtip tip inorder-twolf-regress
M5 started May 12 2009 10:42:49
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124

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tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out Normal file
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin Normal file
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$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 Normal file
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@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 Normal file
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@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav Normal file
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@ -0,0 +1,18 @@
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19
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 Normal file
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@ -0,0 +1,19 @@
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29
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf Normal file
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net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

268
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
host_inst_rate 52331 # Simulator instruction rate (inst/s)
host_mem_usage 157196 # Number of bytes of host memory used
host_seconds 1756.17 # Real time elapsed on the host
host_tick_rate 57825432 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.101552 # Number of seconds simulated
sim_ticks 101551554000 # Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.instReqsProcessed 91903057 # Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.predictedNotTaken 8198984 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 2041701 # Number of Branches Predicted As Taken (True).
system.cpu.Decode-Unit.instReqsProcessed 91903057 # Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.predictedNotTakenIncorrect 3739118 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 1029596 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
system.cpu.Fetch-Seq-Unit.instReqsProcessed 189586934 # Number of Instructions Requests that completed in this resource.
system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed.
system.cpu.RegFile-Manager.instReqsProcessed 188816950 # Number of Instructions Requests that completed in this resource.
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.cpi 2.209971 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.209971 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 51625.779626 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48552.631579 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995717 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 24832000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 481 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 23062500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56415.277031 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53415.277031 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 104876000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 99299000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11918.612686 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55430.769231 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52425.664096 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26494961 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 129708000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2340 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 122361500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55430.769231 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52425.664096 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26494961 # number of overall hits
system.cpu.dcache.overall_miss_latency 129708000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2340 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 122361500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1441.841728 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495076 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dcache_port.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource.
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.icache.ReadReq_accesses 97683877 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 27281.166802 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24026.033154 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 97675238 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 235682000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000088 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8639 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 205807000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8566 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 11402.666122 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 97683877 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 27281.166802 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 24026.033154 # average overall mshr miss latency
system.cpu.icache.demand_hits 97675238 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 235682000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000088 # miss rate for demand accesses
system.cpu.icache.demand_misses 8639 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 205807000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8566 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 97683877 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 27281.166802 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 24026.033154 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 97675238 # number of overall hits
system.cpu.icache.overall_miss_latency 235682000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000088 # miss rate for overall accesses
system.cpu.icache.overall_misses 8639 # number of overall misses
system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 205807000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8566 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 6732 # number of replacements
system.cpu.icache.sampled_refs 8566 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1428.662553 # Cycle average of tags in use
system.cpu.icache.total_refs 97675238 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache_port.instReqsProcessed 97683876 # Number of Instructions Requests that completed in this resource.
system.cpu.ipc 0.452495 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.452495 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 97683924 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 97683877 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52413.329519 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40003.432494 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 91618500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69926000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 9041 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52240.287300 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40013.548808 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5978 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 160012000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.338790 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 122561500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338790 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52409.909910 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 5817500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.968317 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10789 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52303.159426 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40009.873207 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5978 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 251630500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.445917 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 192487500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.445917 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 10789 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52303.159426 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40009.873207 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5978 # number of overall hits
system.cpu.l2cache.overall_miss_latency 251630500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.445917 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4811 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 192487500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.445917 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2039.443667 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5964 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 203103109 # number of cpu cycles simulated
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.threadCycles 203103109 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------