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ARM: Update SE stats for TLB stats additions

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This commit is contained in:
Ali Saidi 2010-11-08 13:59:35 -06:00
parent fe300c6de2
commit 06c5283930
51 changed files with 511 additions and 173 deletions
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2
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,7 +52,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr

10
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 5 2010 14:46:04
M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch
M5 started Oct 5 2010 15:01:57
M5 executing on aus-bc2-b14
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:16:15
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 4265359 # Simulator instruction rate (inst/s)
host_mem_usage 252884 # Number of bytes of host memory used
host_seconds 140.80 # Real time elapsed on the host
host_tick_rate 2132757259 # Simulator tick rate (ticks/s)
host_inst_rate 2821771 # Simulator instruction rate (inst/s)
host_mem_usage 253968 # Number of bytes of host memory used
host_seconds 212.84 # Real time elapsed on the host
host_tick_rate 1410937507 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581394 # Number of instructions simulated
sim_seconds 0.300302 # Number of seconds simulated

2
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:05:18
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:44:50
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1338185 # Simulator instruction rate (inst/s)
host_mem_usage 196956 # Number of bytes of host memory used
host_seconds 447.34 # Real time elapsed on the host
host_tick_rate 1781116972 # Simulator tick rate (ticks/s)
host_inst_rate 652561 # Simulator instruction rate (inst/s)
host_mem_usage 261720 # Number of bytes of host memory used
host_seconds 917.34 # Real time elapsed on the host
host_tick_rate 868554806 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated
sim_seconds 0.796760 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 216774877 # To
system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 392389 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,7 +52,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr

10
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 5 2010 14:46:04
M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch
M5 started Oct 5 2010 15:01:57
M5 executing on aus-bc2-b14
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:40:32
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3851747 # Simulator instruction rate (inst/s)
host_mem_usage 385600 # Number of bytes of host memory used
host_seconds 23.68 # Real time elapsed on the host
host_tick_rate 2289652632 # Simulator tick rate (ticks/s)
host_inst_rate 2560594 # Simulator instruction rate (inst/s)
host_mem_usage 386656 # Number of bytes of host memory used
host_seconds 35.62 # Real time elapsed on the host
host_tick_rate 1522136495 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.054216 # Number of seconds simulated

2
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -152,7 +152,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr

10
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 5 2010 14:46:04
M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch
M5 started Oct 5 2010 15:02:21
M5 executing on aus-bc2-b14
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:41:18
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 795252 # Simulator instruction rate (inst/s)
host_mem_usage 393312 # Number of bytes of host memory used
host_seconds 114.65 # Real time elapsed on the host
host_tick_rate 1291628028 # Simulator tick rate (ticks/s)
host_inst_rate 587679 # Simulator instruction rate (inst/s)
host_mem_usage 394372 # Number of bytes of host memory used
host_seconds 155.15 # Real time elapsed on the host
host_tick_rate 954493550 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91176087 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated

6
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,14 +52,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

10
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:44:22
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:37:50
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 4358961 # Simulator instruction rate (inst/s)
host_mem_usage 206092 # Number of bytes of host memory used
host_seconds 128.79 # Real time elapsed on the host
host_tick_rate 2218414400 # Simulator tick rate (ticks/s)
host_inst_rate 2845430 # Simulator instruction rate (inst/s)
host_mem_usage 257528 # Number of bytes of host memory used
host_seconds 197.30 # Real time elapsed on the host
host_tick_rate 1448130657 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 561403855 # Number of instructions simulated
sim_seconds 0.285717 # Number of seconds simulated
sim_ticks 285716811500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:07:44
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:30:07
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1404297 # Simulator instruction rate (inst/s)
host_mem_usage 200728 # Number of bytes of host memory used
host_seconds 398.40 # Real time elapsed on the host
host_tick_rate 1806912378 # Simulator tick rate (ticks/s)
host_inst_rate 698342 # Simulator instruction rate (inst/s)
host_mem_usage 265248 # Number of bytes of host memory used
host_seconds 801.14 # Real time elapsed on the host
host_tick_rate 898558125 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 559470527 # Number of instructions simulated
sim_seconds 0.719872 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 181914877 # To
system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1025629 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

10
tests/long/30.eon/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:34:42
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:19:59
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

32
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2356342 # Simulator instruction rate (inst/s)
host_mem_usage 210592 # Number of bytes of host memory used
host_seconds 146.32 # Real time elapsed on the host
host_tick_rate 1436586032 # Simulator tick rate (ticks/s)
host_inst_rate 2280191 # Simulator instruction rate (inst/s)
host_mem_usage 262416 # Number of bytes of host memory used
host_seconds 151.21 # Real time elapsed on the host
host_tick_rate 1390158822 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344777955 # Number of instructions simulated
sim_seconds 0.210200 # Number of seconds simulated
sim_ticks 210200321500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

8
tests/long/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:12:46
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:23:59
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1114146 # Simulator instruction rate (inst/s)
host_mem_usage 205224 # Number of bytes of host memory used
host_seconds 309.12 # Real time elapsed on the host
host_tick_rate 1701065680 # Simulator tick rate (ticks/s)
host_inst_rate 520438 # Simulator instruction rate (inst/s)
host_mem_usage 270128 # Number of bytes of host memory used
host_seconds 661.75 # Real time elapsed on the host
host_tick_rate 794599336 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344399678 # Number of instructions simulated
sim_seconds 0.525826 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 176645818 # To
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 998 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

10
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:34:43
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:04:52
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

32
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3147097 # Simulator instruction rate (inst/s)
host_mem_usage 207700 # Number of bytes of host memory used
host_seconds 585.86 # Real time elapsed on the host
host_tick_rate 1578574708 # Simulator tick rate (ticks/s)
host_inst_rate 2747008 # Simulator instruction rate (inst/s)
host_mem_usage 259372 # Number of bytes of host memory used
host_seconds 671.19 # Real time elapsed on the host
host_tick_rate 1377891283 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1843766922 # Number of instructions simulated
sim_seconds 0.924828 # Number of seconds simulated
sim_ticks 924828408500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

8
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:06:09
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:41:18
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1326917 # Simulator instruction rate (inst/s)
host_mem_usage 202424 # Number of bytes of host memory used
host_seconds 1381.15 # Real time elapsed on the host
host_tick_rate 1715881736 # Simulator tick rate (ticks/s)
host_inst_rate 628678 # Simulator instruction rate (inst/s)
host_mem_usage 267092 # Number of bytes of host memory used
host_seconds 2915.13 # Real time elapsed on the host
host_tick_rate 812964589 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1832675505 # Number of instructions simulated
sim_seconds 2.369896 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 895775787 # To
system.cpu.dcache.warmup_cycle 993944000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107259 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

10
tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:37:09
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:44:04
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

32
tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2664701 # Simulator instruction rate (inst/s)
host_mem_usage 209976 # Number of bytes of host memory used
host_seconds 37.09 # Real time elapsed on the host
host_tick_rate 1429827283 # Simulator tick rate (ticks/s)
host_inst_rate 2790357 # Simulator instruction rate (inst/s)
host_mem_usage 261760 # Number of bytes of host memory used
host_seconds 35.42 # Real time elapsed on the host
host_tick_rate 1497251955 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 98838077 # Number of instructions simulated
sim_seconds 0.053035 # Number of seconds simulated
sim_ticks 53034982000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

8
tests/long/50.vortex/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:54
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:37:39
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1323688 # Simulator instruction rate (inst/s)
host_mem_usage 204612 # Number of bytes of host memory used
host_seconds 74.03 # Real time elapsed on the host
host_tick_rate 1797531911 # Simulator tick rate (ticks/s)
host_inst_rate 607999 # Simulator instruction rate (inst/s)
host_mem_usage 269484 # Number of bytes of host memory used
host_seconds 161.18 # Real time elapsed on the host
host_tick_rate 825650483 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
sim_seconds 0.133079 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 46870204 # To
system.cpu.dcache.warmup_cycle 1079223000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 122819 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

10
tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:40:33
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:37:39
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

32
tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3154654 # Simulator instruction rate (inst/s)
host_mem_usage 202692 # Number of bytes of host memory used
host_seconds 541.87 # Real time elapsed on the host
host_tick_rate 1577328455 # Simulator tick rate (ticks/s)
host_inst_rate 2718053 # Simulator instruction rate (inst/s)
host_mem_usage 254288 # Number of bytes of host memory used
host_seconds 628.91 # Real time elapsed on the host
host_tick_rate 1359028059 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1709408682 # Number of instructions simulated
sim_seconds 0.854706 # Number of seconds simulated
sim_ticks 854705615000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

8
tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:06:16
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:48:19
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1373516 # Simulator instruction rate (inst/s)
host_mem_usage 197324 # Number of bytes of host memory used
host_seconds 1240.32 # Real time elapsed on the host
host_tick_rate 1960310324 # Simulator tick rate (ticks/s)
host_inst_rate 640383 # Simulator instruction rate (inst/s)
host_mem_usage 262008 # Number of bytes of host memory used
host_seconds 2660.29 # Real time elapsed on the host
host_tick_rate 913967481 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1703605163 # Number of instructions simulated
sim_seconds 2.431420 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 645855111 # To
system.cpu.dcache.warmup_cycle 25922969000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3061986 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

4
tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
View file

@ -52,12 +52,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
View file

@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:37:46
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:22:41
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 4206748 # Simulator instruction rate (inst/s)
host_mem_usage 205772 # Number of bytes of host memory used
host_seconds 44.41 # Real time elapsed on the host
host_tick_rate 2300875527 # Simulator tick rate (ticks/s)
host_inst_rate 2742393 # Simulator instruction rate (inst/s)
host_mem_usage 257424 # Number of bytes of host memory used
host_seconds 68.12 # Real time elapsed on the host
host_tick_rate 1499949275 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186818826 # Number of instructions simulated
sim_seconds 0.102181 # Number of seconds simulated
sim_ticks 102180734000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

10
tests/long/70.twolf/ref/arm/linux/simple-timing/simout
View file

@ -5,11 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:05:16
M5 executing on phenom
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 19:00:18
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

32
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1260082 # Simulator instruction rate (inst/s)
host_mem_usage 200384 # Number of bytes of host memory used
host_seconds 147.87 # Real time elapsed on the host
host_tick_rate 1569082964 # Simulator tick rate (ticks/s)
host_inst_rate 709254 # Simulator instruction rate (inst/s)
host_mem_usage 265144 # Number of bytes of host memory used
host_seconds 262.72 # Real time elapsed on the host
host_tick_rate 883179772 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186333855 # Number of instructions simulated
sim_seconds 0.232028 # Number of seconds simulated
@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 42025084 # To
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 16 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses

2
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
View file

@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/arm/linux/hello
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

10
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 24 2010 15:34:40
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
M5 started Aug 24 2010 15:34:42
M5 executing on zizzer
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:37:39
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!

32
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 6903 # Simulator instruction rate (inst/s)
host_mem_usage 198548 # Number of bytes of host memory used
host_seconds 0.81 # Real time elapsed on the host
host_tick_rate 3457658 # Simulator tick rate (ticks/s)
host_inst_rate 402550 # Simulator instruction rate (inst/s)
host_mem_usage 249936 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 197047093 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5620 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2816000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -19,8 +31,20 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses