stats: Update Ruby regressions for memory controller fix
This commit is contained in:
Joel Hestness
parent
6924e10978
commit
4124ea09f8
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@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
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type=System
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children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
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boot_osflags=a
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clock=1
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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@ -47,7 +48,6 @@ max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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profile=0
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progress_interval=0
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system=system
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@ -78,7 +78,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -119,9 +119,9 @@ bank_busy_time=11
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bank_queue_size=12
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banks_per_rank=8
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basic_bus_busy_time=2
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clock=3
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dimm_bit_0=12
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dimms_per_channel=2
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mem_bus_cycle_multiplier=10
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mem_ctl_latency=12
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mem_fixed_delay=0
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mem_random_arbitrate=0
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@ -130,6 +130,7 @@ rank_rank_delay=1
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ranks_per_dimm=2
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read_write_delay=2
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refresh_period=1560
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ruby_system=system.ruby
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tFaw=0
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version=0
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@ -183,6 +184,7 @@ tagArrayBanks=1
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[system.l1_cntrl0.sequencer]
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type=RubySequencer
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access_phys_mem=true
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clock=1
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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@ -227,6 +229,7 @@ tagArrayBanks=1
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[system.physmem]
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type=SimpleMemory
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clock=1
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conf_table_reported=false
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file=
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in_addr_map=true
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@ -351,6 +354,7 @@ ruby_system=system.ruby
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[system.sys_port_proxy]
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type=RubyPortProxy
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access_phys_mem=true
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clock=1
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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@ -1,26 +1,26 @@
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Real time: Jul/10/2012 17:30:50
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Real time: Sep/01/2012 14:02:52
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.62
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Virtual_time_in_minutes: 0.0103333
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Virtual_time_in_hours: 0.000172222
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Virtual_time_in_days: 7.17593e-06
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Virtual_time_in_seconds: 0.56
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Virtual_time_in_minutes: 0.00933333
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Virtual_time_in_hours: 0.000155556
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Virtual_time_in_days: 6.48148e-06
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Ruby_current_time: 279353
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Ruby_current_time: 138616
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Ruby_start_time: 0
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Ruby_cycles: 279353
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Ruby_cycles: 138616
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mbytes_resident: 47.9336
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mbytes_total: 230.535
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resident_ratio: 0.20794
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mbytes_resident: 49.5195
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mbytes_total: 259.898
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resident_ratio: 0.190594
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ruby_cycles_executed: [ 279354 ]
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ruby_cycles_executed: [ 138617 ]
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Busy Controller Counts:
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L1Cache-0:0
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@ -30,15 +30,15 @@ Directory-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
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sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency: [binsize: 1 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
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miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 37.6915 | standard deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 3 0 0 1 ]
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miss_latency_ST: [binsize: 1 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 ]
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miss_latency_IFETCH: [binsize: 1 max: 98 count: 6400 average: 10.5978 | standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 ]
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miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 0 0 0 6958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 269 472 460 8 43 37 35 30 26 2 16 29 14 0 4 0 0 2 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 1 0 1 6 0 0 1 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 37.6915 | standard deviation: 35.8089 | 0 0 0 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 211 147 0 28 22 17 10 4 2 12 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 3 0 0 1 ]
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miss_latency_ST_NULL: [binsize: 1 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 0 0 0 649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 37 82 0 6 10 3 3 6 0 4 20 5 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 ]
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miss_latency_IFETCH_NULL: [binsize: 1 max: 98 count: 6400 average: 10.5978 | standard deviation: 21.9071 | 0 0 0 5709 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 155 224 231 8 9 5 15 17 16 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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@ -65,10 +65,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
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Total_delay_cycles: [binsize: 1 max: 4 count: 9645 average: 0.0609642 | standard deviation: 0.490156 | 9498 0 0 0 147 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 2725 average: 0.21578 | standard deviation: 0.90398 | 2578 0 0 0 147 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@ -83,11 +83,11 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 13465
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page_faults: 0
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page_reclaims: 10172
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page_faults: 15
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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block_inputs: 1112
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block_outputs: 80
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Network Stats
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-------------
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@ -102,9 +102,9 @@ total_msgs: 37671 total_bytes: 976248
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 1.87549
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links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0: 3.77969
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links_utilized_percent_switch_0_link_0: 5.36987 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 2.1895 bw: 16000 base_latency: 1
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outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
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@ -116,9 +116,9 @@ links_utilized_percent_switch_0: 1.87549
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 3.64029
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links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1: 7.33627
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links_utilized_percent_switch_1_link_0: 7.45296 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 7.21959 bw: 16000 base_latency: 1
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outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
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@ -132,9 +132,9 @@ links_utilized_percent_switch_1: 3.64029
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 1.76479
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links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2: 3.55659
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links_utilized_percent_switch_2_link_0: 1.84971 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 5.26346 bw: 16000 base_latency: 1
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outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
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@ -144,10 +144,10 @@ links_utilized_percent_switch_2: 1.76479
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switch_3_inlinks: 3
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switch_3_outlinks: 3
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links_utilized_percent_switch_3: 2.42686
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links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3: 4.89085
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links_utilized_percent_switch_3_link_0: 5.36987 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 7.45296 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_2: 1.84971 bw: 16000 base_latency: 1
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outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -186,8 +186,8 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
Inv [1041 ] 1041
|
||||
L1_Replacement [1354 ] 1354
|
||||
|
|
@ -216,12 +216,12 @@ I Inv [0 ] 0
|
|||
I L1_Replacement [556 ] 556
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [5723 ] 5723
|
||||
S Ifetch [5709 ] 5709
|
||||
S Store [0 ] 0
|
||||
S Inv [325 ] 325
|
||||
S L1_Replacement [362 ] 362
|
||||
|
||||
E Load [454 ] 454
|
||||
E Load [452 ] 452
|
||||
E Ifetch [0 ] 0
|
||||
E Store [71 ] 71
|
||||
E Inv [219 ] 219
|
||||
|
|
@ -307,7 +307,7 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [691 ] 691
|
||||
L1_GETS [585 ] 585
|
||||
L1_GETS [583 ] 583
|
||||
L1_GETX [216 ] 216
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [436 ] 436
|
||||
|
|
@ -364,7 +364,7 @@ MT L2_Replacement_clean [352 ] 352
|
|||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [2 ] 2
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
|
|
@ -518,19 +518,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 1737
|
||||
memory_reads: 1460
|
||||
memory_writes: 277
|
||||
memory_refreshes: 582
|
||||
memory_total_request_delays: 821
|
||||
memory_delays_per_request: 0.472654
|
||||
memory_delays_in_input_queue: 84
|
||||
memory_refreshes: 963
|
||||
memory_total_request_delays: 341
|
||||
memory_delays_per_request: 0.196315
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 737
|
||||
memory_stalls_for_bank_busy: 197
|
||||
memory_delays_stalled_at_head_of_bank_queue: 341
|
||||
memory_stalls_for_bank_busy: 166
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 40
|
||||
memory_stalls_for_bus: 242
|
||||
memory_stalls_for_arbitration: 24
|
||||
memory_stalls_for_bus: 147
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 258
|
||||
memory_stalls_for_read_write_turnaround: 4
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:55:16
|
||||
gem5 started Aug 13 2012 18:08:58
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:01:54
|
||||
gem5 started Sep 1 2012 14:02:52
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 279353 because target called exit()
|
||||
Exiting @ tick 138616 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000279 # Number of seconds simulated
|
||||
sim_ticks 279353 # Number of ticks simulated
|
||||
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000139 # Number of seconds simulated
|
||||
sim_ticks 138616 # Number of ticks simulated
|
||||
final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30486 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30483 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1332529 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233960 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_inst_rate 27614 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27611 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 598893 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266140 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
|
|||
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 91640326 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 31458406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 123098732 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 91640326 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 91640326 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 91640326 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 55428078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 147068404 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 184682865 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 63398165 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 248081030 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 184682865 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 184682865 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 48306112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 48306112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 184682865 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 111704277 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 296387141 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 279353 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 138616 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -103,7 +103,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 279353 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 138616 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -118,9 +118,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -129,6 +129,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -180,6 +181,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -223,6 +225,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -347,6 +350,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:36:36
|
||||
Real time: Sep/01/2012 14:11:17
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.67
|
||||
Virtual_time_in_minutes: 0.0111667
|
||||
Virtual_time_in_hours: 0.000186111
|
||||
Virtual_time_in_days: 7.75463e-06
|
||||
Virtual_time_in_seconds: 0.58
|
||||
Virtual_time_in_minutes: 0.00966667
|
||||
Virtual_time_in_hours: 0.000161111
|
||||
Virtual_time_in_days: 6.71296e-06
|
||||
|
||||
Ruby_current_time: 223694
|
||||
Ruby_current_time: 117611
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 223694
|
||||
Ruby_cycles: 117611
|
||||
|
||||
mbytes_resident: 48.0078
|
||||
mbytes_total: 230.77
|
||||
resident_ratio: 0.208051
|
||||
mbytes_resident: 49.6211
|
||||
mbytes_total: 260.035
|
||||
resident_ratio: 0.190885
|
||||
|
||||
ruby_cycles_executed: [ 223695 ]
|
||||
ruby_cycles_executed: [ 117612 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L2Cache-0:0
|
||||
|
|
@ -30,15 +30,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -83,11 +83,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 13444
|
||||
page_faults: 0
|
||||
page_reclaims: 10188
|
||||
page_faults: 19
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_inputs: 1176
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -102,9 +102,9 @@ total_msgs: 44262 total_bytes: 1125744
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 5.24221
|
||||
links_utilized_percent_switch_0_link_0: 6.11058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.37383 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 9.97058
|
||||
links_utilized_percent_switch_0_link_0: 11.6222 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 8.31895 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -120,9 +120,9 @@ links_utilized_percent_switch_0: 5.24221
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 3.33894
|
||||
links_utilized_percent_switch_1_link_0: 3.04255 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 3.63532 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 6.3506
|
||||
links_utilized_percent_switch_1_link_0: 5.78687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 6.91432 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 3.33894
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.90327
|
||||
links_utilized_percent_switch_2_link_0: 1.33128 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.47526 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 3.61998
|
||||
links_utilized_percent_switch_2_link_0: 2.53208 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.70789 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.90327
|
|||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 3.4948
|
||||
links_utilized_percent_switch_3_link_0: 6.11058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.04255 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.33128 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 6.64705
|
||||
links_utilized_percent_switch_3_link_0: 11.6222 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 5.78687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 2.53208 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -183,8 +183,8 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
L1_Replacement [1379 ] 1379
|
||||
Own_GETX [0 ] 0
|
||||
|
|
@ -224,8 +224,8 @@ O Fwd_GETX [0 ] 0
|
|||
O Fwd_GETS [0 ] 0
|
||||
O Fwd_DMA [0 ] 0
|
||||
|
||||
M Load [307 ] 307
|
||||
M Ifetch [3481 ] 3481
|
||||
M Load [305 ] 305
|
||||
M Ifetch [3467 ] 3467
|
||||
M Store [51 ] 51
|
||||
M L1_Replacement [1086 ] 1086
|
||||
M Fwd_GETX [0 ] 0
|
||||
|
|
@ -1199,19 +1199,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 1303
|
||||
memory_reads: 1109
|
||||
memory_writes: 194
|
||||
memory_refreshes: 466
|
||||
memory_total_request_delays: 279
|
||||
memory_delays_per_request: 0.214121
|
||||
memory_delays_in_input_queue: 12
|
||||
memory_refreshes: 817
|
||||
memory_total_request_delays: 115
|
||||
memory_delays_per_request: 0.0882579
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 267
|
||||
memory_stalls_for_bank_busy: 123
|
||||
memory_delays_stalled_at_head_of_bank_queue: 115
|
||||
memory_stalls_for_bank_busy: 40
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 16
|
||||
memory_stalls_for_bus: 58
|
||||
memory_stalls_for_arbitration: 17
|
||||
memory_stalls_for_bus: 55
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 70
|
||||
memory_stalls_for_read_write_turnaround: 3
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 74 17 45 40 54 99 29 16 19 22 31 34 52 48 38 30 39 21 21 27 28 37 55 22 31 21 32 69 84 103 13 52
|
||||
|
||||
|
|
@ -1240,7 +1240,7 @@ I GETS [979 ] 979
|
|||
I PUTX [0 ] 0
|
||||
I PUTO [0 ] 0
|
||||
I Memory_Data [0 ] 0
|
||||
I Memory_Ack [190 ] 190
|
||||
I Memory_Ack [193 ] 193
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -1281,7 +1281,7 @@ IS PUTO_SHARERS [0 ] 0
|
|||
IS Unblock [0 ] 0
|
||||
IS Exclusive_Unblock [979 ] 979
|
||||
IS Memory_Data [979 ] 979
|
||||
IS Memory_Ack [3 ] 3
|
||||
IS Memory_Ack [1 ] 1
|
||||
IS DMA_READ [0 ] 0
|
||||
IS DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -1328,7 +1328,7 @@ MM PUTO [0 ] 0
|
|||
MM PUTO_SHARERS [0 ] 0
|
||||
MM Exclusive_Unblock [130 ] 130
|
||||
MM Memory_Data [130 ] 130
|
||||
MM Memory_Ack [1 ] 1
|
||||
MM Memory_Ack [0 ] 0
|
||||
MM DMA_READ [0 ] 0
|
||||
MM DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:57:01
|
||||
gem5 started Aug 13 2012 18:09:22
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:10:16
|
||||
gem5 started Sep 1 2012 14:11:17
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 223694 because target called exit()
|
||||
Exiting @ tick 117611 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000224 # Number of seconds simulated
|
||||
sim_ticks 223694 # Number of ticks simulated
|
||||
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000118 # Number of seconds simulated
|
||||
sim_ticks 117611 # Number of ticks simulated
|
||||
final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 29074 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29072 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1017648 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 235156 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
host_inst_rate 24451 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24449 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 449950 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266280 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
|
|||
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 114442050 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 39285810 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 153727860 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 114442050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 114442050 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 114442050 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 69219559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 183661609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 217666715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 74720902 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 292387617 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 217666715 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 217666715 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 56933450 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 56933450 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 217666715 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 131654352 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 349321067 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 223694 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 117611 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -103,7 +103,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 223694 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 117611 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -121,9 +121,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -132,6 +132,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -214,6 +215,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -229,6 +231,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -330,6 +333,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:50:25
|
||||
Real time: Sep/01/2012 13:54:22
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.53
|
||||
Virtual_time_in_minutes: 0.00883333
|
||||
Virtual_time_in_hours: 0.000147222
|
||||
Virtual_time_in_days: 6.13426e-06
|
||||
Virtual_time_in_seconds: 0.47
|
||||
Virtual_time_in_minutes: 0.00783333
|
||||
Virtual_time_in_hours: 0.000130556
|
||||
Virtual_time_in_days: 5.43981e-06
|
||||
|
||||
Ruby_current_time: 208400
|
||||
Ruby_current_time: 93341
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 208400
|
||||
Ruby_cycles: 93341
|
||||
|
||||
mbytes_resident: 45.6484
|
||||
mbytes_total: 228.203
|
||||
resident_ratio: 0.200068
|
||||
mbytes_resident: 47.3203
|
||||
mbytes_total: 257.496
|
||||
resident_ratio: 0.183832
|
||||
|
||||
ruby_cycles_executed: [ 208401 ]
|
||||
ruby_cycles_executed: [ 93342 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -29,17 +29,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
|
||||
miss_latency: [binsize: 1 max: 128 count: 8448 average: 10.0489 | standard deviation: 19.8982 | 0 0 7086 0 0 0 0 0 0 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840 107 39 100 1 1 10 0 0 4 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 3 0 16 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 1 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 122 count: 1183 average: 22.776 | standard deviation: 26.5223 | 0 0 658 0 0 0 0 0 0 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 314 33 13 37 0 0 6 0 0 1 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 0 0 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
|
||||
miss_latency_ST: [binsize: 1 max: 128 count: 865 average: 14.3214 | standard deviation: 27.0647 | 0 0 674 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108 7 1 11 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 90 count: 6400 average: 7.11891 | standard deviation: 15.9003 | 0 0 5754 0 0 0 0 0 0 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 418 67 25 52 0 1 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7 0 0 2 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7086 average: 2 | standard deviation: 0 | 0 0 7086 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 1 max: 128 count: 1159 average: 58.742 | standard deviation: 10.823 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840 107 39 100 1 1 10 0 0 4 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 3 0 16 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 1 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -47,18 +47,18 @@ miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 avera
|
|||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
imcomplete_dir_Times: 1158
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 658 average: 2 | standard deviation: 0 | 0 0 658 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_Directory: [binsize: 1 max: 122 count: 420 average: 57.769 | standard deviation: 7.42617 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 314 33 13 37 0 0 6 0 0 1 0 0 2 0 0 1 0 0 2 0 0 0 0 0 1 0 0 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
|
||||
miss_latency_ST_Directory: [binsize: 1 max: 128 count: 158 average: 67.1582 | standard deviation: 23.8632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108 7 1 11 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5754 average: 2 | standard deviation: 0 | 0 0 5754 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 90 count: 581 average: 57.1566 | standard deviation: 4.1703 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 418 67 25 52 0 1 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7 0 0 2 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -90,11 +90,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12815
|
||||
page_faults: 0
|
||||
page_reclaims: 9600
|
||||
page_faults: 19
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_inputs: 1136
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -108,9 +108,9 @@ total_msgs: 20718 total_bytes: 430512
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.15187
|
||||
links_utilized_percent_switch_0_link_0: 2.77687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.52687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 4.80443
|
||||
links_utilized_percent_switch_0_link_0: 6.19985 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 3.40901 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -121,9 +121,9 @@ links_utilized_percent_switch_0: 2.15187
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.15187
|
||||
links_utilized_percent_switch_1_link_0: 1.52687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.77687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 4.80443
|
||||
links_utilized_percent_switch_1_link_0: 3.40901 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 6.19985 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 2.15187
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.15187
|
||||
links_utilized_percent_switch_2_link_0: 2.77687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.52687 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 4.80443
|
||||
links_utilized_percent_switch_2_link_0: 6.19985 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 3.40901 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -183,8 +183,8 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1193 ] 1193
|
||||
Ifetch [6425 ] 6425
|
||||
Load [1191 ] 1191
|
||||
Ifetch [6411 ] 6411
|
||||
Store [892 ] 892
|
||||
L2_Replacement [1143 ] 1143
|
||||
L1_to_L2 [1354 ] 1354
|
||||
|
|
@ -253,8 +253,8 @@ O NC_DMA_GETS [0 ] 0
|
|||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [306 ] 306
|
||||
M Ifetch [5768 ] 5768
|
||||
M Load [304 ] 304
|
||||
M Ifetch [5754 ] 5754
|
||||
M Store [60 ] 60
|
||||
M L2_Replacement [923 ] 923
|
||||
M L1_to_L2 [1061 ] 1061
|
||||
|
|
@ -590,26 +590,26 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 1379
|
||||
memory_reads: 1159
|
||||
memory_writes: 220
|
||||
memory_refreshes: 435
|
||||
memory_total_request_delays: 495
|
||||
memory_delays_per_request: 0.358956
|
||||
memory_delays_in_input_queue: 3
|
||||
memory_refreshes: 649
|
||||
memory_total_request_delays: 167
|
||||
memory_delays_per_request: 0.121102
|
||||
memory_delays_in_input_queue: 1
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 492
|
||||
memory_stalls_for_bank_busy: 124
|
||||
memory_delays_stalled_at_head_of_bank_queue: 166
|
||||
memory_stalls_for_bank_busy: 114
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 23
|
||||
memory_stalls_for_bus: 78
|
||||
memory_stalls_for_arbitration: 11
|
||||
memory_stalls_for_bus: 33
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 267
|
||||
memory_stalls_for_read_write_turnaround: 8
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [189 ] 189
|
||||
GETS [1027 ] 1027
|
||||
GETX [186 ] 186
|
||||
GETS [1022 ] 1022
|
||||
PUT [1143 ] 1143
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
|
|
@ -909,8 +909,8 @@ WB_O_W DMA_WRITE [0 ] 0
|
|||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [4 ] 4
|
||||
WB_E_W GETS [7 ] 7
|
||||
WB_E_W GETX [1 ] 1
|
||||
WB_E_W GETS [2 ] 2
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:53:31
|
||||
gem5 started Aug 13 2012 18:06:43
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 13:53:26
|
||||
gem5 started Sep 1 2012 13:54:22
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 208110 because target called exit()
|
||||
Exiting @ tick 93341 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 208110 # Number of ticks simulated
|
||||
final_tick 208110 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000093 # Number of seconds simulated
|
||||
sim_ticks 93341 # Number of ticks simulated
|
||||
final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 43199 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1406596 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231928 # Number of bytes of host memory used
|
||||
host_inst_rate 42148 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42141 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 615474 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263680 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
|
|||
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 123011869 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 42227668 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 165239537 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 123011869 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 123011869 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 32175292 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 32175292 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 123011869 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 74402960 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 197414829 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 274263186 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 94149409 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 368412595 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 274263186 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 274263186 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 71736964 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 71736964 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 274263186 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 165886374 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 440149559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -90,7 +90,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 208110 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 93341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -109,7 +109,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 208110 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 93341 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -118,9 +118,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -129,6 +129,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -165,6 +166,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
|
|
@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -281,6 +284,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:16:10
|
||||
Real time: Sep/01/2012 13:43:15
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.53
|
||||
Virtual_time_in_minutes: 0.00883333
|
||||
Virtual_time_in_hours: 0.000147222
|
||||
Virtual_time_in_days: 6.13426e-06
|
||||
Virtual_time_in_seconds: 0.47
|
||||
Virtual_time_in_minutes: 0.00783333
|
||||
Virtual_time_in_hours: 0.000130556
|
||||
Virtual_time_in_days: 5.43981e-06
|
||||
|
||||
Ruby_current_time: 342698
|
||||
Ruby_current_time: 143853
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 342698
|
||||
Ruby_cycles: 143853
|
||||
|
||||
mbytes_resident: 46.8906
|
||||
mbytes_total: 229.363
|
||||
resident_ratio: 0.204455
|
||||
mbytes_resident: 48.5508
|
||||
mbytes_total: 258.688
|
||||
resident_ratio: 0.187727
|
||||
|
||||
ruby_cycles_executed: [ 342699 ]
|
||||
ruby_cycles_executed: [ 143854 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -29,16 +29,16 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 1 max: 123 count: 8448 average: 16.0281 | standard deviation: 25.9113 | 0 0 0 6718 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 14 10 309 629 543 10 7 7 7 24 22 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 42 37 51 2 1 1 3 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 98 count: 1183 average: 41.5604 | standard deviation: 30.9227 | 0 0 0 456 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 9 4 103 318 220 1 4 2 4 12 9 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 10 13 11 1 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 95 count: 865 average: 23.8058 | standard deviation: 31.1488 | 0 0 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 27 63 122 1 2 4 0 3 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 6 30 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 123 count: 6400 average: 10.2573 | standard deviation: 20.4119 | 0 0 0 5670 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 5 179 248 201 8 1 1 3 9 6 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 27 18 10 1 1 0 3 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6718 average: 3 | standard deviation: 0 | 0 0 0 6718 ]
|
||||
miss_latency_Directory: [binsize: 1 max: 123 count: 1730 average: 66.6191 | standard deviation: 7.72578 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 14 10 309 629 543 10 7 7 7 24 22 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 42 37 51 2 1 1 3 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -47,14 +47,14 @@ imcomplete_wCC_Times: 0
|
|||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 1729
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 456 average: 3 | standard deviation: 0 | 0 0 0 456 ]
|
||||
miss_latency_LD_Directory: [binsize: 1 max: 98 count: 727 average: 65.7469 | standard deviation: 6.09023 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 9 4 103 318 220 1 4 2 4 12 9 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 10 13 11 1 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 1 max: 95 count: 273 average: 68.9231 | standard deviation: 9.83653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 27 63 122 1 2 4 0 3 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 6 30 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5670 average: 3 | standard deviation: 0 | 0 0 0 5670 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 123 count: 730 average: 66.626 | standard deviation: 8.11043 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 5 179 248 201 8 1 1 3 9 6 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 27 18 10 1 1 0 3 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -86,11 +86,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 13155
|
||||
page_reclaims: 9931
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -103,9 +103,9 @@ total_msgs: 20736 total_bytes: 829440
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.52117
|
||||
links_utilized_percent_switch_0_link_0: 2.5235 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.51884 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 6.00613
|
||||
links_utilized_percent_switch_0_link_0: 6.01169 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 6.00057 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -114,9 +114,9 @@ links_utilized_percent_switch_0: 2.52117
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.52117
|
||||
links_utilized_percent_switch_1_link_0: 2.51884 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.5235 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 6.00613
|
||||
links_utilized_percent_switch_1_link_0: 6.00057 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 6.01169 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -125,9 +125,9 @@ links_utilized_percent_switch_1: 2.52117
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.52117
|
||||
links_utilized_percent_switch_2_link_0: 2.5235 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.51884 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 6.00613
|
||||
links_utilized_percent_switch_2_link_0: 6.01169 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 6.00057 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -149,8 +149,8 @@ Cache Stats: system.l1_cntrl0.cacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Load [1183 ] 1183
|
||||
Ifetch [6400 ] 6400
|
||||
Store [865 ] 865
|
||||
Data [1730 ] 1730
|
||||
Fwd_GETX [0 ] 0
|
||||
|
|
@ -168,8 +168,8 @@ I Replacement [0 ] 0
|
|||
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load [458 ] 458
|
||||
M Ifetch [5684 ] 5684
|
||||
M Load [456 ] 456
|
||||
M Ifetch [5670 ] 5670
|
||||
M Store [592 ] 592
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
|
|
@ -190,19 +190,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 3456
|
||||
memory_reads: 1730
|
||||
memory_writes: 1726
|
||||
memory_refreshes: 714
|
||||
memory_total_request_delays: 4411
|
||||
memory_delays_per_request: 1.27633
|
||||
memory_delays_in_input_queue: 1083
|
||||
memory_delays_behind_head_of_bank_queue: 8
|
||||
memory_delays_stalled_at_head_of_bank_queue: 3320
|
||||
memory_stalls_for_bank_busy: 1509
|
||||
memory_refreshes: 999
|
||||
memory_total_request_delays: 3048
|
||||
memory_delays_per_request: 0.881944
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 11
|
||||
memory_delays_stalled_at_head_of_bank_queue: 3037
|
||||
memory_stalls_for_bank_busy: 1500
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 99
|
||||
memory_stalls_for_bus: 1677
|
||||
memory_stalls_for_arbitration: 107
|
||||
memory_stalls_for_bus: 1375
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 35
|
||||
memory_stalls_for_read_write_turnaround: 55
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 13 2012 16:51:51
|
||||
gem5 started Aug 13 2012 17:17:12
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 13:41:29
|
||||
gem5 started Sep 1 2012 13:43:15
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 342698 because target called exit()
|
||||
Exiting @ tick 143853 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000343 # Number of seconds simulated
|
||||
sim_ticks 342698 # Number of ticks simulated
|
||||
final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000144 # Number of seconds simulated
|
||||
sim_ticks 143853 # Number of ticks simulated
|
||||
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30634 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1642762 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233644 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_inst_rate 43143 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43136 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 970941 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264900 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1183 # Nu
|
|||
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 74701341 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 25643570 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 100344910 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 74701341 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 74701341 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 74701341 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 45182639 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 119883979 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 177959445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 61090141 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 239049585 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 177959445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 177959445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 46547517 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 46547517 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 177959445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 107637658 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 285597103 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -72,7 +72,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 342698 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 143853 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -91,7 +91,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 342698 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 143853 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -119,9 +119,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -130,6 +130,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -183,6 +184,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -227,6 +229,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -351,6 +354,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:31:25
|
||||
Real time: Sep/01/2012 14:03:04
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.47
|
||||
Virtual_time_in_minutes: 0.00783333
|
||||
Virtual_time_in_hours: 0.000130556
|
||||
Virtual_time_in_days: 5.43981e-06
|
||||
Virtual_time_in_seconds: 0.41
|
||||
Virtual_time_in_minutes: 0.00683333
|
||||
Virtual_time_in_hours: 0.000113889
|
||||
Virtual_time_in_days: 4.74537e-06
|
||||
|
||||
Ruby_current_time: 104867
|
||||
Ruby_current_time: 52575
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 104867
|
||||
Ruby_cycles: 52575
|
||||
|
||||
mbytes_resident: 45.3203
|
||||
mbytes_total: 228.348
|
||||
resident_ratio: 0.198488
|
||||
mbytes_resident: 46.8984
|
||||
mbytes_total: 257.648
|
||||
resident_ratio: 0.182086
|
||||
|
||||
ruby_cycles_executed: [ 104868 ]
|
||||
ruby_cycles_executed: [ 52576 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -34,11 +34,11 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 275 count: 3294 average: 30.8358 | standard deviation: 62.2139 | 0 2722 0 0 0 0 0 0 0 23 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62 131 87 117 74 6 17 4 2 2 1 11 10 5 4 3 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 1 max: 116 count: 3294 average: 14.9608 | standard deviation: 26.5582 | 0 0 0 2722 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 178 170 5 17 15 15 11 9 0 5 5 3 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 116 count: 415 average: 36.7566 | standard deviation: 35.7458 | 0 0 0 211 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 70 54 1 10 7 8 4 0 0 4 4 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 106 count: 294 average: 18.915 | standard deviation: 29.8083 | 0 0 0 226 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 17 15 0 6 5 3 2 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 89 count: 2585 average: 11.012 | standard deviation: 22.3546 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 91 101 4 1 3 4 5 9 0 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_NULL: [binsize: 1 max: 116 count: 3294 average: 14.9608 | standard deviation: 26.5582 | 0 0 0 2722 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 178 170 5 17 15 15 11 9 0 5 5 3 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 235 count: 415 average: 80.7349 | standard deviation: 83.1868 | 0 211 0 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 46 24 49 14 4 7 4 1 1 0 5 0 4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 275 count: 294 average: 39.8435 | standard deviation: 69.7713 | 0 226 0 0 0 0 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 19 3 12 8 0 8 0 0 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 267 count: 2585 average: 21.8004 | standard deviation: 52.7361 | 0 2285 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 66 60 56 52 2 2 0 1 1 1 5 9 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 1 max: 116 count: 415 average: 36.7566 | standard deviation: 35.7458 | 0 0 0 211 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 70 54 1 10 7 8 4 0 0 4 4 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 1 max: 106 count: 294 average: 18.915 | standard deviation: 29.8083 | 0 0 0 226 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 17 15 0 6 5 3 2 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 89 count: 2585 average: 11.012 | standard deviation: 22.3546 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 91 101 4 1 3 4 5 9 0 0 0 0 0 0 0 1 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -65,10 +65,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 4 count: 3612 average: 0.0520487 | standard deviation: 0.453608 | 3565 0 0 0 47 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2644 average: 0 | standard deviation: 0 | 2644 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 968 average: 0.194215 | standard deviation: 0.860485 | 921 0 0 0 47 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -83,11 +83,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12765
|
||||
page_reclaims: 9494
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -102,9 +102,9 @@ total_msgs: 14094 total_bytes: 368304
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.90098
|
||||
links_utilized_percent_switch_0_link_0: 2.71916 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.0828 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 3.79173
|
||||
links_utilized_percent_switch_0_link_0: 5.42368 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.15977 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -116,9 +116,9 @@ links_utilized_percent_switch_0: 1.90098
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 3.65844
|
||||
links_utilized_percent_switch_1_link_0: 3.68705 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 3.62984 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 7.29719
|
||||
links_utilized_percent_switch_1_link_0: 7.35426 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 7.24013 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -132,9 +132,9 @@ links_utilized_percent_switch_1: 3.65844
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.75746
|
||||
links_utilized_percent_switch_2_link_0: 0.910677 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.60425 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 3.50547
|
||||
links_utilized_percent_switch_2_link_0: 1.81645 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 5.19448 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -144,10 +144,10 @@ links_utilized_percent_switch_2: 1.75746
|
|||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 2.43896
|
||||
links_utilized_percent_switch_3_link_0: 2.71916 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.68705 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.910677 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 4.8648
|
||||
links_utilized_percent_switch_3_link_0: 5.42368 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 7.35426 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.81645 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -307,8 +307,8 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [300 ] 300
|
||||
L1_GETS [205 ] 205
|
||||
L1_GETX [69 ] 69
|
||||
L1_GETS [204 ] 204
|
||||
L1_GETX [68 ] 68
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [124 ] 124
|
||||
L1_PUTX_old [0 ] 0
|
||||
|
|
@ -364,8 +364,8 @@ MT L2_Replacement_clean [141 ] 141
|
|||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [1 ] 1
|
||||
M_I L1_GETX [1 ] 1
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
|
|
@ -518,19 +518,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 650
|
||||
memory_reads: 547
|
||||
memory_writes: 103
|
||||
memory_refreshes: 219
|
||||
memory_total_request_delays: 306
|
||||
memory_delays_per_request: 0.470769
|
||||
memory_delays_in_input_queue: 27
|
||||
memory_refreshes: 365
|
||||
memory_total_request_delays: 117
|
||||
memory_delays_per_request: 0.18
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 279
|
||||
memory_stalls_for_bank_busy: 56
|
||||
memory_delays_stalled_at_head_of_bank_queue: 117
|
||||
memory_stalls_for_bank_busy: 63
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 9
|
||||
memory_stalls_for_bus: 94
|
||||
memory_stalls_for_arbitration: 8
|
||||
memory_stalls_for_bus: 46
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 120
|
||||
memory_stalls_for_read_write_turnaround: 0
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:30:15
|
||||
gem5 started Jul 28 2012 11:35:39
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:01:54
|
||||
gem5 started Sep 1 2012 14:03:04
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 104867 because target called exit()
|
||||
Exiting @ tick 52575 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000105 # Number of seconds simulated
|
||||
sim_ticks 104867 # Number of ticks simulated
|
||||
final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000053 # Number of seconds simulated
|
||||
sim_ticks 52575 # Number of ticks simulated
|
||||
final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22041 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22037 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 896641 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231628 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 27172 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27165 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 554084 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263836 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu
|
|||
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 196671422 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 57365668 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 254037090 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 196671422 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 196671422 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 39144080 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 39144080 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 196671422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 96509748 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 293181170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 104867 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 52575 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -103,7 +103,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 104867 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 52575 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -118,9 +118,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -129,6 +129,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -180,6 +181,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -223,6 +225,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -347,6 +350,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:37:10
|
||||
Real time: Sep/01/2012 14:11:29
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.48
|
||||
Virtual_time_in_minutes: 0.008
|
||||
Virtual_time_in_hours: 0.000133333
|
||||
Virtual_time_in_days: 5.55556e-06
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 85418
|
||||
Ruby_current_time: 44968
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 85418
|
||||
Ruby_cycles: 44968
|
||||
|
||||
mbytes_resident: 45.4062
|
||||
mbytes_total: 228.586
|
||||
resident_ratio: 0.198657
|
||||
mbytes_resident: 46.9961
|
||||
mbytes_total: 257.863
|
||||
resident_ratio: 0.182313
|
||||
|
||||
ruby_cycles_executed: [ 85419 ]
|
||||
ruby_cycles_executed: [ 44969 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L2Cache-0:0
|
||||
|
|
@ -34,11 +34,11 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 281 count: 3294 average: 24.9314 | standard deviation: 56.0488 | 0 2784 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 91 84 78 63 5 2 2 1 3 3 0 2 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_NULL: [binsize: 1 max: 115 count: 3294 average: 12.6515 | standard deviation: 24.0471 | 0 0 0 2784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126 124 112 20 18 9 5 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 277 count: 415 average: 60.9277 | standard deviation: 78.686 | 0 233 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 17 41 19 25 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 245 count: 294 average: 28.5238 | standard deviation: 59.597 | 0 236 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 3 12 7 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 281 count: 2585 average: 18.7439 | standard deviation: 48.5885 | 0 2315 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 57 40 47 31 2 2 2 1 3 2 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 1 max: 115 count: 415 average: 28.8699 | standard deviation: 33.4854 | 0 0 0 233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 44 27 6 0 2 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 1 max: 82 count: 294 average: 14.5476 | standard deviation: 25.7644 | 0 0 0 236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 10 12 1 0 0 0 1 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 101 count: 2585 average: 9.83211 | standard deviation: 20.7704 | 0 0 0 2315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 80 66 4 6 6 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -83,11 +83,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12740
|
||||
page_reclaims: 9533
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -102,9 +102,9 @@ total_msgs: 16577 total_bytes: 422728
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 5.15524
|
||||
links_utilized_percent_switch_0_link_0: 6.00225 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.30823 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 9.79252
|
||||
links_utilized_percent_switch_0_link_0: 11.4014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 8.1836 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -120,9 +120,9 @@ links_utilized_percent_switch_0: 5.15524
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 3.2581
|
||||
links_utilized_percent_switch_1_link_0: 2.98064 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 3.53555 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 6.18885
|
||||
links_utilized_percent_switch_1_link_0: 5.6618 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 6.71589 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 87 6264 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 3.2581
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.89685
|
||||
links_utilized_percent_switch_2_link_0: 1.327 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.46669 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 3.60312
|
||||
links_utilized_percent_switch_2_link_0: 2.52068 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.68555 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 423 3384 [ 0 423 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 76 5472 [ 0 0 76 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -147,10 +147,10 @@ links_utilized_percent_switch_2: 1.89685
|
|||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 3.43682
|
||||
links_utilized_percent_switch_3_link_0: 6.00225 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 2.98064 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.32759 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 6.52835
|
||||
links_utilized_percent_switch_3_link_0: 11.4014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 5.6618 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 2.52179 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 510 4080 [ 510 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 423 30456 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -1199,19 +1199,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 499
|
||||
memory_reads: 423
|
||||
memory_writes: 76
|
||||
memory_refreshes: 178
|
||||
memory_total_request_delays: 116
|
||||
memory_delays_per_request: 0.232465
|
||||
memory_delays_in_input_queue: 2
|
||||
memory_refreshes: 313
|
||||
memory_total_request_delays: 77
|
||||
memory_delays_per_request: 0.154309
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 114
|
||||
memory_stalls_for_bank_busy: 56
|
||||
memory_delays_stalled_at_head_of_bank_queue: 77
|
||||
memory_stalls_for_bank_busy: 41
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 10
|
||||
memory_stalls_for_arbitration: 9
|
||||
memory_stalls_for_bus: 25
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 23
|
||||
memory_stalls_for_read_write_turnaround: 2
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 18 10 0 34 20 19 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 15 5 5 12 12 18 14 56
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:32:56
|
||||
gem5 started Jul 28 2012 11:35:53
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:10:16
|
||||
gem5 started Sep 1 2012 14:11:29
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 85418 because target called exit()
|
||||
Exiting @ tick 44968 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000085 # Number of seconds simulated
|
||||
sim_ticks 85418 # Number of ticks simulated
|
||||
final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000045 # Number of seconds simulated
|
||||
sim_ticks 44968 # Number of ticks simulated
|
||||
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1284 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1284 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232824 # Number of bytes of host memory used
|
||||
host_seconds 2.01 # Real time elapsed on the host
|
||||
host_inst_rate 22673 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22668 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 395469 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264056 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu
|
|||
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 229941292 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 67069916 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 297011208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 229941292 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 229941292 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 45765878 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 45765878 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 229941292 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 112835794 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 342777086 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -84,7 +84,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 85418 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 44968 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -103,7 +103,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 85418 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 44968 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -47,7 +48,6 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
|
|
@ -78,7 +78,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -121,9 +121,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -132,6 +132,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -214,6 +215,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -229,6 +231,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -330,6 +333,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,26 +1,26 @@
|
|||
Real time: Jul/10/2012 17:50:59
|
||||
Real time: Sep/01/2012 13:54:35
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.42
|
||||
Virtual_time_in_minutes: 0.007
|
||||
Virtual_time_in_hours: 0.000116667
|
||||
Virtual_time_in_days: 4.86111e-06
|
||||
Virtual_time_in_seconds: 0.39
|
||||
Virtual_time_in_minutes: 0.0065
|
||||
Virtual_time_in_hours: 0.000108333
|
||||
Virtual_time_in_days: 4.51389e-06
|
||||
|
||||
Ruby_current_time: 78448
|
||||
Ruby_current_time: 35432
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 78448
|
||||
Ruby_cycles: 35432
|
||||
|
||||
mbytes_resident: 44.0312
|
||||
mbytes_total: 227.02
|
||||
resident_ratio: 0.193988
|
||||
mbytes_resident: 47.6953
|
||||
mbytes_total: 256.324
|
||||
resident_ratio: 0.186135
|
||||
|
||||
ruby_cycles_executed: [ 78449 ]
|
||||
ruby_cycles_executed: [ 35433 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -33,13 +33,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
|
||||
miss_latency: [binsize: 1 max: 122 count: 3294 average: 9.75653 | standard deviation: 19.3896 | 0 0 2784 0 0 0 0 0 0 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ]
|
||||
miss_latency_LD: [binsize: 1 max: 122 count: 415 average: 22.8313 | standard deviation: 27.0523 | 0 0 233 0 0 0 0 0 0 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
miss_latency_ST: [binsize: 1 max: 122 count: 294 average: 12.0102 | standard deviation: 23.154 | 0 0 236 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 83 count: 2585 average: 7.40116 | standard deviation: 16.3551 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 1 max: 122 count: 441 average: 58.2154 | standard deviation: 8.81927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 327 37 9 38 4 1 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 2 1 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -47,18 +47,18 @@ miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 avera
|
|||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
imcomplete_dir_Times: 440
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_Directory: [binsize: 1 max: 122 count: 146 average: 58.5 | standard deviation: 9.33625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110 14 1 9 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 1 max: 122 count: 47 average: 62.0426 | standard deviation: 18.5144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 0 2 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 83 count: 248 average: 57.3226 | standard deviation: 4.46262 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181 23 6 25 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 5 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -90,11 +90,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 12375
|
||||
page_reclaims: 9203
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -108,9 +108,9 @@ total_msgs: 7791 total_bytes: 162552
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.15844
|
||||
links_utilized_percent_switch_0_link_0: 2.80058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.51629 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 4.77887
|
||||
links_utilized_percent_switch_0_link_0: 6.20061 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 3.35713 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -121,9 +121,9 @@ links_utilized_percent_switch_0: 2.15844
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.15844
|
||||
links_utilized_percent_switch_1_link_0: 1.51629 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.80058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 4.77887
|
||||
links_utilized_percent_switch_1_link_0: 3.35713 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 6.20061 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -134,9 +134,9 @@ links_utilized_percent_switch_1: 2.15844
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.15844
|
||||
links_utilized_percent_switch_2_link_0: 2.80058 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.51629 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 4.77887
|
||||
links_utilized_percent_switch_2_link_0: 6.20061 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 3.35713 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -590,25 +590,25 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 522
|
||||
memory_reads: 441
|
||||
memory_writes: 81
|
||||
memory_refreshes: 164
|
||||
memory_total_request_delays: 151
|
||||
memory_delays_per_request: 0.289272
|
||||
memory_delays_in_input_queue: 2
|
||||
memory_refreshes: 246
|
||||
memory_total_request_delays: 39
|
||||
memory_delays_per_request: 0.0747126
|
||||
memory_delays_in_input_queue: 0
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 149
|
||||
memory_stalls_for_bank_busy: 22
|
||||
memory_delays_stalled_at_head_of_bank_queue: 39
|
||||
memory_stalls_for_bank_busy: 15
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 7
|
||||
memory_stalls_for_bus: 26
|
||||
memory_stalls_for_arbitration: 5
|
||||
memory_stalls_for_bus: 15
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 94
|
||||
memory_stalls_for_read_write_turnaround: 4
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [53 ] 53
|
||||
GETX [51 ] 51
|
||||
GETS [410 ] 410
|
||||
PUT [425 ] 425
|
||||
Unblock [0 ] 0
|
||||
|
|
@ -909,7 +909,7 @@ WB_O_W DMA_WRITE [0 ] 0
|
|||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [2 ] 2
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [2 ] 2
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:27:37
|
||||
gem5 started Jul 28 2012 11:35:39
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 13:53:26
|
||||
gem5 started Sep 1 2012 13:54:34
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 78448 because target called exit()
|
||||
Exiting @ tick 35432 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000078 # Number of seconds simulated
|
||||
sim_ticks 78448 # Number of ticks simulated
|
||||
final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000035 # Number of seconds simulated
|
||||
sim_ticks 35432 # Number of ticks simulated
|
||||
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31170 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31163 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 948464 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230616 # Number of bytes of host memory used
|
||||
host_inst_rate 32925 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 452422 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262480 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 415 # Nu
|
|||
system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 294 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 291826597 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 85120795 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 376947392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 291826597 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 291826597 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 58083089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 58083089 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 291826597 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 143203883 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 435030481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -90,7 +90,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 78448 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 35432 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -109,7 +109,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 78448 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 35432 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -10,11 +10,12 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.funcmem system.physmem
|
||||
memories=system.physmem system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -30,6 +31,7 @@ system_port=system.sys_port_proxy.slave[0]
|
|||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -48,6 +50,7 @@ test=system.l1_cntrl0.sequencer.slave[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -66,6 +69,7 @@ test=system.l1_cntrl1.sequencer.slave[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -84,6 +88,7 @@ test=system.l1_cntrl2.sequencer.slave[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -102,6 +107,7 @@ test=system.l1_cntrl3.sequencer.slave[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -120,6 +126,7 @@ test=system.l1_cntrl4.sequencer.slave[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -138,6 +145,7 @@ test=system.l1_cntrl5.sequencer.slave[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -156,6 +164,7 @@ test=system.l1_cntrl6.sequencer.slave[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -201,9 +210,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -212,6 +221,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -227,6 +237,7 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
|
|||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
|
|
@ -287,6 +298,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -350,6 +362,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
|
|
@ -413,6 +426,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
|
|
@ -476,6 +490,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
|
|
@ -539,6 +554,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
|
|
@ -602,6 +618,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
|
|
@ -665,6 +682,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
|
|
@ -728,6 +746,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
|
|
@ -772,6 +791,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -1057,6 +1077,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu7: completed 10000 read, 5315 write accesses @2178175
|
||||
system.cpu3: completed 10000 read, 5321 write accesses @2258665
|
||||
system.cpu4: completed 10000 read, 5425 write accesses @2267755
|
||||
system.cpu6: completed 10000 read, 5427 write accesses @2268141
|
||||
system.cpu0: completed 10000 read, 5406 write accesses @2273125
|
||||
system.cpu1: completed 10000 read, 5452 write accesses @2273264
|
||||
system.cpu5: completed 10000 read, 5563 write accesses @2285825
|
||||
system.cpu2: completed 10000 read, 5393 write accesses @2319830
|
||||
system.cpu6: completed 20000 read, 10754 write accesses @4478934
|
||||
system.cpu7: completed 20000 read, 10722 write accesses @4479230
|
||||
system.cpu3: completed 20000 read, 10700 write accesses @4490364
|
||||
system.cpu1: completed 20000 read, 10770 write accesses @4490415
|
||||
system.cpu2: completed 20000 read, 10639 write accesses @4498895
|
||||
system.cpu5: completed 20000 read, 10822 write accesses @4521505
|
||||
system.cpu4: completed 20000 read, 10759 write accesses @4557615
|
||||
system.cpu0: completed 20000 read, 10835 write accesses @4559745
|
||||
system.cpu2: completed 30000 read, 15995 write accesses @6715895
|
||||
system.cpu6: completed 30000 read, 16176 write accesses @6737577
|
||||
system.cpu7: completed 30000 read, 16133 write accesses @6741445
|
||||
system.cpu5: completed 30000 read, 16232 write accesses @6761017
|
||||
system.cpu1: completed 30000 read, 16230 write accesses @6767058
|
||||
system.cpu3: completed 30000 read, 16227 write accesses @6779365
|
||||
system.cpu4: completed 30000 read, 16123 write accesses @6794365
|
||||
system.cpu0: completed 30000 read, 16180 write accesses @6842625
|
||||
system.cpu5: completed 40000 read, 21501 write accesses @9004145
|
||||
system.cpu3: completed 40000 read, 21499 write accesses @9006504
|
||||
system.cpu6: completed 40000 read, 21666 write accesses @9018985
|
||||
system.cpu4: completed 40000 read, 21471 write accesses @9035325
|
||||
system.cpu7: completed 40000 read, 21682 write accesses @9038295
|
||||
system.cpu2: completed 40000 read, 21469 write accesses @9046715
|
||||
system.cpu1: completed 40000 read, 21651 write accesses @9051455
|
||||
system.cpu0: completed 40000 read, 21538 write accesses @9086675
|
||||
system.cpu6: completed 50000 read, 27114 write accesses @11277374
|
||||
system.cpu3: completed 50000 read, 26914 write accesses @11278005
|
||||
system.cpu7: completed 50000 read, 27059 write accesses @11289715
|
||||
system.cpu5: completed 50000 read, 26974 write accesses @11300494
|
||||
system.cpu2: completed 50000 read, 27018 write accesses @11307085
|
||||
system.cpu1: completed 50000 read, 26955 write accesses @11338755
|
||||
system.cpu0: completed 50000 read, 26964 write accesses @11375085
|
||||
system.cpu4: completed 50000 read, 26957 write accesses @11429764
|
||||
system.cpu6: completed 60000 read, 32482 write accesses @13471525
|
||||
system.cpu3: completed 60000 read, 32172 write accesses @13503805
|
||||
system.cpu5: completed 60000 read, 32381 write accesses @13517804
|
||||
system.cpu7: completed 60000 read, 32276 write accesses @13525105
|
||||
system.cpu2: completed 60000 read, 32332 write accesses @13536245
|
||||
system.cpu1: completed 60000 read, 32320 write accesses @13562114
|
||||
system.cpu0: completed 60000 read, 32359 write accesses @13656465
|
||||
system.cpu4: completed 60000 read, 32583 write accesses @13754744
|
||||
system.cpu5: completed 70000 read, 37779 write accesses @15741524
|
||||
system.cpu3: completed 70000 read, 37626 write accesses @15742775
|
||||
system.cpu6: completed 70000 read, 37950 write accesses @15755405
|
||||
system.cpu7: completed 70000 read, 37483 write accesses @15767164
|
||||
system.cpu1: completed 70000 read, 37652 write accesses @15806815
|
||||
system.cpu2: completed 70000 read, 37653 write accesses @15812414
|
||||
system.cpu0: completed 70000 read, 37652 write accesses @15945564
|
||||
system.cpu4: completed 70000 read, 37919 write accesses @15985575
|
||||
system.cpu7: completed 80000 read, 42762 write accesses @17959865
|
||||
system.cpu5: completed 80000 read, 43041 write accesses @17974164
|
||||
system.cpu3: completed 80000 read, 42943 write accesses @17982045
|
||||
system.cpu6: completed 80000 read, 43147 write accesses @17984384
|
||||
system.cpu1: completed 80000 read, 42940 write accesses @18041354
|
||||
system.cpu2: completed 80000 read, 43118 write accesses @18148206
|
||||
system.cpu0: completed 80000 read, 42966 write accesses @18152744
|
||||
system.cpu4: completed 80000 read, 43236 write accesses @18256215
|
||||
system.cpu5: completed 90000 read, 48432 write accesses @20226495
|
||||
system.cpu6: completed 90000 read, 48567 write accesses @20256365
|
||||
system.cpu7: completed 90000 read, 48171 write accesses @20262095
|
||||
system.cpu3: completed 90000 read, 48375 write accesses @20266104
|
||||
system.cpu1: completed 90000 read, 48524 write accesses @20337685
|
||||
system.cpu0: completed 90000 read, 48274 write accesses @20381074
|
||||
system.cpu2: completed 90000 read, 48595 write accesses @20447365
|
||||
system.cpu4: completed 90000 read, 48684 write accesses @20509404
|
||||
system.cpu3: completed 100000 read, 53763 write accesses @22495354
|
||||
system.cpu6: completed 10000 read, 5365 write accesses @719672
|
||||
system.cpu4: completed 10000 read, 5437 write accesses @721238
|
||||
system.cpu2: completed 10000 read, 5421 write accesses @727405
|
||||
system.cpu5: completed 10000 read, 5337 write accesses @728640
|
||||
system.cpu1: completed 10000 read, 5306 write accesses @739695
|
||||
system.cpu0: completed 10000 read, 5242 write accesses @743577
|
||||
system.cpu3: completed 10000 read, 5450 write accesses @745629
|
||||
system.cpu7: completed 10000 read, 5714 write accesses @748519
|
||||
system.cpu6: completed 20000 read, 10620 write accesses @1427013
|
||||
system.cpu2: completed 20000 read, 10776 write accesses @1449780
|
||||
system.cpu4: completed 20000 read, 10676 write accesses @1454294
|
||||
system.cpu5: completed 20000 read, 10664 write accesses @1455327
|
||||
system.cpu1: completed 20000 read, 10677 write accesses @1463325
|
||||
system.cpu0: completed 20000 read, 10572 write accesses @1473996
|
||||
system.cpu7: completed 20000 read, 11108 write accesses @1487052
|
||||
system.cpu3: completed 20000 read, 10777 write accesses @1490754
|
||||
system.cpu5: completed 30000 read, 16039 write accesses @2158969
|
||||
system.cpu6: completed 30000 read, 16167 write accesses @2175252
|
||||
system.cpu2: completed 30000 read, 16167 write accesses @2180312
|
||||
system.cpu4: completed 30000 read, 16215 write accesses @2190381
|
||||
system.cpu0: completed 30000 read, 15974 write accesses @2206091
|
||||
system.cpu1: completed 30000 read, 16196 write accesses @2209395
|
||||
system.cpu7: completed 30000 read, 16345 write accesses @2219972
|
||||
system.cpu3: completed 30000 read, 16078 write accesses @2220143
|
||||
system.cpu5: completed 40000 read, 21392 write accesses @2899061
|
||||
system.cpu2: completed 40000 read, 21496 write accesses @2899829
|
||||
system.cpu6: completed 40000 read, 21553 write accesses @2911614
|
||||
system.cpu4: completed 40000 read, 21511 write accesses @2932562
|
||||
system.cpu1: completed 40000 read, 21671 write accesses @2938496
|
||||
system.cpu0: completed 40000 read, 21461 write accesses @2955945
|
||||
system.cpu3: completed 40000 read, 21481 write accesses @2956326
|
||||
system.cpu7: completed 40000 read, 21787 write accesses @2958263
|
||||
system.cpu2: completed 50000 read, 26881 write accesses @3632427
|
||||
system.cpu5: completed 50000 read, 26798 write accesses @3647589
|
||||
system.cpu6: completed 50000 read, 27058 write accesses @3655170
|
||||
system.cpu4: completed 50000 read, 26812 write accesses @3655319
|
||||
system.cpu1: completed 50000 read, 27071 write accesses @3688858
|
||||
system.cpu3: completed 50000 read, 26791 write accesses @3690833
|
||||
system.cpu0: completed 50000 read, 27081 write accesses @3690860
|
||||
system.cpu7: completed 50000 read, 27296 write accesses @3707477
|
||||
system.cpu2: completed 60000 read, 32129 write accesses @4356825
|
||||
system.cpu5: completed 60000 read, 32023 write accesses @4371741
|
||||
system.cpu6: completed 60000 read, 32443 write accesses @4376668
|
||||
system.cpu4: completed 60000 read, 32295 write accesses @4386108
|
||||
system.cpu3: completed 60000 read, 32175 write accesses @4408668
|
||||
system.cpu0: completed 60000 read, 32420 write accesses @4415861
|
||||
system.cpu1: completed 60000 read, 32486 write accesses @4431347
|
||||
system.cpu7: completed 60000 read, 32741 write accesses @4445010
|
||||
system.cpu2: completed 70000 read, 37617 write accesses @5091246
|
||||
system.cpu5: completed 70000 read, 37377 write accesses @5103537
|
||||
system.cpu4: completed 70000 read, 37661 write accesses @5110093
|
||||
system.cpu6: completed 70000 read, 37706 write accesses @5114409
|
||||
system.cpu3: completed 70000 read, 37523 write accesses @5122627
|
||||
system.cpu0: completed 70000 read, 37790 write accesses @5150115
|
||||
system.cpu7: completed 70000 read, 38053 write accesses @5173503
|
||||
system.cpu1: completed 70000 read, 37871 write accesses @5177041
|
||||
system.cpu2: completed 80000 read, 42964 write accesses @5827270
|
||||
system.cpu5: completed 80000 read, 42671 write accesses @5843646
|
||||
system.cpu4: completed 80000 read, 42873 write accesses @5844336
|
||||
system.cpu3: completed 80000 read, 42910 write accesses @5844576
|
||||
system.cpu6: completed 80000 read, 43090 write accesses @5845119
|
||||
system.cpu0: completed 80000 read, 43048 write accesses @5875184
|
||||
system.cpu1: completed 80000 read, 43196 write accesses @5885103
|
||||
system.cpu7: completed 80000 read, 43360 write accesses @5912912
|
||||
system.cpu2: completed 90000 read, 48230 write accesses @6556181
|
||||
system.cpu6: completed 90000 read, 48543 write accesses @6557564
|
||||
system.cpu4: completed 90000 read, 48345 write accesses @6563045
|
||||
system.cpu3: completed 90000 read, 48233 write accesses @6584230
|
||||
system.cpu5: completed 90000 read, 48065 write accesses @6589320
|
||||
system.cpu0: completed 90000 read, 48648 write accesses @6625439
|
||||
system.cpu1: completed 90000 read, 48656 write accesses @6633753
|
||||
system.cpu7: completed 90000 read, 48776 write accesses @6656500
|
||||
system.cpu2: completed 100000 read, 53615 write accesses @7277301
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:30:15
|
||||
gem5 started Jul 28 2012 11:35:39
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:01:54
|
||||
gem5 started Sep 1 2012 14:03:16
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 22495354 because maximum number of loads reached
|
||||
Exiting @ tick 7277301 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.022495 # Number of seconds simulated
|
||||
sim_ticks 22495354 # Number of ticks simulated
|
||||
final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007277 # Number of seconds simulated
|
||||
sim_ticks 7277301 # Number of ticks simulated
|
||||
final_tick 7277301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 269371 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378776 # Number of bytes of host memory used
|
||||
host_seconds 83.51 # Real time elapsed on the host
|
||||
host_tick_rate 75137 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410244 # Number of bytes of host memory used
|
||||
host_seconds 96.85 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99326 # number of read accesses completed
|
||||
system.cpu0.num_writes 53132 # number of write accesses completed
|
||||
system.cpu0.num_reads 98746 # number of read accesses completed
|
||||
system.cpu0.num_writes 53285 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99634 # number of read accesses completed
|
||||
system.cpu1.num_writes 53798 # number of write accesses completed
|
||||
system.cpu1.num_reads 98932 # number of read accesses completed
|
||||
system.cpu1.num_writes 53387 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99031 # number of read accesses completed
|
||||
system.cpu2.num_writes 53441 # number of write accesses completed
|
||||
system.cpu2.num_reads 100001 # number of read accesses completed
|
||||
system.cpu2.num_writes 53615 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53763 # number of write accesses completed
|
||||
system.cpu3.num_reads 99438 # number of read accesses completed
|
||||
system.cpu3.num_writes 53391 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98726 # number of read accesses completed
|
||||
system.cpu4.num_writes 53438 # number of write accesses completed
|
||||
system.cpu4.num_reads 99851 # number of read accesses completed
|
||||
system.cpu4.num_writes 53668 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99955 # number of read accesses completed
|
||||
system.cpu5.num_writes 53794 # number of write accesses completed
|
||||
system.cpu5.num_reads 99263 # number of read accesses completed
|
||||
system.cpu5.num_writes 53077 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99893 # number of read accesses completed
|
||||
system.cpu6.num_writes 53796 # number of write accesses completed
|
||||
system.cpu6.num_reads 99775 # number of read accesses completed
|
||||
system.cpu6.num_writes 53756 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99993 # number of read accesses completed
|
||||
system.cpu7.num_writes 53567 # number of write accesses completed
|
||||
system.cpu7.num_reads 98608 # number of read accesses completed
|
||||
system.cpu7.num_writes 53419 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,6 +31,7 @@ system_port=system.sys_port_proxy.slave[0]
|
|||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -48,6 +50,7 @@ test=system.l1_cntrl0.sequencer.slave[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -66,6 +69,7 @@ test=system.l1_cntrl1.sequencer.slave[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -84,6 +88,7 @@ test=system.l1_cntrl2.sequencer.slave[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -102,6 +107,7 @@ test=system.l1_cntrl3.sequencer.slave[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -120,6 +126,7 @@ test=system.l1_cntrl4.sequencer.slave[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -138,6 +145,7 @@ test=system.l1_cntrl5.sequencer.slave[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -156,6 +164,7 @@ test=system.l1_cntrl6.sequencer.slave[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -200,9 +209,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -211,6 +220,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -226,6 +236,7 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
|
|||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
|
|
@ -284,6 +295,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -345,6 +357,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
|
|
@ -406,6 +419,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
|
|
@ -467,6 +481,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
|
|
@ -528,6 +543,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
|
|
@ -589,6 +605,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
|
|
@ -650,6 +667,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
|
|
@ -711,6 +729,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
|
|
@ -754,6 +773,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -1039,6 +1059,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu1: completed 10000 read, 5302 write accesses @1928146
|
||||
system.cpu4: completed 10000 read, 5365 write accesses @1942166
|
||||
system.cpu7: completed 10000 read, 5319 write accesses @1965207
|
||||
system.cpu3: completed 10000 read, 5359 write accesses @1968836
|
||||
system.cpu0: completed 10000 read, 5498 write accesses @1974677
|
||||
system.cpu2: completed 10000 read, 5513 write accesses @1977476
|
||||
system.cpu6: completed 10000 read, 5448 write accesses @1980956
|
||||
system.cpu5: completed 10000 read, 5483 write accesses @1995684
|
||||
system.cpu4: completed 20000 read, 10717 write accesses @3830467
|
||||
system.cpu1: completed 20000 read, 10577 write accesses @3871337
|
||||
system.cpu7: completed 20000 read, 10556 write accesses @3902287
|
||||
system.cpu5: completed 20000 read, 10901 write accesses @3923395
|
||||
system.cpu0: completed 20000 read, 10861 write accesses @3926315
|
||||
system.cpu2: completed 20000 read, 10674 write accesses @3934695
|
||||
system.cpu6: completed 20000 read, 10925 write accesses @3939046
|
||||
system.cpu3: completed 20000 read, 10752 write accesses @3981115
|
||||
system.cpu4: completed 30000 read, 16128 write accesses @5754566
|
||||
system.cpu7: completed 30000 read, 16027 write accesses @5841539
|
||||
system.cpu5: completed 30000 read, 16312 write accesses @5857206
|
||||
system.cpu2: completed 30000 read, 16104 write accesses @5869696
|
||||
system.cpu1: completed 30000 read, 16084 write accesses @5872577
|
||||
system.cpu0: completed 30000 read, 16133 write accesses @5895696
|
||||
system.cpu6: completed 30000 read, 16259 write accesses @5909016
|
||||
system.cpu3: completed 30000 read, 16253 write accesses @5970997
|
||||
system.cpu4: completed 40000 read, 21443 write accesses @7732298
|
||||
system.cpu7: completed 40000 read, 21518 write accesses @7817106
|
||||
system.cpu0: completed 40000 read, 21561 write accesses @7817675
|
||||
system.cpu2: completed 40000 read, 21432 write accesses @7822846
|
||||
system.cpu1: completed 40000 read, 21383 write accesses @7845525
|
||||
system.cpu5: completed 40000 read, 21816 write accesses @7858096
|
||||
system.cpu6: completed 40000 read, 21672 write accesses @7885486
|
||||
system.cpu3: completed 40000 read, 21581 write accesses @7941597
|
||||
system.cpu4: completed 50000 read, 26787 write accesses @9651285
|
||||
system.cpu7: completed 50000 read, 26989 write accesses @9793686
|
||||
system.cpu0: completed 50000 read, 26994 write accesses @9797807
|
||||
system.cpu2: completed 50000 read, 26921 write accesses @9830875
|
||||
system.cpu5: completed 50000 read, 27153 write accesses @9839316
|
||||
system.cpu6: completed 50000 read, 27189 write accesses @9858608
|
||||
system.cpu1: completed 50000 read, 26834 write accesses @9863587
|
||||
system.cpu3: completed 50000 read, 27039 write accesses @9921406
|
||||
system.cpu4: completed 60000 read, 32175 write accesses @11605575
|
||||
system.cpu2: completed 60000 read, 32358 write accesses @11729986
|
||||
system.cpu0: completed 60000 read, 32424 write accesses @11735436
|
||||
system.cpu7: completed 60000 read, 32432 write accesses @11778007
|
||||
system.cpu6: completed 60000 read, 32473 write accesses @11788255
|
||||
system.cpu5: completed 60000 read, 32623 write accesses @11789575
|
||||
system.cpu1: completed 60000 read, 32116 write accesses @11821356
|
||||
system.cpu3: completed 60000 read, 32229 write accesses @11884826
|
||||
system.cpu4: completed 70000 read, 37533 write accesses @13546365
|
||||
system.cpu0: completed 70000 read, 37907 write accesses @13701646
|
||||
system.cpu2: completed 70000 read, 37745 write accesses @13708257
|
||||
system.cpu6: completed 70000 read, 37768 write accesses @13710576
|
||||
system.cpu7: completed 70000 read, 37843 write accesses @13719776
|
||||
system.cpu5: completed 70000 read, 37934 write accesses @13770505
|
||||
system.cpu1: completed 70000 read, 37322 write accesses @13773596
|
||||
system.cpu3: completed 70000 read, 37575 write accesses @13859246
|
||||
system.cpu4: completed 80000 read, 42663 write accesses @15468226
|
||||
system.cpu6: completed 80000 read, 43059 write accesses @15617186
|
||||
system.cpu7: completed 80000 read, 43185 write accesses @15635279
|
||||
system.cpu0: completed 80000 read, 43129 write accesses @15668486
|
||||
system.cpu2: completed 80000 read, 43262 write accesses @15680656
|
||||
system.cpu1: completed 80000 read, 42658 write accesses @15703946
|
||||
system.cpu5: completed 80000 read, 43215 write accesses @15712586
|
||||
system.cpu3: completed 80000 read, 42991 write accesses @15858096
|
||||
system.cpu4: completed 90000 read, 48047 write accesses @17468576
|
||||
system.cpu2: completed 90000 read, 48557 write accesses @17581105
|
||||
system.cpu7: completed 90000 read, 48648 write accesses @17584296
|
||||
system.cpu6: completed 90000 read, 48515 write accesses @17584397
|
||||
system.cpu1: completed 90000 read, 48024 write accesses @17672186
|
||||
system.cpu0: completed 90000 read, 48750 write accesses @17683641
|
||||
system.cpu5: completed 90000 read, 48534 write accesses @17695277
|
||||
system.cpu3: completed 90000 read, 48496 write accesses @17843215
|
||||
system.cpu4: completed 100000 read, 53558 write accesses @19400856
|
||||
system.cpu4: completed 10000 read, 5361 write accesses @736700
|
||||
system.cpu2: completed 10000 read, 5258 write accesses @741379
|
||||
system.cpu3: completed 10000 read, 5403 write accesses @747863
|
||||
system.cpu1: completed 10000 read, 5292 write accesses @751357
|
||||
system.cpu6: completed 10000 read, 5451 write accesses @754502
|
||||
system.cpu7: completed 10000 read, 5438 write accesses @755068
|
||||
system.cpu5: completed 10000 read, 5557 write accesses @759525
|
||||
system.cpu0: completed 10000 read, 5442 write accesses @772965
|
||||
system.cpu4: completed 20000 read, 10700 write accesses @1474707
|
||||
system.cpu7: completed 20000 read, 10673 write accesses @1490391
|
||||
system.cpu2: completed 20000 read, 10490 write accesses @1492637
|
||||
system.cpu3: completed 20000 read, 10828 write accesses @1496240
|
||||
system.cpu1: completed 20000 read, 10531 write accesses @1496747
|
||||
system.cpu6: completed 20000 read, 10827 write accesses @1502187
|
||||
system.cpu5: completed 20000 read, 10968 write accesses @1509184
|
||||
system.cpu0: completed 20000 read, 10821 write accesses @1515170
|
||||
system.cpu4: completed 30000 read, 16140 write accesses @2234178
|
||||
system.cpu2: completed 30000 read, 15837 write accesses @2240133
|
||||
system.cpu1: completed 30000 read, 15925 write accesses @2244203
|
||||
system.cpu6: completed 30000 read, 16178 write accesses @2245026
|
||||
system.cpu0: completed 30000 read, 16116 write accesses @2252500
|
||||
system.cpu7: completed 30000 read, 16150 write accesses @2252680
|
||||
system.cpu5: completed 30000 read, 16546 write accesses @2254097
|
||||
system.cpu3: completed 30000 read, 16154 write accesses @2258292
|
||||
system.cpu2: completed 40000 read, 21131 write accesses @2982888
|
||||
system.cpu4: completed 40000 read, 21564 write accesses @2988433
|
||||
system.cpu6: completed 40000 read, 21517 write accesses @2995571
|
||||
system.cpu7: completed 40000 read, 21451 write accesses @3002984
|
||||
system.cpu0: completed 40000 read, 21558 write accesses @3005254
|
||||
system.cpu1: completed 40000 read, 21476 write accesses @3010475
|
||||
system.cpu3: completed 40000 read, 21590 write accesses @3015598
|
||||
system.cpu5: completed 40000 read, 21951 write accesses @3024338
|
||||
system.cpu2: completed 50000 read, 26563 write accesses @3740176
|
||||
system.cpu4: completed 50000 read, 27047 write accesses @3743329
|
||||
system.cpu7: completed 50000 read, 26749 write accesses @3757917
|
||||
system.cpu6: completed 50000 read, 26964 write accesses @3758280
|
||||
system.cpu0: completed 50000 read, 27012 write accesses @3762857
|
||||
system.cpu5: completed 50000 read, 27348 write accesses @3768681
|
||||
system.cpu1: completed 50000 read, 26902 write accesses @3773494
|
||||
system.cpu3: completed 50000 read, 27102 write accesses @3774586
|
||||
system.cpu2: completed 60000 read, 32068 write accesses @4487250
|
||||
system.cpu4: completed 60000 read, 32524 write accesses @4492613
|
||||
system.cpu7: completed 60000 read, 32123 write accesses @4501802
|
||||
system.cpu5: completed 60000 read, 32618 write accesses @4505087
|
||||
system.cpu6: completed 60000 read, 32304 write accesses @4507148
|
||||
system.cpu1: completed 60000 read, 32342 write accesses @4512477
|
||||
system.cpu0: completed 60000 read, 32196 write accesses @4513791
|
||||
system.cpu3: completed 60000 read, 32477 write accesses @4527938
|
||||
system.cpu4: completed 70000 read, 38050 write accesses @5246087
|
||||
system.cpu2: completed 70000 read, 37438 write accesses @5246857
|
||||
system.cpu6: completed 70000 read, 37522 write accesses @5247624
|
||||
system.cpu1: completed 70000 read, 37552 write accesses @5255630
|
||||
system.cpu7: completed 70000 read, 37454 write accesses @5256746
|
||||
system.cpu5: completed 70000 read, 37853 write accesses @5262449
|
||||
system.cpu3: completed 70000 read, 37751 write accesses @5263226
|
||||
system.cpu0: completed 70000 read, 37564 write accesses @5268794
|
||||
system.cpu6: completed 80000 read, 42984 write accesses @5994771
|
||||
system.cpu4: completed 80000 read, 43493 write accesses @5995916
|
||||
system.cpu5: completed 80000 read, 42965 write accesses @6000829
|
||||
system.cpu2: completed 80000 read, 42825 write accesses @6004649
|
||||
system.cpu0: completed 80000 read, 42741 write accesses @6006103
|
||||
system.cpu1: completed 80000 read, 42738 write accesses @6009758
|
||||
system.cpu7: completed 80000 read, 42872 write accesses @6009923
|
||||
system.cpu3: completed 80000 read, 43090 write accesses @6011644
|
||||
system.cpu6: completed 90000 read, 48315 write accesses @6743220
|
||||
system.cpu4: completed 90000 read, 48816 write accesses @6743546
|
||||
system.cpu1: completed 90000 read, 48145 write accesses @6749147
|
||||
system.cpu2: completed 90000 read, 48237 write accesses @6753252
|
||||
system.cpu5: completed 90000 read, 48465 write accesses @6756537
|
||||
system.cpu3: completed 90000 read, 48531 write accesses @6772036
|
||||
system.cpu0: completed 90000 read, 48152 write accesses @6774043
|
||||
system.cpu7: completed 90000 read, 48393 write accesses @6775135
|
||||
system.cpu4: completed 100000 read, 54127 write accesses @7493512
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:32:56
|
||||
gem5 started Jul 28 2012 11:35:54
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:10:16
|
||||
gem5 started Sep 1 2012 14:11:41
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19400856 because maximum number of loads reached
|
||||
Exiting @ tick 7493512 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019401 # Number of seconds simulated
|
||||
sim_ticks 19400856 # Number of ticks simulated
|
||||
final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007494 # Number of seconds simulated
|
||||
sim_ticks 7493512 # Number of ticks simulated
|
||||
final_tick 7493512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 84896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378952 # Number of bytes of host memory used
|
||||
host_seconds 228.52 # Real time elapsed on the host
|
||||
host_tick_rate 42711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410448 # Number of bytes of host memory used
|
||||
host_seconds 175.45 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 98844 # number of read accesses completed
|
||||
system.cpu0.num_writes 53478 # number of write accesses completed
|
||||
system.cpu0.num_reads 99629 # number of read accesses completed
|
||||
system.cpu0.num_writes 53203 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98643 # number of read accesses completed
|
||||
system.cpu1.num_writes 52679 # number of write accesses completed
|
||||
system.cpu1.num_reads 99934 # number of read accesses completed
|
||||
system.cpu1.num_writes 53556 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99369 # number of read accesses completed
|
||||
system.cpu2.num_writes 53574 # number of write accesses completed
|
||||
system.cpu2.num_reads 99904 # number of read accesses completed
|
||||
system.cpu2.num_writes 53683 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97889 # number of read accesses completed
|
||||
system.cpu3.num_writes 52711 # number of write accesses completed
|
||||
system.cpu3.num_reads 99658 # number of read accesses completed
|
||||
system.cpu3.num_writes 53732 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53558 # number of write accesses completed
|
||||
system.cpu4.num_writes 54127 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98762 # number of read accesses completed
|
||||
system.cpu5.num_writes 53328 # number of write accesses completed
|
||||
system.cpu5.num_reads 99924 # number of read accesses completed
|
||||
system.cpu5.num_writes 53749 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99308 # number of read accesses completed
|
||||
system.cpu6.num_writes 53445 # number of write accesses completed
|
||||
system.cpu6.num_reads 99831 # number of read accesses completed
|
||||
system.cpu6.num_writes 53726 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99141 # number of read accesses completed
|
||||
system.cpu7.num_writes 53490 # number of write accesses completed
|
||||
system.cpu7.num_reads 99585 # number of read accesses completed
|
||||
system.cpu7.num_writes 53460 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,6 +31,7 @@ system_port=system.sys_port_proxy.slave[0]
|
|||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -48,6 +50,7 @@ test=system.l1_cntrl0.sequencer.slave[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -66,6 +69,7 @@ test=system.l1_cntrl1.sequencer.slave[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -84,6 +88,7 @@ test=system.l1_cntrl2.sequencer.slave[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -102,6 +107,7 @@ test=system.l1_cntrl3.sequencer.slave[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -120,6 +126,7 @@ test=system.l1_cntrl4.sequencer.slave[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -138,6 +145,7 @@ test=system.l1_cntrl5.sequencer.slave[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -156,6 +164,7 @@ test=system.l1_cntrl6.sequencer.slave[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -203,9 +212,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -214,6 +223,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -243,6 +253,7 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
|
|||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
|
|
@ -318,6 +329,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -396,6 +408,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
|
|
@ -474,6 +487,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
|
|
@ -552,6 +566,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
|
|
@ -630,6 +645,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
|
|
@ -708,6 +724,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
|
|
@ -786,6 +803,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
|
|
@ -864,6 +882,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
|
|
@ -879,6 +898,7 @@ slave=system.cpu7.test
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -1141,6 +1161,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu4: completed 10000 read, 5412 write accesses @1871699
|
||||
system.cpu2: completed 10000 read, 5460 write accesses @1893369
|
||||
system.cpu1: completed 10000 read, 5378 write accesses @1906861
|
||||
system.cpu6: completed 10000 read, 5396 write accesses @1925998
|
||||
system.cpu0: completed 10000 read, 5377 write accesses @1932348
|
||||
system.cpu5: completed 10000 read, 5525 write accesses @1940098
|
||||
system.cpu3: completed 10000 read, 5395 write accesses @1950309
|
||||
system.cpu7: completed 10000 read, 5394 write accesses @1966559
|
||||
system.cpu1: completed 20000 read, 10544 write accesses @3781959
|
||||
system.cpu4: completed 20000 read, 10680 write accesses @3792439
|
||||
system.cpu2: completed 20000 read, 10687 write accesses @3801439
|
||||
system.cpu3: completed 20000 read, 10623 write accesses @3813939
|
||||
system.cpu0: completed 20000 read, 10834 write accesses @3843808
|
||||
system.cpu5: completed 20000 read, 10928 write accesses @3845319
|
||||
system.cpu6: completed 20000 read, 10782 write accesses @3845558
|
||||
system.cpu7: completed 20000 read, 10939 write accesses @3904539
|
||||
system.cpu2: completed 30000 read, 15884 write accesses @5673111
|
||||
system.cpu4: completed 30000 read, 16055 write accesses @5692488
|
||||
system.cpu1: completed 30000 read, 16005 write accesses @5703958
|
||||
system.cpu3: completed 30000 read, 16124 write accesses @5726919
|
||||
system.cpu5: completed 30000 read, 16307 write accesses @5771630
|
||||
system.cpu6: completed 30000 read, 16295 write accesses @5776079
|
||||
system.cpu0: completed 30000 read, 16283 write accesses @5776769
|
||||
system.cpu7: completed 30000 read, 16366 write accesses @5874559
|
||||
system.cpu3: completed 40000 read, 21574 write accesses @7627939
|
||||
system.cpu2: completed 40000 read, 21245 write accesses @7628738
|
||||
system.cpu1: completed 40000 read, 21306 write accesses @7628758
|
||||
system.cpu4: completed 40000 read, 21462 write accesses @7660680
|
||||
system.cpu0: completed 40000 read, 21631 write accesses @7675309
|
||||
system.cpu5: completed 40000 read, 21626 write accesses @7680509
|
||||
system.cpu6: completed 40000 read, 21716 write accesses @7696178
|
||||
system.cpu7: completed 40000 read, 21960 write accesses @7863749
|
||||
system.cpu0: completed 50000 read, 26830 write accesses @9562969
|
||||
system.cpu2: completed 50000 read, 26690 write accesses @9565708
|
||||
system.cpu3: completed 50000 read, 26994 write accesses @9575479
|
||||
system.cpu4: completed 50000 read, 26869 write accesses @9589449
|
||||
system.cpu1: completed 50000 read, 26670 write accesses @9611561
|
||||
system.cpu5: completed 50000 read, 27137 write accesses @9617389
|
||||
system.cpu6: completed 50000 read, 27275 write accesses @9658029
|
||||
system.cpu7: completed 50000 read, 27527 write accesses @9814359
|
||||
system.cpu0: completed 60000 read, 32249 write accesses @11423019
|
||||
system.cpu3: completed 60000 read, 32267 write accesses @11433399
|
||||
system.cpu2: completed 60000 read, 32022 write accesses @11474303
|
||||
system.cpu5: completed 60000 read, 32388 write accesses @11521948
|
||||
system.cpu4: completed 60000 read, 32356 write accesses @11528079
|
||||
system.cpu1: completed 60000 read, 32067 write accesses @11544409
|
||||
system.cpu6: completed 60000 read, 32659 write accesses @11548639
|
||||
system.cpu7: completed 60000 read, 32942 write accesses @11779569
|
||||
system.cpu3: completed 70000 read, 37638 write accesses @13336858
|
||||
system.cpu2: completed 70000 read, 37313 write accesses @13368779
|
||||
system.cpu0: completed 70000 read, 37676 write accesses @13377210
|
||||
system.cpu4: completed 70000 read, 37656 write accesses @13416889
|
||||
system.cpu6: completed 70000 read, 38021 write accesses @13465679
|
||||
system.cpu5: completed 70000 read, 37732 write accesses @13467391
|
||||
system.cpu1: completed 70000 read, 37360 write accesses @13477099
|
||||
system.cpu7: completed 70000 read, 38399 write accesses @13717039
|
||||
system.cpu3: completed 80000 read, 42978 write accesses @15269199
|
||||
system.cpu0: completed 80000 read, 42958 write accesses @15278319
|
||||
system.cpu2: completed 80000 read, 42507 write accesses @15310609
|
||||
system.cpu4: completed 80000 read, 42937 write accesses @15325761
|
||||
system.cpu6: completed 80000 read, 43416 write accesses @15354801
|
||||
system.cpu5: completed 80000 read, 43057 write accesses @15376839
|
||||
system.cpu1: completed 80000 read, 42520 write accesses @15380279
|
||||
system.cpu7: completed 80000 read, 43907 write accesses @15634198
|
||||
system.cpu3: completed 90000 read, 48403 write accesses @17192399
|
||||
system.cpu0: completed 90000 read, 48519 write accesses @17230959
|
||||
system.cpu1: completed 90000 read, 47845 write accesses @17249039
|
||||
system.cpu2: completed 90000 read, 47947 write accesses @17255499
|
||||
system.cpu6: completed 90000 read, 48741 write accesses @17263669
|
||||
system.cpu4: completed 90000 read, 48366 write accesses @17269639
|
||||
system.cpu5: completed 90000 read, 48485 write accesses @17297549
|
||||
system.cpu7: completed 90000 read, 49327 write accesses @17576399
|
||||
system.cpu0: completed 100000 read, 53893 write accesses @19129199
|
||||
system.cpu0: completed 10000 read, 5308 write accesses @570767
|
||||
system.cpu5: completed 10000 read, 5470 write accesses @573498
|
||||
system.cpu1: completed 10000 read, 5429 write accesses @573920
|
||||
system.cpu7: completed 10000 read, 5290 write accesses @575321
|
||||
system.cpu4: completed 10000 read, 5445 write accesses @585929
|
||||
system.cpu3: completed 10000 read, 5486 write accesses @586872
|
||||
system.cpu6: completed 10000 read, 5559 write accesses @588791
|
||||
system.cpu2: completed 10000 read, 5302 write accesses @590705
|
||||
system.cpu1: completed 20000 read, 10655 write accesses @1140898
|
||||
system.cpu7: completed 20000 read, 10580 write accesses @1148482
|
||||
system.cpu4: completed 20000 read, 10689 write accesses @1149967
|
||||
system.cpu0: completed 20000 read, 10632 write accesses @1151560
|
||||
system.cpu3: completed 20000 read, 10736 write accesses @1152482
|
||||
system.cpu5: completed 20000 read, 10944 write accesses @1160453
|
||||
system.cpu6: completed 20000 read, 10906 write accesses @1167829
|
||||
system.cpu2: completed 20000 read, 10785 write accesses @1181432
|
||||
system.cpu7: completed 30000 read, 15883 write accesses @1719841
|
||||
system.cpu1: completed 30000 read, 16166 write accesses @1721891
|
||||
system.cpu4: completed 30000 read, 16033 write accesses @1722326
|
||||
system.cpu3: completed 30000 read, 16219 write accesses @1736719
|
||||
system.cpu0: completed 30000 read, 16143 write accesses @1737446
|
||||
system.cpu5: completed 30000 read, 16313 write accesses @1738202
|
||||
system.cpu6: completed 30000 read, 16098 write accesses @1755658
|
||||
system.cpu2: completed 30000 read, 16394 write accesses @1762469
|
||||
system.cpu7: completed 40000 read, 21291 write accesses @2297271
|
||||
system.cpu1: completed 40000 read, 21590 write accesses @2298548
|
||||
system.cpu4: completed 40000 read, 21488 write accesses @2312342
|
||||
system.cpu6: completed 40000 read, 21332 write accesses @2321888
|
||||
system.cpu5: completed 40000 read, 21705 write accesses @2326997
|
||||
system.cpu3: completed 40000 read, 21707 write accesses @2330357
|
||||
system.cpu2: completed 40000 read, 21706 write accesses @2332615
|
||||
system.cpu0: completed 40000 read, 21524 write accesses @2334713
|
||||
system.cpu7: completed 50000 read, 26831 write accesses @2881244
|
||||
system.cpu1: completed 50000 read, 27020 write accesses @2890941
|
||||
system.cpu4: completed 50000 read, 27058 write accesses @2898430
|
||||
system.cpu3: completed 50000 read, 27008 write accesses @2902889
|
||||
system.cpu6: completed 50000 read, 26758 write accesses @2903882
|
||||
system.cpu5: completed 50000 read, 27004 write accesses @2909259
|
||||
system.cpu0: completed 50000 read, 27056 write accesses @2926100
|
||||
system.cpu2: completed 50000 read, 27098 write accesses @2926472
|
||||
system.cpu7: completed 60000 read, 32186 write accesses @3453644
|
||||
system.cpu4: completed 60000 read, 32482 write accesses @3465349
|
||||
system.cpu1: completed 60000 read, 32394 write accesses @3472313
|
||||
system.cpu5: completed 60000 read, 32325 write accesses @3483119
|
||||
system.cpu3: completed 60000 read, 32421 write accesses @3485537
|
||||
system.cpu6: completed 60000 read, 32185 write accesses @3493077
|
||||
system.cpu0: completed 60000 read, 32338 write accesses @3495286
|
||||
system.cpu2: completed 60000 read, 32370 write accesses @3496153
|
||||
system.cpu7: completed 70000 read, 37611 write accesses @4033523
|
||||
system.cpu4: completed 70000 read, 37774 write accesses @4042787
|
||||
system.cpu1: completed 70000 read, 37690 write accesses @4052999
|
||||
system.cpu3: completed 70000 read, 37732 write accesses @4060208
|
||||
system.cpu5: completed 70000 read, 37748 write accesses @4060547
|
||||
system.cpu2: completed 70000 read, 37645 write accesses @4064696
|
||||
system.cpu0: completed 70000 read, 37774 write accesses @4071656
|
||||
system.cpu6: completed 70000 read, 37516 write accesses @4081376
|
||||
system.cpu7: completed 80000 read, 43002 write accesses @4618082
|
||||
system.cpu4: completed 80000 read, 42974 write accesses @4622306
|
||||
system.cpu2: completed 80000 read, 43016 write accesses @4629591
|
||||
system.cpu3: completed 80000 read, 43060 write accesses @4631933
|
||||
system.cpu0: completed 80000 read, 42919 write accesses @4636700
|
||||
system.cpu5: completed 80000 read, 43162 write accesses @4639808
|
||||
system.cpu1: completed 80000 read, 42988 write accesses @4647998
|
||||
system.cpu6: completed 80000 read, 42866 write accesses @4656086
|
||||
system.cpu7: completed 90000 read, 48437 write accesses @5173289
|
||||
system.cpu4: completed 90000 read, 48464 write accesses @5207890
|
||||
system.cpu3: completed 90000 read, 48532 write accesses @5210569
|
||||
system.cpu2: completed 90000 read, 48392 write accesses @5213621
|
||||
system.cpu5: completed 90000 read, 48493 write accesses @5223220
|
||||
system.cpu0: completed 90000 read, 48496 write accesses @5233894
|
||||
system.cpu6: completed 90000 read, 48247 write accesses @5234744
|
||||
system.cpu1: completed 90000 read, 48380 write accesses @5239171
|
||||
system.cpu7: completed 100000 read, 53766 write accesses @5747338
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:27:37
|
||||
gem5 started Jul 28 2012 11:35:39
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 13:53:26
|
||||
gem5 started Sep 1 2012 13:54:47
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19129199 because maximum number of loads reached
|
||||
Exiting @ tick 5747338 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019129 # Number of seconds simulated
|
||||
sim_ticks 19129199 # Number of ticks simulated
|
||||
final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.005747 # Number of seconds simulated
|
||||
sim_ticks 5747338 # Number of ticks simulated
|
||||
final_tick 5747338 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 190724 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378788 # Number of bytes of host memory used
|
||||
host_seconds 100.30 # Real time elapsed on the host
|
||||
host_tick_rate 47566 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409708 # Number of bytes of host memory used
|
||||
host_seconds 120.83 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -157,29 +157,29 @@ system.dir_cntrl0.probeFilter.num_tag_array_reads 0
|
|||
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
|
||||
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53893 # number of write accesses completed
|
||||
system.cpu0.num_reads 98701 # number of read accesses completed
|
||||
system.cpu0.num_writes 53180 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99845 # number of read accesses completed
|
||||
system.cpu1.num_writes 52936 # number of write accesses completed
|
||||
system.cpu1.num_reads 98822 # number of read accesses completed
|
||||
system.cpu1.num_writes 52970 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99959 # number of read accesses completed
|
||||
system.cpu2.num_writes 53318 # number of write accesses completed
|
||||
system.cpu2.num_reads 99173 # number of read accesses completed
|
||||
system.cpu2.num_writes 53394 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99709 # number of read accesses completed
|
||||
system.cpu3.num_writes 53594 # number of write accesses completed
|
||||
system.cpu3.num_reads 99438 # number of read accesses completed
|
||||
system.cpu3.num_writes 53653 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99622 # number of read accesses completed
|
||||
system.cpu4.num_writes 53609 # number of write accesses completed
|
||||
system.cpu4.num_reads 99047 # number of read accesses completed
|
||||
system.cpu4.num_writes 53311 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99608 # number of read accesses completed
|
||||
system.cpu5.num_writes 53591 # number of write accesses completed
|
||||
system.cpu5.num_reads 99288 # number of read accesses completed
|
||||
system.cpu5.num_writes 53451 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99715 # number of read accesses completed
|
||||
system.cpu6.num_writes 54030 # number of write accesses completed
|
||||
system.cpu6.num_reads 98768 # number of read accesses completed
|
||||
system.cpu6.num_writes 53052 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97913 # number of read accesses completed
|
||||
system.cpu7.num_writes 53717 # number of write accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53766 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -8,8 +8,9 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcbus funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -30,6 +31,7 @@ system_port=system.sys_port_proxy.slave[0]
|
|||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -42,12 +44,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
functional=system.funcbus.slave[0]
|
||||
test=system.l1_cntrl0.sequencer.slave[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -60,12 +63,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
functional=system.funcbus.slave[1]
|
||||
test=system.l1_cntrl1.sequencer.slave[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -78,12 +82,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
functional=system.funcbus.slave[2]
|
||||
test=system.l1_cntrl2.sequencer.slave[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -96,12 +101,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
functional=system.funcbus.slave[3]
|
||||
test=system.l1_cntrl3.sequencer.slave[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -114,12 +120,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
functional=system.funcbus.slave[4]
|
||||
test=system.l1_cntrl4.sequencer.slave[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -132,12 +139,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
functional=system.funcbus.slave[5]
|
||||
test=system.l1_cntrl5.sequencer.slave[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -150,12 +158,13 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
functional=system.funcbus.slave[6]
|
||||
test=system.l1_cntrl6.sequencer.slave[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
clock=1
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
|
|
@ -168,7 +177,7 @@ progress_interval=10000
|
|||
suppress_func_warnings=true
|
||||
sys=system
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
functional=system.funcbus.slave[7]
|
||||
test=system.l1_cntrl7.sequencer.slave[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
|
|
@ -200,9 +209,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -211,11 +220,23 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcbus]
|
||||
type=NoncoherentBus
|
||||
block_size=64
|
||||
clock=1
|
||||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.funcmem.port
|
||||
slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.funcmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=false
|
||||
|
|
@ -224,7 +245,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
|
|
@ -259,6 +280,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
|
|
@ -305,6 +327,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl1.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.cacheMemory
|
||||
|
|
@ -351,6 +374,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl2.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.cacheMemory
|
||||
|
|
@ -397,6 +421,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl3.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.cacheMemory
|
||||
|
|
@ -443,6 +468,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl4.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.cacheMemory
|
||||
|
|
@ -489,6 +515,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl5.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.cacheMemory
|
||||
|
|
@ -535,6 +562,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl6.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.cacheMemory
|
||||
|
|
@ -581,6 +609,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl7.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.cacheMemory
|
||||
|
|
@ -596,6 +625,7 @@ slave=system.cpu7.test
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -858,6 +888,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
|
|||
|
|
@ -1,26 +1,26 @@
|
|||
Real time: Jul/10/2012 17:28:36
|
||||
Real time: Sep/01/2012 13:48:23
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 61
|
||||
Elapsed_time_in_minutes: 1.01667
|
||||
Elapsed_time_in_hours: 0.0169444
|
||||
Elapsed_time_in_days: 0.000706019
|
||||
Elapsed_time_in_seconds: 43
|
||||
Elapsed_time_in_minutes: 0.716667
|
||||
Elapsed_time_in_hours: 0.0119444
|
||||
Elapsed_time_in_days: 0.000497685
|
||||
|
||||
Virtual_time_in_seconds: 60.59
|
||||
Virtual_time_in_minutes: 1.00983
|
||||
Virtual_time_in_hours: 0.0168306
|
||||
Virtual_time_in_days: 0.000701273
|
||||
Virtual_time_in_seconds: 43.31
|
||||
Virtual_time_in_minutes: 0.721833
|
||||
Virtual_time_in_hours: 0.0120306
|
||||
Virtual_time_in_days: 0.000501273
|
||||
|
||||
Ruby_current_time: 28725020
|
||||
Ruby_current_time: 8642753
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 28725020
|
||||
Ruby_cycles: 8642753
|
||||
|
||||
mbytes_resident: 59.0156
|
||||
mbytes_total: 370.527
|
||||
resident_ratio: 0.159285
|
||||
mbytes_resident: 60.6562
|
||||
mbytes_total: 399.672
|
||||
resident_ratio: 0.151804
|
||||
|
||||
ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ]
|
||||
ruby_cycles_executed: [ 8642754 8642754 8642754 8642754 8642754 8642754 8642754 8642754 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -30,29 +30,29 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615998 average: 15.9984 | standard deviation: 0.126895 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615878 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 616251 average: 15.9984 | standard deviation: 0.126869 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 616131 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 17550 count: 615870 average: 5969.46 | standard deviation: 7116.59 | 0 4 6 6 5 4 5 1 5 4 3 6 4 5 21 31 46 90 169 235 418 648 1027 1394 1760 2694 3780 4717 5558 6535 8753 9589 11125 13750 13954 15292 17133 20395 19978 18654 22068 23938 22152 22290 22426 24096 21689 21471 22547 19077 18860 18264 18773 15923 13248 14135 13631 11388 10257 9512 9377 7381 6802 6677 5240 4722 4293 4074 3235 2564 2639 2296 1833 1614 1375 1233 1052 854 776 591 544 492 453 330 284 288 215 200 140 122 116 82 91 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 17550 count: 400035 average: 5968.22 | standard deviation: 1417.97 | 0 4 3 5 3 2 4 1 2 2 1 2 2 4 14 21 27 59 108 148 275 433 688 907 1155 1771 2429 3013 3676 4199 5764 6270 7293 8986 9054 9918 11064 13179 12948 12115 14336 15590 14383 14461 14549 15708 14037 13915 14593 12436 12325 11870 12195 10304 8534 9247 8896 7405 6689 6174 6004 4768 4401 4309 3422 3106 2791 2621 2096 1647 1749 1478 1176 1060 878 801 692 570 497 397 361 314 289 233 190 190 131 126 85 78 64 59 58 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 128 max: 16420 count: 215835 average: 5971.76 | standard deviation: 1418.95 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 7 10 19 31 61 87 143 215 339 487 605 923 1351 1704 1882 2336 2989 3319 3832 4764 4900 5374 6069 7216 7030 6539 7732 8348 7769 7829 7877 8388 7652 7556 7954 6641 6535 6394 6578 5619 4714 4888 4735 3983 3568 3338 3373 2613 2401 2368 1818 1616 1502 1453 1139 917 890 818 657 554 497 432 360 284 279 194 183 178 164 97 94 98 84 74 55 44 52 23 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 128 max: 17550 count: 607509 average: 5975.88 | standard deviation: 7210.5 | 0 4 6 6 5 4 5 1 5 4 2 6 4 5 17 27 42 88 158 222 402 618 977 1328 1698 2630 3655 4589 5430 6369 8536 9419 10886 13519 13647 15042 16854 20026 19684 18343 21765 23626 21819 22017 22137 23782 21417 21230 22311 18836 18644 18063 18598 15763 13119 14010 13517 11272 10178 9410 9289 7324 6756 6627 5186 4688 4257 4046 3210 2538 2620 2281 1809 1600 1365 1221 1045 850 772 587 539 484 451 326 282 287 213 200 140 121 112 80 90 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 64 max: 11892 count: 8361 average: 5503.07 | standard deviation: 1405.32 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 2 2 2 1 3 0 2 5 6 7 6 10 6 16 14 19 31 39 27 26 36 23 41 67 58 59 69 63 65 72 94 106 111 94 76 113 126 110 121 152 155 134 116 137 142 173 196 157 137 171 140 153 150 150 162 167 166 135 138 142 147 168 146 131 141 113 128 99 137 136 105 110 106 88 113 83 92 85 75 72 57 65 60 51 63 66 50 39 40 51 51 44 44 31 26 20 26 28 22 29 25 18 16 22 14 12 16 13 12 15 11 12 7 7 8 15 9 5 9 4 6 7 5 4 3 3 1 2 2 3 1 3 2 4 4 1 1 2 2 2 0 1 0 0 2 0 0 0 0 1 0 3 1 1 1 0 1 ]
|
||||
miss_latency: [binsize: 32 max: 4776 count: 616123 average: 1795.35 | standard deviation: 414.477 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 24 35 84 107 158 246 394 516 799 1053 1257 1834 2502 2826 3510 4476 5278 6753 7207 7603 9693 11698 11058 12663 14078 14754 17257 16918 15782 18905 20633 18435 19307 19900 19344 21176 19234 17152 19082 20051 16188 16264 15715 14908 15416 13291 11277 12219 11916 9452 9307 8556 7808 7864 6457 5309 5581 5515 4250 3842 3580 3265 3103 2466 1908 2073 1994 1517 1313 1242 1090 1028 790 677 670 662 435 413 368 358 318 235 216 208 174 141 115 105 85 103 63 53 50 50 35 26 25 21 27 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4737 count: 400262 average: 1795.26 | standard deviation: 414.645 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 23 53 66 110 159 266 334 537 699 799 1186 1637 1820 2298 2878 3407 4350 4680 4906 6373 7625 7226 8201 9120 9644 11229 10853 10342 12294 13400 12030 12512 12946 12569 13875 12476 11156 12382 13030 10587 10544 10172 9663 9945 8585 7315 7818 7765 6162 6022 5538 5088 5151 4134 3417 3701 3583 2767 2452 2314 2095 1997 1601 1255 1387 1294 988 884 833 737 684 490 452 419 436 288 285 220 225 214 149 143 140 122 94 73 73 51 66 34 32 32 31 24 15 10 10 18 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4776 count: 215861 average: 1795.51 | standard deviation: 414.166 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 13 12 31 41 48 87 128 182 262 354 458 648 865 1006 1212 1598 1871 2403 2527 2697 3320 4073 3832 4462 4958 5110 6028 6065 5440 6611 7233 6405 6795 6954 6775 7301 6758 5996 6700 7021 5601 5720 5543 5245 5471 4706 3962 4401 4151 3290 3285 3018 2720 2713 2323 1892 1880 1932 1483 1390 1266 1170 1106 865 653 686 700 529 429 409 353 344 300 225 251 226 147 128 148 133 104 86 73 68 52 47 42 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4776 count: 607868 average: 1796.88 | standard deviation: 414.375 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 23 33 79 102 150 235 382 500 770 1020 1209 1785 2449 2745 3429 4369 5167 6620 7042 7423 9530 11521 10828 12435 13885 14505 16983 16670 15485 18664 20359 18181 19011 19634 19059 20930 19001 16911 18870 19850 15969 16076 15575 14760 15247 13149 11146 12125 11810 9354 9206 8478 7728 7786 6400 5234 5534 5471 4213 3806 3559 3230 3075 2450 1891 2058 1978 1499 1308 1237 1081 1020 780 667 662 659 434 408 362 357 314 235 214 208 174 140 113 104 84 103 63 53 50 50 35 26 25 21 26 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 32 max: 3752 count: 8255 average: 1682.74 | standard deviation: 406.431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 5 5 8 11 12 16 29 33 48 49 53 81 81 107 111 133 165 180 163 177 230 228 193 249 274 248 297 241 274 254 296 266 285 246 233 241 212 201 219 188 140 148 169 142 131 94 106 98 101 78 80 78 57 75 47 44 37 36 21 35 28 16 17 15 16 18 5 5 9 8 10 10 8 3 1 5 6 1 4 0 2 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 8361
|
||||
imcomplete_wCC_Times: 8255
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 4 max: 539 count: 7 average: 334.714 | standard deviation: 168.608 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 607502
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 17550 count: 394629 average: 5974.59 | standard deviation: 1417.29 | 0 4 3 5 3 2 4 1 2 2 0 2 2 4 12 19 26 58 101 141 268 411 656 862 1113 1732 2355 2930 3601 4101 5626 6152 7140 8833 8863 9755 10888 12929 12755 11909 14133 15388 14160 14288 14352 15497 13858 13765 14436 12280 12181 11739 12073 10206 8456 9180 8819 7329 6645 6110 5948 4735 4371 4278 3389 3086 2766 2599 2081 1630 1735 1469 1159 1055 871 794 686 566 493 394 358 310 288 231 189 189 130 126 85 78 62 58 57 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11892 count: 5406 average: 5502.87 | standard deviation: 1389.98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 3 4 6 1 3 4 11 11 12 20 23 22 18 24 18 21 41 33 36 47 39 36 42 56 71 67 63 55 69 84 71 82 98 93 85 78 90 86 118 132 103 90 116 90 106 97 93 109 110 113 88 85 95 102 115 96 79 100 69 81 57 100 89 67 62 82 57 74 55 67 55 43 46 32 35 32 35 42 42 34 22 22 37 27 26 30 18 15 12 18 20 11 14 19 9 11 15 10 10 12 10 5 9 8 10 4 5 4 10 7 2 3 2 5 4 3 4 2 3 1 2 2 2 1 2 1 0 4 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 128 max: 16420 count: 212880 average: 5978.26 | standard deviation: 1417.67 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 5 8 16 30 57 81 134 207 321 466 585 898 1300 1659 1829 2268 2910 3267 3746 4686 4784 5287 5966 7097 6929 6434 7632 8238 7659 7729 7785 8285 7559 7465 7875 6556 6463 6324 6525 5557 4663 4830 4698 3943 3533 3300 3341 2589 2385 2349 1797 1602 1491 1447 1129 908 885 812 650 545 494 427 359 284 279 193 181 174 163 95 93 98 83 74 55 43 50 22 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 11673 count: 2955 average: 5503.42 | standard deviation: 1433.2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 0 1 2 2 1 5 7 2 5 3 7 11 16 5 8 12 5 20 26 25 23 22 24 29 30 38 35 44 31 21 44 42 39 39 54 62 49 38 47 56 55 64 54 47 55 50 47 53 57 53 57 53 47 53 47 45 53 50 52 41 44 47 42 37 47 38 48 24 31 39 28 25 30 32 26 25 30 28 16 21 24 16 17 18 14 24 18 14 13 11 8 8 8 11 15 6 9 5 7 4 2 4 3 7 6 3 2 3 2 4 5 2 3 6 2 1 3 2 0 1 0 0 0 0 1 0 1 1 4 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 2 0 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 175 count: 7 average: 113.714 | standard deviation: 50.5833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 607861
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4737 count: 394885 average: 1796.82 | standard deviation: 414.485 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 21 49 64 105 152 257 322 518 679 769 1153 1596 1772 2247 2811 3334 4264 4563 4792 6261 7499 7072 8051 8990 9488 11054 10677 10152 12134 13228 11861 12318 12772 12386 13725 12331 11008 12241 12895 10439 10424 10080 9578 9838 8498 7238 7755 7697 6105 5957 5481 5033 5099 4100 3368 3668 3554 2742 2429 2302 2071 1979 1590 1241 1375 1283 979 882 829 732 677 483 443 413 433 287 283 216 225 211 149 141 140 122 93 72 72 50 66 34 32 32 31 24 15 10 10 17 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 3752 count: 5377 average: 1681.26 | standard deviation: 410.533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 2 5 7 9 12 19 20 30 33 41 48 51 67 73 86 117 114 112 126 154 150 130 156 175 176 190 160 172 169 194 174 183 150 145 148 141 135 148 120 92 85 107 87 77 63 68 57 65 57 55 52 34 49 33 29 25 23 12 24 18 11 14 12 11 9 2 4 5 7 7 9 6 3 1 2 4 0 3 0 2 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4776 count: 212983 average: 1797 | standard deviation: 414.172 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 12 12 30 38 45 83 125 178 252 341 440 632 853 973 1182 1558 1833 2356 2479 2631 3269 4022 3756 4384 4895 5017 5929 5993 5333 6530 7131 6320 6693 6862 6673 7205 6670 5903 6629 6955 5530 5652 5495 5182 5409 4651 3908 4370 4113 3249 3249 2997 2695 2687 2300 1866 1866 1917 1471 1377 1257 1159 1096 860 650 683 695 520 426 408 349 343 297 224 249 226 147 125 146 132 103 86 73 68 52 47 41 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3360 count: 2878 average: 1685.51 | standard deviation: 398.712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3 3 4 3 4 10 13 18 16 12 33 30 40 38 47 48 66 51 51 76 78 63 93 99 72 107 81 102 85 102 92 102 96 88 93 71 66 71 68 48 63 62 55 54 31 38 41 36 21 25 26 23 26 14 15 12 13 9 11 10 5 3 3 5 9 3 1 4 1 3 1 2 0 0 3 2 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -66,11 +66,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 3 count: 615870 average: 0.000342605 | standard deviation: 0.0243446 | 615732 69 65 4 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 618018 average: 0.01454 | standard deviation: 0.24705 | 615646 19 113 443 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 616123 average: 0.000835872 | standard deviation: 0.0469998 | 615902 40 84 81 16 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 21 count: 618697 average: 0.01353 | standard deviation: 0.214574 | 615412 911 734 765 856 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -82,337 +82,337 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 60
|
||||
user_time: 43
|
||||
system_time: 0
|
||||
page_reclaims: 16275
|
||||
page_reclaims: 11522
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 184
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1847643 14781144
|
||||
total_msg_count_Data: 1829024 131689728
|
||||
total_msg_count_Response_Data: 1847610 133027920
|
||||
total_msg_count_Writeback_Control: 1854054 14832432
|
||||
total_msgs: 7378331 total_bytes: 294331224
|
||||
total_msg_count_Control: 1848417 14787336
|
||||
total_msg_count_Data: 1831398 131860656
|
||||
total_msg_count_Response_Data: 1848370 133082640
|
||||
total_msg_count_Writeback_Control: 1856091 14848728
|
||||
total_msgs: 7384276 total_bytes: 294579360
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.34528
|
||||
links_utilized_percent_switch_0_link_0: 1.34317 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.34738 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 4.48511
|
||||
links_utilized_percent_switch_0_link_0: 4.47733 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.49289 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 77138 617104 [ 0 0 77138 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76420 5502240 [ 0 0 76420 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 77364 618912 [ 0 0 77364 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76700 5522400 [ 0 0 76700 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 995 71640 [ 0 0 0 0 995 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.34599
|
||||
links_utilized_percent_switch_1_link_0: 1.34421 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.34776 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 4.47412
|
||||
links_utilized_percent_switch_1_link_0: 4.46635 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 4.48189 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 77201 617608 [ 0 0 77201 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 76436 5503392 [ 0 0 76436 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 77173 617384 [ 0 0 77173 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 76458 5504976 [ 0 0 76458 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1047 75384 [ 0 0 0 0 1047 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.34111
|
||||
links_utilized_percent_switch_2_link_0: 1.33905 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.34318 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 4.45232
|
||||
links_utilized_percent_switch_2_link_0: 4.44489 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.45975 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76900 615200 [ 0 0 76900 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 76098 5479056 [ 0 0 76098 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1097 78984 [ 0 0 0 0 1097 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76801 614408 [ 0 0 76801 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 76122 5480784 [ 0 0 76122 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 999 71928 [ 0 0 0 0 999 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 1.34039
|
||||
links_utilized_percent_switch_3_link_0: 1.33852 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.34225 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 4.4511
|
||||
links_utilized_percent_switch_3_link_0: 4.44343 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 4.45876 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76875 615000 [ 0 0 76875 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 76106 5479632 [ 0 0 76106 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1033 74376 [ 0 0 0 0 1033 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76775 614200 [ 0 0 76775 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 76039 5474808 [ 0 0 76039 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1066 76752 [ 0 0 0 0 1066 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 1.34098
|
||||
links_utilized_percent_switch_4_link_0: 1.33927 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 1.34269 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4: 4.47992
|
||||
links_utilized_percent_switch_4_link_0: 4.47268 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 4.48716 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 76918 615344 [ 0 0 76918 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76104 5479488 [ 0 0 76104 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 1058 76176 [ 0 0 0 0 1058 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 77282 618256 [ 0 0 77282 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76562 5512464 [ 0 0 76562 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 1032 74304 [ 0 0 0 0 1032 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 1.34326
|
||||
links_utilized_percent_switch_5_link_0: 1.34149 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 1.34504 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 4.45778
|
||||
links_utilized_percent_switch_5_link_0: 4.44972 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 4.46585 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 77044 616352 [ 0 0 77044 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76280 5492160 [ 0 0 76280 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76151 5482872 [ 0 0 76151 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1078 77616 [ 0 0 0 0 1078 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 1.33528
|
||||
links_utilized_percent_switch_6_link_0: 1.33337 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 1.33719 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 4.46993
|
||||
links_utilized_percent_switch_6_link_0: 4.46316 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 4.4767 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 76576 612608 [ 0 0 76576 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 75797 5457384 [ 0 0 75797 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 1052 75744 [ 0 0 0 0 1052 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 77121 616968 [ 0 0 77121 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 76391 5500152 [ 0 0 76391 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 1020 73440 [ 0 0 0 0 1020 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 1.34665
|
||||
links_utilized_percent_switch_7_link_0: 1.34474 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 1.34856 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7: 4.44875
|
||||
links_utilized_percent_switch_7_link_0: 4.44123 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 4.45627 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 77229 617832 [ 0 0 77229 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 76434 5503248 [ 0 0 76434 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1068 76896 [ 0 0 0 0 1068 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 76740 613920 [ 0 0 76740 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 76043 5475096 [ 0 0 76043 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 10.608
|
||||
links_utilized_percent_switch_8_link_0: 10.6231 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 10.5929 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8: 35.2892
|
||||
links_utilized_percent_switch_8_link_0: 35.3495 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 35.229 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 609674 43896528 [ 0 0 609674 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 607509 43740648 [ 0 0 0 0 607509 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 618018 4944144 [ 0 0 0 618018 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 607869 43766568 [ 0 0 0 0 607869 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 618697 4949576 [ 0 0 0 618697 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 2.37188
|
||||
links_utilized_percent_switch_9_link_0: 1.34318 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 1.34421 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 1.33905 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 1.33852 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 1.33927 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 1.34149 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 1.33337 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 1.34474 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 10.6231 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9: 7.88981
|
||||
links_utilized_percent_switch_9_link_0: 4.47733 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 4.46635 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 4.44489 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 4.44343 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 4.4727 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 4.44972 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 4.46316 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 4.44123 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 35.3495 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 609675 43896600 [ 0 0 609675 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 77138
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 77138
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 77364
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 77364
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.2065%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.7935%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.016%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.984%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77138 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77364 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
|
||||
Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
|
||||
Data [76917 77043 76575 77228 77136 77200 76899 76872 ] 615870
|
||||
Fwd_GETX [1058 1018 1052 1068 1017 1018 1097 1033 ] 8361
|
||||
Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867
|
||||
Data [77282 76881 77119 76737 77360 77170 76800 76774 ] 616123
|
||||
Fwd_GETX [1032 1078 1020 1018 995 1047 999 1066 ] 8255
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [76914 77040 76572 77225 77134 77197 76896 76872 ] 615850
|
||||
Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
|
||||
Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
|
||||
Replacement [77281 76879 77117 76736 77360 77169 76797 76771 ] 616110
|
||||
Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828
|
||||
Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614
|
||||
|
||||
- Transitions -
|
||||
I Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
|
||||
I Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
|
||||
I Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [810 760 775 791 714 761 798 766 ] 6175
|
||||
I Replacement [716 728 726 693 660 711 675 732 ] 5641
|
||||
|
||||
II Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
|
||||
II Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614
|
||||
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [810 760 775 791 714 761 798 766 ] 6175
|
||||
M Fwd_GETX [716 728 726 693 660 711 675 732 ] 5641
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [76104 76280 75797 76434 76420 76436 76098 76106 ] 609675
|
||||
M Replacement [76565 76151 76391 76043 76700 76458 76122 76039 ] 610469
|
||||
|
||||
MI Fwd_GETX [248 258 277 277 303 257 299 267 ] 2186
|
||||
MI Fwd_GETX [316 350 294 325 335 336 324 334 ] 2614
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
|
||||
MI Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data [50061 49936 49885 50168 50297 50005 49691 49992 ] 400035
|
||||
IS Data [50041 50016 50022 50034 50297 50229 49853 49770 ] 400262
|
||||
|
||||
IM Data [26856 27107 26690 27060 26839 27195 27208 26880 ] 215835
|
||||
IM Data [27241 26865 27097 26703 27063 26941 26947 27004 ] 215861
|
||||
|
||||
Cache Stats: system.l1_cntrl1.cacheMemory
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 77201
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 77201
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 77173
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 77173
|
||||
system.l1_cntrl1.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 64.7738%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 35.2262%
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 65.0901%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 34.9099%
|
||||
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77201 100%
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77173 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl2.cacheMemory
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76900
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76900
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76801
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76801
|
||||
system.l1_cntrl2.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 64.619%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 35.381%
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 64.9119%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 35.0881%
|
||||
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76900 100%
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76801 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl3.cacheMemory
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76876
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76876
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76775
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76775
|
||||
system.l1_cntrl3.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 65.032%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 34.968%
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.8271%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.1729%
|
||||
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76876 100%
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76775 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl4.cacheMemory
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 76918
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 76918
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 77285
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 77285
|
||||
system.l1_cntrl4.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 65.0849%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 34.9151%
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 64.75%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 35.25%
|
||||
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 76918 100%
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 77285 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl5.cacheMemory
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 77044
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 77044
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 76883
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 76883
|
||||
system.l1_cntrl5.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 64.8149%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 35.1851%
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 65.056%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 34.944%
|
||||
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 77044 100%
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76883 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl6.cacheMemory
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 76576
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 76576
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 77121
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 77121
|
||||
system.l1_cntrl6.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 65.1444%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 34.8556%
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 64.8643%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 35.1357%
|
||||
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 76576 100%
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 77121 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl7.cacheMemory
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 77229
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 77229
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 76740
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 76740
|
||||
system.l1_cntrl7.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 64.9613%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 35.0387%
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.2033%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.7967%
|
||||
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 77229 100%
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76740 100%
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1215007
|
||||
memory_reads: 607514
|
||||
memory_writes: 607471
|
||||
memory_refreshes: 59844
|
||||
memory_total_request_delays: 94490839
|
||||
memory_delays_per_request: 77.7698
|
||||
memory_delays_in_input_queue: 4956280
|
||||
memory_delays_behind_head_of_bank_queue: 42721539
|
||||
memory_delays_stalled_at_head_of_bank_queue: 46813020
|
||||
memory_stalls_for_bank_busy: 7203781
|
||||
memory_total_requests: 1215736
|
||||
memory_reads: 607873
|
||||
memory_writes: 607828
|
||||
memory_refreshes: 60020
|
||||
memory_total_request_delays: 87259380
|
||||
memory_delays_per_request: 71.7749
|
||||
memory_delays_in_input_queue: 1519458
|
||||
memory_delays_behind_head_of_bank_queue: 40027777
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45712145
|
||||
memory_stalls_for_bank_busy: 7071199
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 12030630
|
||||
memory_stalls_for_arbitration: 9262268
|
||||
memory_stalls_for_bus: 12663868
|
||||
memory_stalls_for_anti_starvation: 11246699
|
||||
memory_stalls_for_arbitration: 9161203
|
||||
memory_stalls_for_bus: 12538876
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4593756
|
||||
memory_stalls_for_read_read_turnaround: 1058717
|
||||
accesses_per_bank: 38064 37906 37810 38185 38131 38139 38459 38015 38286 38038 38075 38326 37705 37695 37985 37984 37848 37764 37931 38109 38114 37875 38032 37917 37934 37358 38024 37068 37768 38020 38377 38065
|
||||
memory_stalls_for_read_write_turnaround: 4625197
|
||||
memory_stalls_for_read_read_turnaround: 1068971
|
||||
accesses_per_bank: 38200 37933 37788 38170 38170 38159 38358 38044 38330 38092 38142 38320 37763 37679 37948 38038 37829 37792 38064 38023 38122 37894 38063 37979 37916 37422 38015 37136 37884 38037 38326 38100
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [1243024 ] 1243024
|
||||
GETX [786348 ] 786348
|
||||
GETS [0 ] 0
|
||||
PUTX [607488 ] 607488
|
||||
PUTX_NotOwner [2186 ] 2186
|
||||
PUTX [607852 ] 607852
|
||||
PUTX_NotOwner [2614 ] 2614
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [607509 ] 607509
|
||||
Memory_Ack [607471 ] 607471
|
||||
Memory_Data [607869 ] 607869
|
||||
Memory_Ack [607828 ] 607828
|
||||
|
||||
- Transitions -
|
||||
I GETX [607519 ] 607519
|
||||
I GETX [607884 ] 607884
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [8361 ] 8361
|
||||
M PUTX [607488 ] 607488
|
||||
M PUTX_NotOwner [2186 ] 2186
|
||||
M GETX [8255 ] 8255
|
||||
M PUTX [607852 ] 607852
|
||||
M PUTX_NotOwner [2614 ] 2614
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -428,21 +428,21 @@ M_DWRI Memory_Ack [0 ] 0
|
|||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [250002 ] 250002
|
||||
IM GETX [65216 ] 65216
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [607509 ] 607509
|
||||
IM Memory_Data [607869 ] 607869
|
||||
|
||||
MI GETX [377142 ] 377142
|
||||
MI GETX [104993 ] 104993
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [607471 ] 607471
|
||||
MI Memory_Ack [607828 ] 607828
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read, 5419 write accesses @2858002
|
||||
system.cpu7: completed 10000 read, 5473 write accesses @2858520
|
||||
system.cpu0: completed 10000 read, 5305 write accesses @2868940
|
||||
system.cpu1: completed 10000 read, 5416 write accesses @2893421
|
||||
system.cpu4: completed 10000 read, 5371 write accesses @2900102
|
||||
system.cpu2: completed 10000 read, 5337 write accesses @2905419
|
||||
system.cpu3: completed 10000 read, 5513 write accesses @2916882
|
||||
system.cpu6: completed 10000 read, 5458 write accesses @2971509
|
||||
system.cpu1: completed 20000 read, 10866 write accesses @5727829
|
||||
system.cpu0: completed 20000 read, 10592 write accesses @5734440
|
||||
system.cpu4: completed 20000 read, 10679 write accesses @5748810
|
||||
system.cpu7: completed 20000 read, 10819 write accesses @5759030
|
||||
system.cpu3: completed 20000 read, 10666 write accesses @5769940
|
||||
system.cpu5: completed 20000 read, 10771 write accesses @5778709
|
||||
system.cpu6: completed 20000 read, 10832 write accesses @5805350
|
||||
system.cpu2: completed 20000 read, 10785 write accesses @5828740
|
||||
system.cpu1: completed 30000 read, 16207 write accesses @8557570
|
||||
system.cpu0: completed 30000 read, 15949 write accesses @8566069
|
||||
system.cpu7: completed 30000 read, 16214 write accesses @8624139
|
||||
system.cpu4: completed 30000 read, 16127 write accesses @8660230
|
||||
system.cpu3: completed 30000 read, 16038 write accesses @8676099
|
||||
system.cpu5: completed 30000 read, 16217 write accesses @8736099
|
||||
system.cpu6: completed 30000 read, 16240 write accesses @8737471
|
||||
system.cpu2: completed 30000 read, 16356 write accesses @8775610
|
||||
system.cpu4: completed 40000 read, 21442 write accesses @11430710
|
||||
system.cpu1: completed 40000 read, 21431 write accesses @11446880
|
||||
system.cpu0: completed 40000 read, 21249 write accesses @11450119
|
||||
system.cpu7: completed 40000 read, 21591 write accesses @11495090
|
||||
system.cpu3: completed 40000 read, 21525 write accesses @11637130
|
||||
system.cpu6: completed 40000 read, 21625 write accesses @11655440
|
||||
system.cpu5: completed 40000 read, 21557 write accesses @11655900
|
||||
system.cpu2: completed 40000 read, 22064 write accesses @11762920
|
||||
system.cpu0: completed 50000 read, 26643 write accesses @14301920
|
||||
system.cpu7: completed 50000 read, 26956 write accesses @14350920
|
||||
system.cpu1: completed 50000 read, 26912 write accesses @14419140
|
||||
system.cpu4: completed 50000 read, 27035 write accesses @14428630
|
||||
system.cpu3: completed 50000 read, 26875 write accesses @14456189
|
||||
system.cpu6: completed 50000 read, 26968 write accesses @14552960
|
||||
system.cpu5: completed 50000 read, 27033 write accesses @14560100
|
||||
system.cpu2: completed 50000 read, 27494 write accesses @14706770
|
||||
system.cpu0: completed 60000 read, 32018 write accesses @17124880
|
||||
system.cpu7: completed 60000 read, 32300 write accesses @17213372
|
||||
system.cpu3: completed 60000 read, 32247 write accesses @17322589
|
||||
system.cpu4: completed 60000 read, 32351 write accesses @17326542
|
||||
system.cpu1: completed 60000 read, 32302 write accesses @17368660
|
||||
system.cpu6: completed 60000 read, 32274 write accesses @17446980
|
||||
system.cpu5: completed 60000 read, 32418 write accesses @17468540
|
||||
system.cpu2: completed 60000 read, 32981 write accesses @17554781
|
||||
system.cpu0: completed 70000 read, 37316 write accesses @19965899
|
||||
system.cpu7: completed 70000 read, 37727 write accesses @20108089
|
||||
system.cpu4: completed 70000 read, 37633 write accesses @20233790
|
||||
system.cpu1: completed 70000 read, 37821 write accesses @20289790
|
||||
system.cpu3: completed 70000 read, 37645 write accesses @20291829
|
||||
system.cpu6: completed 70000 read, 37499 write accesses @20304889
|
||||
system.cpu5: completed 70000 read, 37769 write accesses @20345680
|
||||
system.cpu2: completed 70000 read, 38246 write accesses @20384949
|
||||
system.cpu0: completed 80000 read, 42438 write accesses @22835499
|
||||
system.cpu7: completed 80000 read, 43085 write accesses @23031949
|
||||
system.cpu4: completed 80000 read, 42968 write accesses @23134444
|
||||
system.cpu3: completed 80000 read, 42908 write accesses @23138450
|
||||
system.cpu1: completed 80000 read, 43002 write accesses @23183439
|
||||
system.cpu6: completed 80000 read, 42955 write accesses @23224650
|
||||
system.cpu2: completed 80000 read, 43596 write accesses @23229730
|
||||
system.cpu5: completed 80000 read, 43242 write accesses @23231600
|
||||
system.cpu0: completed 90000 read, 47763 write accesses @25792220
|
||||
system.cpu7: completed 90000 read, 48675 write accesses @25948310
|
||||
system.cpu3: completed 90000 read, 48223 write accesses @26022110
|
||||
system.cpu4: completed 90000 read, 48406 write accesses @26054041
|
||||
system.cpu6: completed 90000 read, 48309 write accesses @26074843
|
||||
system.cpu2: completed 90000 read, 49141 write accesses @26106590
|
||||
system.cpu5: completed 90000 read, 48681 write accesses @26106730
|
||||
system.cpu1: completed 90000 read, 48449 write accesses @26117229
|
||||
system.cpu0: completed 100000 read, 53147 write accesses @28725020
|
||||
system.cpu0: completed 10000 read, 5375 write accesses @856398
|
||||
system.cpu7: completed 10000 read, 5367 write accesses @862743
|
||||
system.cpu4: completed 10000 read, 5441 write accesses @863378
|
||||
system.cpu5: completed 10000 read, 5493 write accesses @863384
|
||||
system.cpu6: completed 10000 read, 5390 write accesses @871145
|
||||
system.cpu2: completed 10000 read, 5481 write accesses @872080
|
||||
system.cpu3: completed 10000 read, 5307 write accesses @887641
|
||||
system.cpu1: completed 10000 read, 5435 write accesses @888236
|
||||
system.cpu0: completed 20000 read, 10720 write accesses @1697024
|
||||
system.cpu4: completed 20000 read, 10674 write accesses @1708688
|
||||
system.cpu2: completed 20000 read, 10679 write accesses @1718143
|
||||
system.cpu7: completed 20000 read, 10680 write accesses @1726961
|
||||
system.cpu5: completed 20000 read, 10844 write accesses @1731599
|
||||
system.cpu6: completed 20000 read, 10755 write accesses @1744688
|
||||
system.cpu1: completed 20000 read, 10834 write accesses @1760840
|
||||
system.cpu3: completed 20000 read, 10861 write accesses @1783274
|
||||
system.cpu0: completed 30000 read, 16096 write accesses @2576060
|
||||
system.cpu7: completed 30000 read, 16150 write accesses @2587892
|
||||
system.cpu2: completed 30000 read, 16059 write accesses @2589422
|
||||
system.cpu4: completed 30000 read, 16216 write accesses @2589611
|
||||
system.cpu5: completed 30000 read, 16311 write accesses @2606290
|
||||
system.cpu1: completed 30000 read, 16085 write accesses @2614280
|
||||
system.cpu6: completed 30000 read, 16250 write accesses @2617742
|
||||
system.cpu3: completed 30000 read, 16179 write accesses @2640821
|
||||
system.cpu0: completed 40000 read, 21491 write accesses @3463636
|
||||
system.cpu5: completed 40000 read, 21654 write accesses @3466586
|
||||
system.cpu4: completed 40000 read, 21608 write accesses @3466694
|
||||
system.cpu6: completed 40000 read, 21630 write accesses @3468467
|
||||
system.cpu2: completed 40000 read, 21509 write accesses @3470109
|
||||
system.cpu7: completed 40000 read, 21495 write accesses @3471086
|
||||
system.cpu1: completed 40000 read, 21461 write accesses @3476351
|
||||
system.cpu3: completed 40000 read, 21515 write accesses @3523754
|
||||
system.cpu4: completed 50000 read, 27063 write accesses @4330388
|
||||
system.cpu6: completed 50000 read, 27077 write accesses @4332246
|
||||
system.cpu5: completed 50000 read, 27022 write accesses @4334407
|
||||
system.cpu1: completed 50000 read, 26821 write accesses @4334861
|
||||
system.cpu2: completed 50000 read, 27005 write accesses @4339007
|
||||
system.cpu0: completed 50000 read, 27011 write accesses @4351000
|
||||
system.cpu7: completed 50000 read, 27023 write accesses @4371905
|
||||
system.cpu3: completed 50000 read, 26894 write accesses @4421954
|
||||
system.cpu6: completed 60000 read, 32380 write accesses @5185697
|
||||
system.cpu2: completed 60000 read, 32320 write accesses @5197049
|
||||
system.cpu1: completed 60000 read, 32167 write accesses @5197304
|
||||
system.cpu4: completed 60000 read, 32460 write accesses @5201909
|
||||
system.cpu5: completed 60000 read, 32453 write accesses @5222405
|
||||
system.cpu0: completed 60000 read, 32443 write accesses @5224148
|
||||
system.cpu7: completed 60000 read, 32400 write accesses @5229110
|
||||
system.cpu3: completed 60000 read, 32209 write accesses @5281507
|
||||
system.cpu6: completed 70000 read, 37664 write accesses @6045459
|
||||
system.cpu4: completed 70000 read, 37836 write accesses @6058226
|
||||
system.cpu1: completed 70000 read, 37476 write accesses @6063535
|
||||
system.cpu2: completed 70000 read, 37820 write accesses @6074654
|
||||
system.cpu5: completed 70000 read, 37785 write accesses @6097069
|
||||
system.cpu7: completed 70000 read, 37611 write accesses @6097865
|
||||
system.cpu0: completed 70000 read, 37769 write accesses @6104873
|
||||
system.cpu3: completed 70000 read, 37585 write accesses @6142157
|
||||
system.cpu4: completed 80000 read, 43086 write accesses @6914689
|
||||
system.cpu6: completed 80000 read, 42941 write accesses @6923107
|
||||
system.cpu1: completed 80000 read, 42761 write accesses @6929131
|
||||
system.cpu2: completed 80000 read, 43045 write accesses @6933740
|
||||
system.cpu5: completed 80000 read, 43067 write accesses @6962084
|
||||
system.cpu7: completed 80000 read, 43014 write accesses @6974408
|
||||
system.cpu0: completed 80000 read, 43066 write accesses @6974987
|
||||
system.cpu3: completed 80000 read, 43041 write accesses @7015199
|
||||
system.cpu4: completed 90000 read, 48630 write accesses @7775720
|
||||
system.cpu1: completed 90000 read, 48156 write accesses @7793810
|
||||
system.cpu6: completed 90000 read, 48441 write accesses @7801463
|
||||
system.cpu2: completed 90000 read, 48518 write accesses @7804520
|
||||
system.cpu5: completed 90000 read, 48378 write accesses @7834475
|
||||
system.cpu0: completed 90000 read, 48500 write accesses @7849400
|
||||
system.cpu7: completed 90000 read, 48425 write accesses @7864016
|
||||
system.cpu3: completed 90000 read, 48443 write accesses @7889702
|
||||
system.cpu4: completed 100000 read, 54108 write accesses @8642753
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 10 2012 16:32:12
|
||||
gem5 started Jul 10 2012 17:27:35
|
||||
gem5 executing on sc2b0605
|
||||
gem5 compiled Sep 1 2012 13:41:29
|
||||
gem5 started Sep 1 2012 13:47:40
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 28725020 because maximum number of loads reached
|
||||
Exiting @ tick 8642753 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.028725 # Number of seconds simulated
|
||||
sim_ticks 28725020 # Number of ticks simulated
|
||||
final_tick 28725020 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.008643 # Number of seconds simulated
|
||||
sim_ticks 8642753 # Number of ticks simulated
|
||||
final_tick 8642753 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 477176 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 379424 # Number of bytes of host memory used
|
||||
host_seconds 60.20 # Real time elapsed on the host
|
||||
host_tick_rate 200801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409268 # Number of bytes of host memory used
|
||||
host_seconds 43.04 # Real time elapsed on the host
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0
|
|||
system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53147 # number of write accesses completed
|
||||
system.cpu0.num_reads 99336 # number of read accesses completed
|
||||
system.cpu0.num_writes 53454 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99027 # number of read accesses completed
|
||||
system.cpu1.num_writes 53354 # number of write accesses completed
|
||||
system.cpu1.num_reads 99686 # number of read accesses completed
|
||||
system.cpu1.num_writes 53261 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98992 # number of read accesses completed
|
||||
system.cpu2.num_writes 53956 # number of write accesses completed
|
||||
system.cpu2.num_reads 99694 # number of read accesses completed
|
||||
system.cpu2.num_writes 53721 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99374 # number of read accesses completed
|
||||
system.cpu3.num_writes 53181 # number of write accesses completed
|
||||
system.cpu3.num_reads 98699 # number of read accesses completed
|
||||
system.cpu3.num_writes 53080 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99392 # number of read accesses completed
|
||||
system.cpu4.num_writes 53489 # number of write accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 54108 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99177 # number of read accesses completed
|
||||
system.cpu5.num_writes 53605 # number of write accesses completed
|
||||
system.cpu5.num_reads 99065 # number of read accesses completed
|
||||
system.cpu5.num_writes 53284 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99055 # number of read accesses completed
|
||||
system.cpu6.num_writes 53188 # number of write accesses completed
|
||||
system.cpu6.num_reads 99678 # number of read accesses completed
|
||||
system.cpu6.num_writes 53683 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99520 # number of read accesses completed
|
||||
system.cpu7.num_writes 53821 # number of write accesses completed
|
||||
system.cpu7.num_reads 98986 # number of read accesses completed
|
||||
system.cpu7.num_writes 53291 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -57,9 +58,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -68,6 +69,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -121,6 +123,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -165,6 +168,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -289,6 +293,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
@ -302,6 +307,7 @@ slave=system.system_port
|
|||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
clock=1
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:34:42
|
||||
Real time: Sep/01/2012 14:05:06
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.58
|
||||
Virtual_time_in_minutes: 0.00966667
|
||||
Virtual_time_in_hours: 0.000161111
|
||||
Virtual_time_in_days: 6.71296e-06
|
||||
Virtual_time_in_seconds: 0.52
|
||||
Virtual_time_in_minutes: 0.00866667
|
||||
Virtual_time_in_hours: 0.000144444
|
||||
Virtual_time_in_days: 6.01852e-06
|
||||
|
||||
Ruby_current_time: 349711
|
||||
Ruby_current_time: 318321
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 349711
|
||||
Ruby_cycles: 318321
|
||||
|
||||
mbytes_resident: 41.8008
|
||||
mbytes_total: 225.551
|
||||
resident_ratio: 0.185362
|
||||
mbytes_resident: 44.9961
|
||||
mbytes_total: 254.652
|
||||
resident_ratio: 0.176758
|
||||
|
||||
ruby_cycles_executed: [ 349712 ]
|
||||
ruby_cycles_executed: [ 318322 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -30,15 +30,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 994 average: 15.841 | standard deviation: 1.12331 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 39 941 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1012 average: 15.8221 | standard deviation: 1.11991 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 61 937 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 8736 count: 979 average: 5661.07 | standard deviation: 2367.21 | 72 10 0 0 2 2 5 2 5 4 6 8 4 7 3 2 4 3 2 4 3 1 1 1 0 1 1 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 21 27 27 32 32 32 39 32 43 26 27 28 36 34 35 22 24 33 26 22 19 22 17 14 7 2 16 6 5 11 5 4 3 3 1 2 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 8339 count: 44 average: 6147 | standard deviation: 2036.5 | 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 1 1 4 4 1 1 3 2 0 2 1 1 0 3 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8736 count: 879 average: 5937.77 | standard deviation: 2125.68 | 69 9 0 0 2 0 3 2 2 0 3 0 1 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 19 25 25 31 31 31 38 28 39 25 26 25 34 34 33 21 23 33 23 21 18 21 17 13 7 2 16 5 5 11 5 3 3 3 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 1853 count: 56 average: 936.107 | standard deviation: 353.831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 2 0 0 0 0 0 1 0 2 0 0 1 1 2 3 0 0 0 2 0 4 2 0 1 1 1 0 4 1 0 1 0 1 1 1 1 0 0 2 2 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 64 max: 8736 count: 979 average: 5661.07 | standard deviation: 2367.21 | 72 10 0 0 2 2 5 2 5 4 6 8 4 7 3 2 4 3 2 4 3 1 1 1 0 1 1 0 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 21 27 27 32 32 32 39 32 43 26 27 28 36 34 35 22 24 33 26 22 19 22 17 14 7 2 16 6 5 11 5 4 3 3 1 2 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 8110 count: 997 average: 5056.15 | standard deviation: 2131.53 | 69 13 4 2 1 6 6 4 4 1 8 8 6 5 0 3 0 1 1 1 2 3 2 3 0 0 3 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 1 0 1 3 0 3 1 5 8 11 8 16 15 20 29 26 21 24 31 17 30 34 34 27 28 36 25 28 32 33 35 28 34 17 19 21 21 16 13 13 11 7 3 6 6 8 3 2 2 4 2 2 1 0 3 1 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 7764 count: 44 average: 5504.89 | standard deviation: 1648.56 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 2 0 1 3 1 1 1 2 1 0 0 3 3 0 2 1 1 1 3 1 2 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8110 count: 897 average: 5296.67 | standard deviation: 1932.9 | 66 13 3 2 0 3 1 2 2 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 1 0 1 2 0 3 1 4 7 11 7 15 15 19 27 26 20 21 30 16 29 32 33 27 28 33 22 28 30 32 34 27 31 16 17 20 21 15 12 13 11 7 2 6 6 8 3 2 1 4 2 2 1 0 2 1 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 2 0 3 0 1 1 0 1 0 1 0 0 2 0 0 1 0 0 2 3 1 1 2 0 3 3 1 1 2 2 0 0 3 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 64 max: 8110 count: 997 average: 5056.15 | standard deviation: 2131.53 | 69 13 4 2 1 6 6 4 4 1 8 8 6 5 0 3 0 1 1 1 2 3 2 3 0 0 3 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 1 0 1 3 0 3 1 5 8 11 8 16 15 20 29 26 21 24 31 17 30 34 34 27 28 36 25 28 32 33 35 28 34 17 19 21 21 16 13 13 11 7 3 6 6 8 3 2 2 4 2 2 1 0 3 1 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 64 max: 8339 count: 44 average: 6147 | standard deviation: 2036.5 | 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 1 1 1 1 4 4 1 1 3 2 0 2 1 1 0 3 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 64 max: 8736 count: 879 average: 5937.77 | standard deviation: 2125.68 | 69 9 0 0 2 0 3 2 2 0 3 0 1 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 1 1 2 8 4 5 9 6 8 9 19 19 25 25 31 31 31 38 28 39 25 26 25 34 34 33 21 23 33 23 21 18 21 17 13 7 2 16 5 5 11 5 3 3 3 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 1853 count: 56 average: 936.107 | standard deviation: 353.831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 2 0 0 0 0 0 1 0 2 0 0 1 1 2 3 0 0 0 2 0 4 2 0 1 1 1 0 4 1 0 1 0 1 1 1 1 0 0 2 2 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 64 max: 7764 count: 44 average: 5504.89 | standard deviation: 1648.56 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 2 0 1 3 1 1 1 2 1 0 0 3 3 0 2 1 1 1 3 1 2 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 64 max: 8110 count: 897 average: 5296.67 | standard deviation: 1932.9 | 66 13 3 2 0 3 1 2 2 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 1 0 1 2 0 3 1 4 7 11 7 15 15 19 27 26 20 21 30 16 29 32 33 27 28 33 22 28 30 32 34 27 31 16 17 20 21 15 12 13 11 7 2 6 6 8 3 2 1 4 2 2 1 0 2 1 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 2 0 3 0 1 1 0 1 0 1 0 0 2 0 0 1 0 0 2 3 1 1 2 0 3 3 1 1 2 2 0 0 3 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -65,11 +65,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 64 max: 1964 count: 6930 average: 44.9837 | standard deviation: 177.937 | 6277 162 19 77 35 23 39 25 31 46 31 47 16 29 20 14 5 2 2 5 1 3 4 7 1 3 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 10 count: 4452 average: 0.269093 | standard deviation: 0.946561 | 4000 119 113 132 37 23 14 8 1 4 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 1964 count: 2478 average: 125.318 | standard deviation: 280.209 | 1825 162 19 77 35 23 39 25 31 46 31 47 16 29 20 14 5 2 2 5 1 3 4 7 1 3 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 10 count: 3903 average: 0.282603 | standard deviation: 0.959989 | 3479 115 110 122 32 19 13 8 1 3 1 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 549 average: 0.173042 | standard deviation: 0.84036 | 521 4 3 10 5 4 1 0 0 1 ]
|
||||
Total_delay_cycles: [binsize: 32 max: 1572 count: 7069 average: 39.9154 | standard deviation: 159.247 | 6421 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 11 count: 4539 average: 0.320996 | standard deviation: 1.03402 | 3993 136 158 137 52 29 15 8 6 4 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 32 max: 1572 count: 2530 average: 110.951 | standard deviation: 251.02 | 1882 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 3976 average: 0.342807 | standard deviation: 1.04899 | 3455 133 152 135 45 25 14 8 5 4 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 11 count: 563 average: 0.166963 | standard deviation: 0.907658 | 538 3 6 2 7 4 1 0 1 0 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -83,83 +83,83 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11853
|
||||
page_reclaims: 8497
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 5280 42240
|
||||
total_msg_count_Request_Control: 1647 13176
|
||||
total_msg_count_Response_Data: 7584 546048
|
||||
total_msg_count_Response_Control: 7733 61864
|
||||
total_msg_count_Writeback_Data: 3603 259416
|
||||
total_msg_count_Writeback_Control: 108 864
|
||||
total_msgs: 25955 total_bytes: 923608
|
||||
total_msg_count_Control: 5373 42984
|
||||
total_msg_count_Request_Control: 1689 13512
|
||||
total_msg_count_Response_Data: 7724 556128
|
||||
total_msg_count_Response_Control: 7854 62832
|
||||
total_msg_count_Writeback_Data: 3705 266760
|
||||
total_msg_count_Writeback_Control: 102 816
|
||||
total_msgs: 26447 total_bytes: 943032
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.57251
|
||||
links_utilized_percent_switch_0_link_0: 1.33853 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.80649 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 1.76936
|
||||
links_utilized_percent_switch_0_link_0: 1.50069 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.03804 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 740 5920 [ 0 740 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 892 7136 [ 0 52 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 563 4504 [ 563 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 915 65880 [ 0 915 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 756 6048 [ 0 756 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 917 7336 [ 917 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 909 7272 [ 0 50 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1235 88920 [ 722 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 34 272 [ 34 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.75106
|
||||
links_utilized_percent_switch_1_link_0: 3.03694 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.46518 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 3.08541
|
||||
links_utilized_percent_switch_1_link_0: 3.40851 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.76231 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1749 13992 [ 0 909 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1667 120024 [ 0 1667 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 828 6624 [ 0 828 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 917 7336 [ 917 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 873 62856 [ 0 873 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1777 14216 [ 0 919 858 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1235 88920 [ 722 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 34 272 [ 34 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 874 6992 [ 874 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 563 4504 [ 563 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1701 122472 [ 0 1701 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 840 6720 [ 0 840 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.17862
|
||||
links_utilized_percent_switch_2_link_0: 1.12664 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.23059 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.31691
|
||||
links_utilized_percent_switch_2_link_0: 1.26162 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.3722 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 770 55440 [ 0 770 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 88 704 [ 0 88 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 858 6864 [ 0 858 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 874 6992 [ 874 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 874 62928 [ 0 874 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.83409
|
||||
links_utilized_percent_switch_3_link_0: 1.33853 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.03708 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.12664 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 2.05746
|
||||
links_utilized_percent_switch_3_link_0: 1.50069 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 3.41008 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.26162 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 740 5920 [ 0 740 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 861 61992 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1750 14000 [ 0 910 840 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1201 86472 [ 704 497 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 36 288 [ 36 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 770 55440 [ 0 770 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 88 704 [ 0 88 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 563 4504 [ 563 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 915 65880 [ 0 915 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 756 6048 [ 0 756 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 917 7336 [ 917 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 874 62928 [ 0 874 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1778 14224 [ 0 920 858 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1235 88920 [ 722 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 34 272 [ 34 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 874 6992 [ 874 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 56
|
||||
|
|
@ -173,39 +173,39 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 56 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 842
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 842
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 861
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 861
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.86936%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.1306%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.87805%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.122%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 842 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 861 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [45 ] 45
|
||||
Ifetch [62 ] 62
|
||||
Store [879 ] 879
|
||||
Inv [549 ] 549
|
||||
L1_Replacement [10481 ] 10481
|
||||
Load [44 ] 44
|
||||
Ifetch [67 ] 67
|
||||
Store [898 ] 898
|
||||
Inv [563 ] 563
|
||||
L1_Replacement [10398 ] 10398
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [40 ] 40
|
||||
Data_Exclusive [41 ] 41
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [857 ] 857
|
||||
Data_all_Acks [874 ] 874
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [740 ] 740
|
||||
Ack_all [1 ] 1
|
||||
WB_Ack [755 ] 755
|
||||
|
||||
- Transitions -
|
||||
NP Load [41 ] 41
|
||||
NP Load [42 ] 42
|
||||
NP Ifetch [56 ] 56
|
||||
NP Store [801 ] 801
|
||||
NP Store [818 ] 818
|
||||
NP Inv [1 ] 1
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
|
|
@ -213,28 +213,28 @@ I Load [0 ] 0
|
|||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [146 ] 146
|
||||
I L1_Replacement [145 ] 145
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Inv [27 ] 27
|
||||
S L1_Replacement [7 ] 7
|
||||
S Store [1 ] 1
|
||||
S Inv [31 ] 31
|
||||
S L1_Replacement [11 ] 11
|
||||
|
||||
E Load [0 ] 0
|
||||
E Ifetch [0 ] 0
|
||||
E Store [1 ] 1
|
||||
E Inv [2 ] 2
|
||||
E L1_Replacement [36 ] 36
|
||||
E Store [2 ] 2
|
||||
E Inv [4 ] 4
|
||||
E L1_Replacement [34 ] 34
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
M Load [4 ] 4
|
||||
M Load [2 ] 2
|
||||
M Ifetch [0 ] 0
|
||||
M Store [77 ] 77
|
||||
M Inv [97 ] 97
|
||||
M L1_Replacement [704 ] 704
|
||||
M L1_Replacement [722 ] 722
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
|
@ -242,19 +242,19 @@ M Fwd_GET_INSTR [0 ] 0
|
|||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [22 ] 22
|
||||
IS L1_Replacement [508 ] 508
|
||||
IS Data_Exclusive [40 ] 40
|
||||
IS Inv [14 ] 14
|
||||
IS L1_Replacement [374 ] 374
|
||||
IS Data_Exclusive [41 ] 41
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [34 ] 34
|
||||
IS Data_all_Acks [43 ] 43
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [9080 ] 9080
|
||||
IM L1_Replacement [9112 ] 9112
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [801 ] 801
|
||||
IM Data_all_Acks [817 ] 817
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -263,7 +263,7 @@ SM Store [0 ] 0
|
|||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
SM Ack_all [1 ] 1
|
||||
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
|
|
@ -272,12 +272,12 @@ IS_I Inv [0 ] 0
|
|||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [22 ] 22
|
||||
IS_I Data_all_Acks [14 ] 14
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [6 ] 6
|
||||
M_I Ifetch [10 ] 10
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [400 ] 400
|
||||
M_I Inv [416 ] 416
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
|
|
@ -285,73 +285,73 @@ M_I Fwd_GET_INSTR [0 ] 0
|
|||
M_I WB_Ack [340 ] 340
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Ifetch [1 ] 1
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [400 ] 400
|
||||
SINK_WB_ACK WB_Ack [415 ] 415
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 862
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 862
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 874
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 874
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.75638%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 5.80046%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4432%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.69108%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 5.26316%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.0458%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 862 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 874 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [56 ] 56
|
||||
L1_GETS [41 ] 41
|
||||
L1_GETX [801 ] 801
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [349 ] 349
|
||||
L1_PUTX_old [757 ] 757
|
||||
L1_GETS [42 ] 42
|
||||
L1_GETX [818 ] 818
|
||||
L1_UPGRADE [1 ] 1
|
||||
L1_PUTX [345 ] 345
|
||||
L1_PUTX_old [796 ] 796
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [297 ] 297
|
||||
L2_Replacement_clean [1183 ] 1183
|
||||
Mem_Data [861 ] 861
|
||||
Mem_Ack [856 ] 856
|
||||
WB_Data [473 ] 473
|
||||
WB_Data_clean [24 ] 24
|
||||
L2_Replacement [291 ] 291
|
||||
L2_Replacement_clean [1216 ] 1216
|
||||
Mem_Data [873 ] 873
|
||||
Mem_Ack [869 ] 869
|
||||
WB_Data [495 ] 495
|
||||
WB_Data_clean [18 ] 18
|
||||
Ack [0 ] 0
|
||||
Ack_all [52 ] 52
|
||||
Ack_all [50 ] 50
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [840 ] 840
|
||||
Exclusive_Unblock [858 ] 858
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [50 ] 50
|
||||
NP L1_GET_INSTR [46 ] 46
|
||||
NP L1_GETS [41 ] 41
|
||||
NP L1_GETX [771 ] 771
|
||||
NP L1_GETX [787 ] 787
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [264 ] 264
|
||||
NP L1_PUTX_old [302 ] 302
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [6 ] 6
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_GETS [1 ] 1
|
||||
SS L1_GETX [9 ] 9
|
||||
SS L1_UPGRADE [1 ] 1
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [50 ] 50
|
||||
SS L2_Replacement_clean [46 ] 46
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [6 ] 6
|
||||
M L1_GET_INSTR [10 ] 10
|
||||
M L1_GETS [0 ] 0
|
||||
M L1_GETX [24 ] 24
|
||||
M L1_GETX [22 ] 22
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [297 ] 297
|
||||
M L2_Replacement_clean [12 ] 12
|
||||
M L2_Replacement [291 ] 291
|
||||
M L2_Replacement_clean [16 ] 16
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -360,7 +360,7 @@ MT L1_GETX [0 ] 0
|
|||
MT L1_PUTX [340 ] 340
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L2_Replacement_clean [499 ] 499
|
||||
MT L2_Replacement_clean [517 ] 517
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -368,8 +368,8 @@ M_I L1_GETS [0 ] 0
|
|||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [136 ] 136
|
||||
M_I Mem_Ack [856 ] 856
|
||||
M_I L1_PUTX_old [113 ] 113
|
||||
M_I Mem_Ack [869 ] 869
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -388,10 +388,10 @@ MCT_I L1_GETS [0 ] 0
|
|||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [181 ] 181
|
||||
MCT_I WB_Data [473 ] 473
|
||||
MCT_I WB_Data_clean [24 ] 24
|
||||
MCT_I Ack_all [2 ] 2
|
||||
MCT_I L1_PUTX_old [210 ] 210
|
||||
MCT_I WB_Data [495 ] 495
|
||||
MCT_I WB_Data_clean [18 ] 18
|
||||
MCT_I Ack_all [4 ] 4
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
|
|
@ -400,7 +400,7 @@ I_I L1_UPGRADE [0 ] 0
|
|||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [50 ] 50
|
||||
I_I Ack_all [46 ] 46
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
|
|
@ -418,8 +418,8 @@ ISS L1_GETX [0 ] 0
|
|||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [14 ] 14
|
||||
ISS Mem_Data [40 ] 40
|
||||
ISS L2_Replacement_clean [11 ] 11
|
||||
ISS Mem_Data [41 ] 41
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -428,8 +428,8 @@ IS L1_GETX [0 ] 0
|
|||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [69 ] 69
|
||||
IS Mem_Data [50 ] 50
|
||||
IS L2_Replacement_clean [57 ] 57
|
||||
IS Mem_Data [46 ] 46
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -438,8 +438,8 @@ IM L1_GETX [0 ] 0
|
|||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [225 ] 225
|
||||
IM Mem_Data [771 ] 771
|
||||
IM L2_Replacement_clean [219 ] 219
|
||||
IM Mem_Data [786 ] 786
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -451,19 +451,19 @@ SS_MB L1_PUTX_old [0 ] 0
|
|||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [6 ] 6
|
||||
SS_MB Exclusive_Unblock [10 ] 10
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [9 ] 9
|
||||
MT_MB L1_PUTX_old [176 ] 176
|
||||
MT_MB L1_PUTX [5 ] 5
|
||||
MT_MB L1_PUTX_old [171 ] 171
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [314 ] 314
|
||||
MT_MB L2_Replacement_clean [350 ] 350
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [834 ] 834
|
||||
MT_MB Exclusive_Unblock [848 ] 848
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -515,37 +515,37 @@ MT_SB Unblock [0 ] 0
|
|||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1632
|
||||
memory_reads: 861
|
||||
memory_writes: 770
|
||||
memory_refreshes: 729
|
||||
memory_total_request_delays: 1043
|
||||
memory_delays_per_request: 0.639093
|
||||
memory_delays_in_input_queue: 147
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 896
|
||||
memory_stalls_for_bank_busy: 170
|
||||
memory_total_requests: 1660
|
||||
memory_reads: 874
|
||||
memory_writes: 786
|
||||
memory_refreshes: 2210
|
||||
memory_total_request_delays: 601
|
||||
memory_delays_per_request: 0.362048
|
||||
memory_delays_in_input_queue: 44
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 555
|
||||
memory_stalls_for_bank_busy: 169
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 70
|
||||
memory_stalls_for_bus: 355
|
||||
memory_stalls_for_arbitration: 30
|
||||
memory_stalls_for_bus: 188
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 230
|
||||
memory_stalls_for_read_read_turnaround: 71
|
||||
accesses_per_bank: 59 40 48 77 75 69 65 47 55 56 48 54 65 48 34 60 44 35 56 37 49 41 46 49 50 48 50 47 58 40 41 41
|
||||
memory_stalls_for_read_write_turnaround: 104
|
||||
memory_stalls_for_read_read_turnaround: 64
|
||||
accesses_per_bank: 42 51 50 73 73 71 65 49 54 41 50 44 58 48 47 63 57 47 58 57 41 49 46 49 57 45 42 49 45 53 48 38
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [862 ] 862
|
||||
Data [770 ] 770
|
||||
Memory_Data [861 ] 861
|
||||
Memory_Ack [770 ] 770
|
||||
Fetch [874 ] 874
|
||||
Data [786 ] 786
|
||||
Memory_Data [874 ] 874
|
||||
Memory_Ack [786 ] 786
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [88 ] 88
|
||||
CleanReplacement [84 ] 84
|
||||
|
||||
- Transitions -
|
||||
I Fetch [862 ] 862
|
||||
I Fetch [874 ] 874
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -561,20 +561,20 @@ ID_W Memory_Ack [0 ] 0
|
|||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [770 ] 770
|
||||
M Data [786 ] 786
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [88 ] 88
|
||||
M CleanReplacement [84 ] 84
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [861 ] 861
|
||||
IM Memory_Data [874 ] 874
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [770 ] 770
|
||||
MI Memory_Ack [786 ] 786
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:30:15
|
||||
gem5 started Jul 28 2012 11:35:50
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:01:54
|
||||
gem5 started Sep 1 2012 14:05:06
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 349711 because Ruby Tester completed
|
||||
Exiting @ tick 318321 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000350 # Number of seconds simulated
|
||||
sim_ticks 349711 # Number of ticks simulated
|
||||
final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000318 # Number of seconds simulated
|
||||
sim_ticks 318321 # Number of ticks simulated
|
||||
final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 2474351 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229272 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1505639 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260768 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -56,9 +57,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -67,6 +68,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -118,6 +120,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -161,6 +164,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -285,6 +289,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
@ -298,6 +303,7 @@ slave=system.system_port
|
|||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
clock=1
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
|
|
|
|||
|
|
@ -1,26 +1,26 @@
|
|||
Real time: Jul/10/2012 17:44:41
|
||||
Real time: Sep/01/2012 14:14:50
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 1.08
|
||||
Virtual_time_in_minutes: 0.018
|
||||
Virtual_time_in_hours: 0.0003
|
||||
Virtual_time_in_days: 1.25e-05
|
||||
Virtual_time_in_seconds: 0.83
|
||||
Virtual_time_in_minutes: 0.0138333
|
||||
Virtual_time_in_hours: 0.000230556
|
||||
Virtual_time_in_days: 9.60648e-06
|
||||
|
||||
Ruby_current_time: 357561
|
||||
Ruby_current_time: 316521
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 357561
|
||||
Ruby_cycles: 316521
|
||||
|
||||
mbytes_resident: 41.8789
|
||||
mbytes_total: 225.645
|
||||
resident_ratio: 0.185631
|
||||
mbytes_resident: 44.0977
|
||||
mbytes_total: 254.852
|
||||
resident_ratio: 0.173094
|
||||
|
||||
ruby_cycles_executed: [ 357562 ]
|
||||
ruby_cycles_executed: [ 316522 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L2Cache-0:0
|
||||
|
|
@ -30,15 +30,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 959 average: 15.8321 | standard deviation: 1.14411 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 42 903 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 977 average: 15.825 | standard deviation: 1.13712 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 52 911 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 35755 count: 944 average: 5943.47 | standard deviation: 8648.87 | 80 45 92 101 84 54 37 40 29 42 18 14 12 10 11 11 4 10 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 5 2 1 1 4 1 8 4 3 6 6 6 2 4 10 4 6 2 5 3 3 3 1 4 5 3 3 4 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 1 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 256 max: 32625 count: 44 average: 6010.95 | standard deviation: 9060.42 | 5 4 0 9 2 5 2 0 2 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 256 max: 35755 count: 844 average: 6286.24 | standard deviation: 8806.66 | 73 32 69 78 75 48 35 40 27 40 18 13 12 10 11 11 4 8 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 4 2 1 1 4 1 8 3 3 5 6 6 2 4 9 4 6 2 4 3 2 2 1 4 5 3 3 2 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1342 count: 56 average: 724.5 | standard deviation: 266.653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 1 1 0 0 0 0 2 2 4 1 0 0 1 1 0 0 1 1 0 0 2 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_NULL: [binsize: 256 max: 35755 count: 944 average: 5943.47 | standard deviation: 8648.87 | 80 45 92 101 84 54 37 40 29 42 18 14 12 10 11 11 4 10 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 5 2 1 1 4 1 8 4 3 6 6 6 2 4 10 4 6 2 5 3 3 3 1 4 5 3 3 4 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 1 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 256 max: 34293 count: 962 average: 5083.18 | standard deviation: 7651.66 | 97 58 107 114 62 59 47 32 38 24 25 15 18 13 6 9 6 5 2 4 5 3 3 2 2 2 1 0 0 2 2 2 1 2 3 1 2 2 1 2 0 0 2 1 1 2 3 0 3 2 1 0 2 1 2 5 3 4 3 2 3 2 2 4 3 3 10 3 2 5 4 1 8 2 6 4 5 4 4 2 1 1 2 4 3 2 4 0 2 1 6 0 3 3 1 1 1 3 6 1 1 0 1 2 0 0 0 1 1 1 0 1 6 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 25205 count: 44 average: 5768.3 | standard deviation: 8418.68 | 7 0 1 1 0 0 6 2 3 1 0 0 2 3 0 1 0 0 2 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 ]
|
||||
miss_latency_ST: [binsize: 256 max: 34293 count: 862 average: 5340.56 | standard deviation: 7771.5 | 84 40 83 99 56 58 42 31 38 22 24 14 17 12 6 9 6 5 2 4 5 3 3 2 2 2 1 0 0 2 2 2 1 2 2 1 2 2 1 2 0 0 2 1 1 2 3 0 3 2 1 0 2 1 2 5 3 4 3 2 1 1 2 4 3 3 10 3 2 5 4 1 7 2 6 4 5 4 3 2 1 1 2 4 3 2 3 0 2 1 5 0 3 3 1 0 1 3 4 1 1 0 1 2 0 0 0 1 1 1 0 1 6 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1374 count: 56 average: 583.107 | standard deviation: 267.301 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 1 2 0 0 0 0 0 1 0 1 0 0 2 1 1 1 0 2 0 1 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 1 1 3 3 1 2 2 1 0 1 0 0 0 0 0 2 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 256 max: 34293 count: 962 average: 5083.18 | standard deviation: 7651.66 | 97 58 107 114 62 59 47 32 38 24 25 15 18 13 6 9 6 5 2 4 5 3 3 2 2 2 1 0 0 2 2 2 1 2 3 1 2 2 1 2 0 0 2 1 1 2 3 0 3 2 1 0 2 1 2 5 3 4 3 2 3 2 2 4 3 3 10 3 2 5 4 1 8 2 6 4 5 4 4 2 1 1 2 4 3 2 4 0 2 1 6 0 3 3 1 1 1 3 6 1 1 0 1 2 0 0 0 1 1 1 0 1 6 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -49,9 +49,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 256 max: 32625 count: 44 average: 6010.95 | standard deviation: 9060.42 | 5 4 0 9 2 5 2 0 2 2 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 256 max: 35755 count: 844 average: 6286.24 | standard deviation: 8806.66 | 73 32 69 78 75 48 35 40 27 40 18 13 12 10 11 11 4 8 2 6 6 0 1 3 5 3 4 3 0 5 2 1 4 4 1 1 1 1 2 2 2 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 2 1 0 1 1 1 2 1 5 4 2 1 1 4 1 8 3 3 5 6 6 2 4 9 4 6 2 4 3 2 2 1 4 5 3 3 2 4 1 3 0 2 2 0 6 4 3 1 1 0 1 2 5 0 2 1 1 2 0 0 3 2 0 3 2 1 2 0 1 1 1 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 8 max: 1342 count: 56 average: 724.5 | standard deviation: 266.653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 1 1 0 0 0 0 2 2 4 1 0 0 1 1 0 0 1 1 0 0 2 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_NULL: [binsize: 128 max: 25205 count: 44 average: 5768.3 | standard deviation: 8418.68 | 7 0 1 1 0 0 6 2 3 1 0 0 2 3 0 1 0 0 2 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 ]
|
||||
miss_latency_ST_NULL: [binsize: 256 max: 34293 count: 862 average: 5340.56 | standard deviation: 7771.5 | 84 40 83 99 56 58 42 31 38 22 24 14 17 12 6 9 6 5 2 4 5 3 3 2 2 2 1 0 0 2 2 2 1 2 2 1 2 2 1 2 0 0 2 1 1 2 3 0 3 2 1 0 2 1 2 5 3 4 3 2 1 1 2 4 3 3 10 3 2 5 4 1 7 2 6 4 5 4 3 2 1 1 2 4 3 2 3 0 2 1 5 0 3 3 1 0 1 3 4 1 1 0 1 2 0 0 0 1 1 1 0 1 6 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 8 max: 1374 count: 56 average: 583.107 | standard deviation: 267.301 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 1 2 0 0 0 0 0 1 0 1 0 0 2 1 1 1 0 2 0 1 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 1 1 3 3 1 2 2 1 0 1 0 0 0 0 0 2 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -81,89 +81,89 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 1
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11882
|
||||
page_reclaims: 8272
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5082 40656
|
||||
total_msg_count_Response_Data: 4932 355104
|
||||
total_msg_count_ResponseL2hit_Data: 138 9936
|
||||
total_msg_count_Writeback_Data: 4785 344520
|
||||
total_msg_count_Writeback_Control: 10307 82456
|
||||
total_msg_count_Unblock_Control: 5058 40464
|
||||
total_msgs: 30302 total_bytes: 873136
|
||||
total_msg_count_Request_Control: 5112 40896
|
||||
total_msg_count_Response_Data: 4992 359424
|
||||
total_msg_count_ResponseL2hit_Data: 120 8640
|
||||
total_msg_count_Writeback_Data: 4839 348408
|
||||
total_msg_count_Writeback_Control: 10370 82960
|
||||
total_msg_count_Unblock_Control: 5107 40856
|
||||
total_msgs: 30540 total_bytes: 881184
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.54369
|
||||
links_utilized_percent_switch_0_link_0: 2.59676 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.49062 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.89997
|
||||
links_utilized_percent_switch_0_link_0: 2.95778 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.84215 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1678 13424 [ 865 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 1758 14064 [ 865 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 872 6976 [ 872 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 867 62424 [ 0 0 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1690 13520 [ 867 823 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Unblock_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 832 6656 [ 0 832 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 40 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 746 53712 [ 0 0 746 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 1767 14136 [ 867 824 76 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 831 6648 [ 0 0 831 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.33089
|
||||
links_utilized_percent_switch_1_link_0: 1.21322 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.44856 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 1.51096
|
||||
links_utilized_percent_switch_1_link_0: 1.37669 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.64523 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 864 6912 [ 864 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 865 6920 [ 865 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 40 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 872 6976 [ 872 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 867 62424 [ 0 0 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 868 6944 [ 868 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 872 6976 [ 0 0 872 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.21273
|
||||
links_utilized_percent_switch_2_link_0: 1.27726 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.1482 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.38901
|
||||
links_utilized_percent_switch_2_link_0: 1.46515 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.31287 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 893 7144 [ 0 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 813 6504 [ 0 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 832 6656 [ 0 832 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 746 53712 [ 0 0 746 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 899 7192 [ 0 823 76 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 830 6640 [ 0 0 830 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 823 6584 [ 0 823 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.69579
|
||||
links_utilized_percent_switch_3_link_0: 2.59676 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.21336 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.27726 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 1.93331
|
||||
links_utilized_percent_switch_3_link_0: 2.95794 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 1.37669 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.46531 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 870 6960 [ 870 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 862 62064 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1678 13424 [ 865 813 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Unblock_Control: 866 6928 [ 0 0 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 822 59184 [ 0 0 822 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 865 6920 [ 865 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 824 6592 [ 0 824 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 733 52776 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 893 7144 [ 0 813 80 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 820 6560 [ 0 0 820 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 872 6976 [ 872 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 867 62424 [ 0 0 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1690 13520 [ 867 823 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Unblock_Control: 872 6976 [ 0 0 872 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 832 59904 [ 0 0 832 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 40 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 832 6656 [ 0 832 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 746 53712 [ 0 0 746 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 899 7192 [ 0 823 76 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 831 6648 [ 0 0 831 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
|
|
@ -183,10 +183,10 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [47 ] 47
|
||||
Ifetch [318 ] 318
|
||||
Store [964 ] 964
|
||||
L1_Replacement [506921 ] 506921
|
||||
Load [44 ] 44
|
||||
Ifetch [204 ] 204
|
||||
Store [1039 ] 1039
|
||||
L1_Replacement [449881 ] 449881
|
||||
Own_GETX [0 ] 0
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
|
|
@ -194,17 +194,17 @@ Fwd_DMA [0 ] 0
|
|||
Inv [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Exclusive_Data [868 ] 868
|
||||
Exclusive_Data [872 ] 872
|
||||
Writeback_Ack [0 ] 0
|
||||
Writeback_Ack_Data [864 ] 864
|
||||
Writeback_Ack_Data [867 ] 867
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [772 ] 772
|
||||
Use_Timeout [866 ] 866
|
||||
All_acks [782 ] 782
|
||||
Use_Timeout [870 ] 870
|
||||
|
||||
- Transitions -
|
||||
I Load [41 ] 41
|
||||
I Ifetch [56 ] 56
|
||||
I Store [773 ] 773
|
||||
I Load [37 ] 37
|
||||
I Ifetch [53 ] 53
|
||||
I Store [783 ] 783
|
||||
I L1_Replacement [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
|
||||
|
|
@ -225,28 +225,28 @@ O Fwd_GETS [0 ] 0
|
|||
O Fwd_DMA [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Ifetch [3 ] 3
|
||||
M Store [0 ] 0
|
||||
M L1_Replacement [94 ] 94
|
||||
M L1_Replacement [88 ] 88
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_DMA [0 ] 0
|
||||
|
||||
M_W Load [1 ] 1
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L1_Replacement [1321 ] 1321
|
||||
M_W L1_Replacement [1690 ] 1690
|
||||
M_W Own_GETX [0 ] 0
|
||||
M_W Fwd_GETX [0 ] 0
|
||||
M_W Fwd_GETS [0 ] 0
|
||||
M_W Fwd_DMA [0 ] 0
|
||||
M_W Inv [0 ] 0
|
||||
M_W Use_Timeout [94 ] 94
|
||||
M_W Use_Timeout [90 ] 90
|
||||
|
||||
MM Load [2 ] 2
|
||||
MM Load [6 ] 6
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [66 ] 66
|
||||
MM L1_Replacement [771 ] 771
|
||||
MM Store [74 ] 74
|
||||
MM L1_Replacement [780 ] 780
|
||||
MM Fwd_GETX [0 ] 0
|
||||
MM Fwd_GETS [0 ] 0
|
||||
MM Fwd_DMA [0 ] 0
|
||||
|
|
@ -254,22 +254,22 @@ MM Fwd_DMA [0 ] 0
|
|||
MM_W Load [1 ] 1
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [6 ] 6
|
||||
MM_W L1_Replacement [28136 ] 28136
|
||||
MM_W L1_Replacement [28210 ] 28210
|
||||
MM_W Own_GETX [0 ] 0
|
||||
MM_W Fwd_GETX [0 ] 0
|
||||
MM_W Fwd_GETS [0 ] 0
|
||||
MM_W Fwd_DMA [0 ] 0
|
||||
MM_W Inv [0 ] 0
|
||||
MM_W Use_Timeout [772 ] 772
|
||||
MM_W Use_Timeout [780 ] 780
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L1_Replacement [439219 ] 439219
|
||||
IM L1_Replacement [383229 ] 383229
|
||||
IM Inv [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [772 ] 772
|
||||
IM Exclusive_Data [782 ] 782
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
|
@ -285,21 +285,21 @@ SM Exclusive_Data [0 ] 0
|
|||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
OM Store [0 ] 0
|
||||
OM L1_Replacement [14936 ] 14936
|
||||
OM L1_Replacement [14910 ] 14910
|
||||
OM Own_GETX [0 ] 0
|
||||
OM Fwd_GETX [0 ] 0
|
||||
OM Fwd_GETS [0 ] 0
|
||||
OM Fwd_DMA [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [772 ] 772
|
||||
OM All_acks [782 ] 782
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L1_Replacement [22444 ] 22444
|
||||
IS L1_Replacement [20974 ] 20974
|
||||
IS Inv [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Exclusive_Data [96 ] 96
|
||||
IS Exclusive_Data [90 ] 90
|
||||
|
||||
SI Load [0 ] 0
|
||||
SI Ifetch [0 ] 0
|
||||
|
|
@ -323,15 +323,15 @@ OI Writeback_Ack [0 ] 0
|
|||
OI Writeback_Ack_Data [0 ] 0
|
||||
OI Writeback_Nack [0 ] 0
|
||||
|
||||
MI Load [2 ] 2
|
||||
MI Ifetch [262 ] 262
|
||||
MI Store [119 ] 119
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [148 ] 148
|
||||
MI Store [176 ] 176
|
||||
MI L1_Replacement [0 ] 0
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Fwd_GETS [0 ] 0
|
||||
MI Fwd_DMA [0 ] 0
|
||||
MI Writeback_Ack [0 ] 0
|
||||
MI Writeback_Ack_Data [864 ] 864
|
||||
MI Writeback_Ack_Data [867 ] 867
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
|
|
@ -353,10 +353,10 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [127 ] 127
|
||||
L1_GETX [839 ] 839
|
||||
L1_GETS [129 ] 129
|
||||
L1_GETX [848 ] 848
|
||||
L1_PUTO [0 ] 0
|
||||
L1_PUTX [2005 ] 2005
|
||||
L1_PUTX [2406 ] 2406
|
||||
L1_PUTS_only [0 ] 0
|
||||
L1_PUTS [0 ] 0
|
||||
Fwd_GETX [0 ] 0
|
||||
|
|
@ -366,21 +366,21 @@ Own_GETX [0 ] 0
|
|||
Inv [0 ] 0
|
||||
IntAck [0 ] 0
|
||||
ExtAck [0 ] 0
|
||||
All_Acks [736 ] 736
|
||||
Data [736 ] 736
|
||||
Data_Exclusive [86 ] 86
|
||||
L1_WBCLEANDATA [84 ] 84
|
||||
L1_WBDIRTYDATA [778 ] 778
|
||||
Writeback_Ack [813 ] 813
|
||||
All_Acks [752 ] 752
|
||||
Data [752 ] 752
|
||||
Data_Exclusive [80 ] 80
|
||||
L1_WBCLEANDATA [79 ] 79
|
||||
L1_WBDIRTYDATA [788 ] 788
|
||||
Writeback_Ack [823 ] 823
|
||||
Writeback_Nack [0 ] 0
|
||||
Unblock [0 ] 0
|
||||
Exclusive_Unblock [866 ] 866
|
||||
Exclusive_Unblock [871 ] 871
|
||||
DmaAck [0 ] 0
|
||||
L2_Replacement [814 ] 814
|
||||
L2_Replacement [824 ] 824
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [87 ] 87
|
||||
NP L1_GETX [737 ] 737
|
||||
NP L1_GETS [80 ] 80
|
||||
NP L1_GETX [752 ] 752
|
||||
NP L1_PUTO [0 ] 0
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTS [0 ] 0
|
||||
|
|
@ -406,7 +406,7 @@ ILS L2_Replacement [0 ] 0
|
|||
ILX L1_GETS [0 ] 0
|
||||
ILX L1_GETX [0 ] 0
|
||||
ILX L1_PUTO [0 ] 0
|
||||
ILX L1_PUTX [865 ] 865
|
||||
ILX L1_PUTX [867 ] 867
|
||||
ILX L1_PUTS_only [0 ] 0
|
||||
ILX L1_PUTS [0 ] 0
|
||||
ILX Fwd_GETX [0 ] 0
|
||||
|
|
@ -506,14 +506,14 @@ SLS Inv [0 ] 0
|
|||
SLS L2_Replacement [0 ] 0
|
||||
|
||||
M L1_GETS [10 ] 10
|
||||
M L1_GETX [36 ] 36
|
||||
M L1_GETX [30 ] 30
|
||||
M L1_PUTO [0 ] 0
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTS [0 ] 0
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_DMA [0 ] 0
|
||||
M L2_Replacement [813 ] 813
|
||||
M L2_Replacement [824 ] 824
|
||||
|
||||
IFGX L1_GETS [0 ] 0
|
||||
IFGX L1_GETX [0 ] 0
|
||||
|
|
@ -762,8 +762,8 @@ OLSXW Inv [0 ] 0
|
|||
OLSXW Unblock [0 ] 0
|
||||
OLSXW L2_Replacement [0 ] 0
|
||||
|
||||
ILXW L1_GETS [30 ] 30
|
||||
ILXW L1_GETX [31 ] 31
|
||||
ILXW L1_GETS [36 ] 36
|
||||
ILXW L1_GETX [47 ] 47
|
||||
ILXW L1_PUTO [0 ] 0
|
||||
ILXW L1_PUTX [0 ] 0
|
||||
ILXW L1_PUTS_only [0 ] 0
|
||||
|
|
@ -773,8 +773,8 @@ ILXW Fwd_GETS [0 ] 0
|
|||
ILXW Fwd_DMA [0 ] 0
|
||||
ILXW Inv [0 ] 0
|
||||
ILXW Data [0 ] 0
|
||||
ILXW L1_WBCLEANDATA [84 ] 84
|
||||
ILXW L1_WBDIRTYDATA [778 ] 778
|
||||
ILXW L1_WBCLEANDATA [79 ] 79
|
||||
ILXW L1_WBDIRTYDATA [788 ] 788
|
||||
ILXW Unblock [0 ] 0
|
||||
ILXW L2_Replacement [0 ] 0
|
||||
|
||||
|
|
@ -862,7 +862,7 @@ IFLXO L2_Replacement [0 ] 0
|
|||
IGS L1_GETS [0 ] 0
|
||||
IGS L1_GETX [0 ] 0
|
||||
IGS L1_PUTO [0 ] 0
|
||||
IGS L1_PUTX [87 ] 87
|
||||
IGS L1_PUTX [44 ] 44
|
||||
IGS L1_PUTS_only [0 ] 0
|
||||
IGS L1_PUTS [0 ] 0
|
||||
IGS Fwd_GETX [0 ] 0
|
||||
|
|
@ -871,9 +871,9 @@ IGS Fwd_DMA [0 ] 0
|
|||
IGS Own_GETX [0 ] 0
|
||||
IGS Inv [0 ] 0
|
||||
IGS Data [0 ] 0
|
||||
IGS Data_Exclusive [86 ] 86
|
||||
IGS Data_Exclusive [80 ] 80
|
||||
IGS Unblock [0 ] 0
|
||||
IGS Exclusive_Unblock [84 ] 84
|
||||
IGS Exclusive_Unblock [80 ] 80
|
||||
IGS L2_Replacement [0 ] 0
|
||||
|
||||
IGM L1_GETS [0 ] 0
|
||||
|
|
@ -888,7 +888,7 @@ IGM Fwd_DMA [0 ] 0
|
|||
IGM Own_GETX [0 ] 0
|
||||
IGM Inv [0 ] 0
|
||||
IGM ExtAck [0 ] 0
|
||||
IGM Data [736 ] 736
|
||||
IGM Data [752 ] 752
|
||||
IGM Data_Exclusive [0 ] 0
|
||||
IGM L2_Replacement [0 ] 0
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ IGMLS L2_Replacement [0 ] 0
|
|||
IGMO L1_GETS [0 ] 0
|
||||
IGMO L1_GETX [0 ] 0
|
||||
IGMO L1_PUTO [0 ] 0
|
||||
IGMO L1_PUTX [1037 ] 1037
|
||||
IGMO L1_PUTX [1465 ] 1465
|
||||
IGMO L1_PUTS_only [0 ] 0
|
||||
IGMO L1_PUTS [0 ] 0
|
||||
IGMO Fwd_GETX [0 ] 0
|
||||
|
|
@ -917,8 +917,8 @@ IGMO Fwd_GETS [0 ] 0
|
|||
IGMO Fwd_DMA [0 ] 0
|
||||
IGMO Own_GETX [0 ] 0
|
||||
IGMO ExtAck [0 ] 0
|
||||
IGMO All_Acks [736 ] 736
|
||||
IGMO Exclusive_Unblock [736 ] 736
|
||||
IGMO All_Acks [752 ] 752
|
||||
IGMO Exclusive_Unblock [751 ] 751
|
||||
IGMO L2_Replacement [0 ] 0
|
||||
|
||||
IGMIO L1_GETS [0 ] 0
|
||||
|
|
@ -991,14 +991,14 @@ II All_Acks [0 ] 0
|
|||
MM L1_GETS [0 ] 0
|
||||
MM L1_GETX [0 ] 0
|
||||
MM L1_PUTO [0 ] 0
|
||||
MM L1_PUTX [0 ] 0
|
||||
MM L1_PUTX [30 ] 30
|
||||
MM L1_PUTS_only [0 ] 0
|
||||
MM L1_PUTS [0 ] 0
|
||||
MM Fwd_GETX [0 ] 0
|
||||
MM Fwd_GETS [0 ] 0
|
||||
MM Fwd_DMA [0 ] 0
|
||||
MM Inv [0 ] 0
|
||||
MM Exclusive_Unblock [36 ] 36
|
||||
MM Exclusive_Unblock [30 ] 30
|
||||
MM L2_Replacement [0 ] 0
|
||||
|
||||
SS L1_GETS [0 ] 0
|
||||
|
|
@ -1017,7 +1017,7 @@ SS L2_Replacement [0 ] 0
|
|||
OO L1_GETS [0 ] 0
|
||||
OO L1_GETX [0 ] 0
|
||||
OO L1_PUTO [0 ] 0
|
||||
OO L1_PUTX [16 ] 16
|
||||
OO L1_PUTX [0 ] 0
|
||||
OO L1_PUTS_only [0 ] 0
|
||||
OO L1_PUTS [0 ] 0
|
||||
OO Fwd_GETX [0 ] 0
|
||||
|
|
@ -1026,7 +1026,7 @@ OO Fwd_DMA [0 ] 0
|
|||
OO Inv [0 ] 0
|
||||
OO Unblock [0 ] 0
|
||||
OO Exclusive_Unblock [10 ] 10
|
||||
OO L2_Replacement [1 ] 1
|
||||
OO L2_Replacement [0 ] 0
|
||||
|
||||
OLSS L1_GETS [0 ] 0
|
||||
OLSS L1_GETX [0 ] 0
|
||||
|
|
@ -1080,8 +1080,8 @@ OI Writeback_Ack [0 ] 0
|
|||
OI Writeback_Nack [0 ] 0
|
||||
OI L2_Replacement [0 ] 0
|
||||
|
||||
MI L1_GETS [0 ] 0
|
||||
MI L1_GETX [35 ] 35
|
||||
MI L1_GETS [3 ] 3
|
||||
MI L1_GETX [19 ] 19
|
||||
MI L1_PUTO [0 ] 0
|
||||
MI L1_PUTX [0 ] 0
|
||||
MI L1_PUTS_only [0 ] 0
|
||||
|
|
@ -1089,7 +1089,7 @@ MI L1_PUTS [0 ] 0
|
|||
MI Fwd_GETX [0 ] 0
|
||||
MI Fwd_GETS [0 ] 0
|
||||
MI Fwd_DMA [0 ] 0
|
||||
MI Writeback_Ack [813 ] 813
|
||||
MI Writeback_Ack [823 ] 823
|
||||
MI L2_Replacement [0 ] 0
|
||||
|
||||
MII L1_GETS [0 ] 0
|
||||
|
|
@ -1196,51 +1196,51 @@ ILOXD DmaAck [0 ] 0
|
|||
ILOXD L2_Replacement [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1557
|
||||
memory_reads: 824
|
||||
memory_writes: 733
|
||||
memory_refreshes: 745
|
||||
memory_total_request_delays: 699
|
||||
memory_delays_per_request: 0.44894
|
||||
memory_delays_in_input_queue: 100
|
||||
memory_total_requests: 1578
|
||||
memory_reads: 832
|
||||
memory_writes: 746
|
||||
memory_refreshes: 2198
|
||||
memory_total_request_delays: 449
|
||||
memory_delays_per_request: 0.284537
|
||||
memory_delays_in_input_queue: 36
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 599
|
||||
memory_stalls_for_bank_busy: 167
|
||||
memory_delays_stalled_at_head_of_bank_queue: 413
|
||||
memory_stalls_for_bank_busy: 165
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 37
|
||||
memory_stalls_for_bus: 228
|
||||
memory_stalls_for_arbitration: 26
|
||||
memory_stalls_for_bus: 146
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 89
|
||||
memory_stalls_for_read_read_turnaround: 78
|
||||
accesses_per_bank: 58 56 38 78 87 60 65 48 44 42 38 35 56 49 46 40 29 55 43 35 47 44 52 40 42 46 53 46 44 46 52 43
|
||||
memory_stalls_for_read_write_turnaround: 29
|
||||
memory_stalls_for_read_read_turnaround: 47
|
||||
accesses_per_bank: 42 42 62 72 55 44 62 62 55 41 42 49 52 46 57 38 61 59 41 51 46 55 45 47 39 55 63 43 31 45 39 37
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [788 ] 788
|
||||
GETS [87 ] 87
|
||||
PUTX [817 ] 817
|
||||
GETX [765 ] 765
|
||||
GETS [80 ] 80
|
||||
PUTX [823 ] 823
|
||||
PUTO [0 ] 0
|
||||
PUTO_SHARERS [0 ] 0
|
||||
Unblock [0 ] 0
|
||||
Last_Unblock [0 ] 0
|
||||
Exclusive_Unblock [820 ] 820
|
||||
Clean_Writeback [80 ] 80
|
||||
Dirty_Writeback [733 ] 733
|
||||
Memory_Data [822 ] 822
|
||||
Memory_Ack [732 ] 732
|
||||
Exclusive_Unblock [830 ] 830
|
||||
Clean_Writeback [76 ] 76
|
||||
Dirty_Writeback [746 ] 746
|
||||
Memory_Data [832 ] 832
|
||||
Memory_Ack [746 ] 746
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_ACK [0 ] 0
|
||||
Data [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I GETX [737 ] 737
|
||||
I GETS [87 ] 87
|
||||
I GETX [752 ] 752
|
||||
I GETS [80 ] 80
|
||||
I PUTX [0 ] 0
|
||||
I PUTO [0 ] 0
|
||||
I Memory_Data [0 ] 0
|
||||
I Memory_Ack [728 ] 728
|
||||
I Memory_Ack [744 ] 744
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -1265,7 +1265,7 @@ O DMA_WRITE [0 ] 0
|
|||
|
||||
M GETX [0 ] 0
|
||||
M GETS [0 ] 0
|
||||
M PUTX [813 ] 813
|
||||
M PUTX [823 ] 823
|
||||
M PUTO [0 ] 0
|
||||
M PUTO_SHARERS [0 ] 0
|
||||
M Memory_Data [0 ] 0
|
||||
|
|
@ -1279,8 +1279,8 @@ IS PUTX [0 ] 0
|
|||
IS PUTO [0 ] 0
|
||||
IS PUTO_SHARERS [0 ] 0
|
||||
IS Unblock [0 ] 0
|
||||
IS Exclusive_Unblock [84 ] 84
|
||||
IS Memory_Data [86 ] 86
|
||||
IS Exclusive_Unblock [80 ] 80
|
||||
IS Memory_Data [80 ] 80
|
||||
IS Memory_Ack [0 ] 0
|
||||
IS DMA_READ [0 ] 0
|
||||
IS DMA_WRITE [0 ] 0
|
||||
|
|
@ -1323,24 +1323,24 @@ MO DMA_WRITE [0 ] 0
|
|||
|
||||
MM GETX [0 ] 0
|
||||
MM GETS [0 ] 0
|
||||
MM PUTX [4 ] 4
|
||||
MM PUTX [0 ] 0
|
||||
MM PUTO [0 ] 0
|
||||
MM PUTO_SHARERS [0 ] 0
|
||||
MM Exclusive_Unblock [736 ] 736
|
||||
MM Memory_Data [736 ] 736
|
||||
MM Memory_Ack [4 ] 4
|
||||
MM Exclusive_Unblock [750 ] 750
|
||||
MM Memory_Data [752 ] 752
|
||||
MM Memory_Ack [2 ] 2
|
||||
MM DMA_READ [0 ] 0
|
||||
MM DMA_WRITE [0 ] 0
|
||||
|
||||
|
||||
MI GETX [51 ] 51
|
||||
MI GETX [13 ] 13
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTO [0 ] 0
|
||||
MI PUTO_SHARERS [0 ] 0
|
||||
MI Unblock [0 ] 0
|
||||
MI Clean_Writeback [80 ] 80
|
||||
MI Dirty_Writeback [733 ] 733
|
||||
MI Clean_Writeback [76 ] 76
|
||||
MI Dirty_Writeback [746 ] 746
|
||||
MI Memory_Data [0 ] 0
|
||||
MI Memory_Ack [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:32:56
|
||||
gem5 started Jul 28 2012 11:35:54
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 14:10:16
|
||||
gem5 started Sep 1 2012 14:14:49
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 357561 because Ruby Tester completed
|
||||
Exiting @ tick 316521 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000358 # Number of seconds simulated
|
||||
sim_ticks 357561 # Number of ticks simulated
|
||||
final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000317 # Number of seconds simulated
|
||||
sim_ticks 316521 # Number of ticks simulated
|
||||
final_tick 316521 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 791110 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229444 # Number of bytes of host memory used
|
||||
host_seconds 0.45 # Real time elapsed on the host
|
||||
host_tick_rate 596457 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260972 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -59,9 +60,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -70,6 +71,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -152,6 +154,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
@ -167,6 +170,7 @@ slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -268,6 +272,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
@ -281,6 +286,7 @@ slave=system.system_port
|
|||
type=RubyTester
|
||||
check_flush=true
|
||||
checks_to_complete=100
|
||||
clock=1
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:54:42
|
||||
Real time: Sep/01/2012 13:57:00
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.48
|
||||
Virtual_time_in_minutes: 0.008
|
||||
Virtual_time_in_hours: 0.000133333
|
||||
Virtual_time_in_days: 5.55556e-06
|
||||
Virtual_time_in_seconds: 0.44
|
||||
Virtual_time_in_minutes: 0.00733333
|
||||
Virtual_time_in_hours: 0.000122222
|
||||
Virtual_time_in_days: 5.09259e-06
|
||||
|
||||
Ruby_current_time: 205611
|
||||
Ruby_current_time: 172201
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 205611
|
||||
Ruby_cycles: 172201
|
||||
|
||||
mbytes_resident: 41.625
|
||||
mbytes_total: 225.387
|
||||
resident_ratio: 0.184717
|
||||
mbytes_resident: 44.8359
|
||||
mbytes_total: 254.68
|
||||
resident_ratio: 0.176125
|
||||
|
||||
ruby_cycles_executed: [ 205612 ]
|
||||
ruby_cycles_executed: [ 172202 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -29,18 +29,18 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 955 average: 15.8063 | standard deviation: 1.1547 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 64 876 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 986 average: 15.788 | standard deviation: 1.14484 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 84 885 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 5995 count: 940 average: 3454.8 | standard deviation: 1689.48 | 73 0 0 15 0 3 1 1 9 6 2 7 11 6 2 14 6 0 5 12 4 2 3 2 1 3 2 1 0 0 1 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 3 3 2 4 5 6 5 14 2 7 10 3 17 12 13 12 12 19 15 16 15 18 28 27 20 15 26 23 19 24 21 26 18 22 22 18 11 20 18 12 11 10 9 7 8 8 11 9 0 7 5 8 5 7 3 3 4 5 4 1 1 5 2 2 0 0 3 0 0 2 0 0 2 5 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5688 count: 51 average: 3691.18 | standard deviation: 1748.75 | 8 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 0 0 0 1 0 0 1 0 0 2 1 0 4 1 3 1 1 0 1 2 1 3 0 0 4 1 1 2 2 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 5995 count: 837 average: 3617.77 | standard deviation: 1564.58 | 62 0 0 14 0 2 1 0 4 4 2 3 5 2 0 10 2 0 2 7 4 1 2 0 1 2 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 3 3 2 4 5 6 4 14 2 7 10 3 15 12 13 12 12 18 15 16 14 18 28 25 19 15 22 21 16 23 20 26 17 20 21 14 11 20 14 11 10 8 7 7 8 8 10 9 0 7 5 7 4 7 3 3 3 5 3 1 0 5 2 2 0 0 3 0 0 2 0 0 1 5 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 809 count: 49 average: 434 | standard deviation: 189.079 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 2 2 1 0 1 0 0 0 0 0 0 1 0 2 4 2 0 0 1 2 1 0 0 2 0 0 1 2 1 0 2 0 1 1 0 0 0 0 1 1 0 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH: [binsize: 32 max: 4507 count: 3 average: 3306 | standard deviation: 1853.78 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4507 count: 81 average: 139.605 | standard deviation: 691.167 | 67 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 5708 count: 38 average: 2643.53 | standard deviation: 1886.57 | 6 0 0 4 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 2 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 2 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 5995 count: 821 average: 3819.42 | standard deviation: 1346.15 | 0 0 0 0 0 3 1 1 9 5 2 7 11 5 2 14 6 0 5 11 4 2 3 2 1 3 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 2 2 2 4 4 6 5 12 2 7 10 2 17 12 13 12 11 18 14 15 14 17 28 25 19 14 25 21 19 23 21 26 18 22 22 16 11 20 18 12 11 10 8 7 8 8 11 9 0 7 5 8 5 7 3 3 4 5 4 1 1 5 2 2 0 0 3 0 0 2 0 0 2 4 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency: [binsize: 32 max: 4954 count: 971 average: 2802.39 | standard deviation: 1327.57 | 80 0 6 7 2 8 6 2 1 19 3 3 8 2 2 8 6 2 5 4 1 3 3 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 1 2 2 0 1 1 5 4 7 3 3 4 9 8 7 5 8 19 10 17 6 23 19 18 16 17 17 21 17 30 28 20 26 23 25 26 21 23 34 18 14 18 15 15 9 20 13 16 12 12 7 10 6 8 6 11 3 1 4 6 4 5 2 4 0 0 0 1 1 0 0 2 1 0 2 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4368 count: 50 average: 2780.46 | standard deviation: 1378.72 | 4 0 1 1 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 2 1 1 0 1 0 3 0 0 1 1 1 0 0 0 4 1 1 1 0 0 2 0 0 4 3 0 1 0 0 0 0 2 1 0 0 3 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4954 count: 866 average: 2940.8 | standard deviation: 1219.88 | 67 0 4 4 1 5 5 1 1 9 2 1 3 1 1 5 4 0 3 2 0 2 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 1 1 2 0 1 1 5 4 7 3 3 4 9 7 7 4 7 17 9 16 6 22 19 15 16 17 16 20 16 30 28 20 22 22 23 25 20 23 32 17 14 14 12 15 8 20 13 16 12 10 6 10 6 5 5 9 3 1 4 6 4 5 2 3 0 0 0 1 1 0 0 2 1 0 2 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 817 count: 50 average: 332.28 | standard deviation: 230.032 | 6 3 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 1 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 3 2 1 2 0 1 0 0 0 0 1 1 2 1 0 1 1 0 0 0 0 1 0 0 0 1 0 2 1 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH: [binsize: 32 max: 4122 count: 5 average: 3751 | standard deviation: 332.267 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4122 count: 76 average: 256.355 | standard deviation: 937.092 | 66 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 4319 count: 49 average: 1546.86 | standard deviation: 1620.72 | 14 0 3 1 0 1 2 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 2 0 0 0 1 0 0 0 1 1 1 1 0 0 0 2 0 0 0 1 0 0 2 0 0 1 0 1 0 0 0 0 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4954 count: 846 average: 3103.83 | standard deviation: 1015.18 | 0 0 3 1 2 7 4 1 1 18 3 3 7 2 1 7 6 2 5 3 1 3 3 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 1 2 2 0 1 1 4 3 6 3 3 4 9 6 7 5 8 18 10 17 6 22 18 17 15 17 17 21 15 30 28 20 25 23 24 24 20 23 33 17 13 18 15 15 9 19 13 14 12 11 7 10 6 8 5 10 3 1 4 6 4 4 2 4 0 0 0 1 1 0 0 2 1 0 2 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -50,16 +50,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 821
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 7 average: 2.42857 | standard deviation: 1 | 0 1 3 2 1 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 32 max: 4298 count: 2 average: 2152.5 | standard deviation: 3034.2 | 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5688 count: 42 average: 4379.24 | standard deviation: 762.412 | 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 0 0 0 1 0 0 1 0 0 2 1 0 4 1 3 0 1 0 1 2 1 3 0 0 4 1 1 2 2 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 71 average: 19.338 | standard deviation: 39.1116 | 0 12 12 16 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 3 1 0 0 2 0 1 0 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 5708 count: 32 average: 3000.47 | standard deviation: 1710.17 | 2 0 0 3 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 2 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 2 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 5995 count: 734 average: 3992.76 | standard deviation: 1120.88 | 0 0 0 0 0 2 1 0 4 3 2 3 5 1 0 10 2 0 2 6 4 1 2 0 1 2 2 1 0 0 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 2 2 2 4 4 6 4 12 2 7 10 2 15 12 13 12 11 17 14 15 13 17 28 23 18 14 21 20 16 23 20 26 17 20 21 13 11 20 14 11 10 8 6 7 8 8 10 9 0 7 5 7 4 7 3 3 3 5 3 1 0 5 2 2 0 0 3 0 0 2 0 0 1 4 0 0 0 1 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 115 count: 4 average: 33.5 | standard deviation: 54.3476 | 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 809 count: 45 average: 469.6 | standard deviation: 151.399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 2 2 1 0 1 0 0 0 0 0 0 1 0 2 4 2 0 0 1 2 1 0 0 2 0 0 1 2 1 0 2 0 1 1 0 0 0 0 1 1 0 1 3 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH_L1Cache: [binsize: 32 max: 4507 count: 3 average: 3306 | standard deviation: 1853.78 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 846
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 112 count: 5 average: 24 | standard deviation: 49.2037 | 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4368 count: 45 average: 3086.73 | standard deviation: 1075.78 | 0 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 2 1 1 0 1 0 3 0 0 1 1 1 0 0 0 4 1 1 1 0 0 2 0 0 4 3 0 1 0 0 0 0 2 1 0 0 3 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 65 average: 9.33846 | standard deviation: 26.6015 | 0 13 15 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 4319 count: 40 average: 1890.95 | standard deviation: 1603.6 | 6 0 3 0 0 1 2 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 2 0 0 0 1 0 0 0 1 1 1 1 0 0 0 2 0 0 0 1 0 0 2 0 0 1 0 1 0 0 0 0 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4954 count: 761 average: 3246.37 | standard deviation: 821.708 | 0 0 1 0 1 4 3 0 1 8 2 1 2 1 0 4 4 0 3 1 0 2 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 1 1 2 0 1 1 4 3 6 3 3 4 9 5 7 4 7 16 9 16 6 21 18 14 15 17 16 20 14 30 28 20 21 22 23 23 20 23 31 17 13 14 12 15 8 19 13 14 12 9 6 10 6 5 5 9 3 1 4 6 4 4 2 3 0 0 0 1 1 0 0 2 1 0 2 2 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 1 count: 1 average: 1 | standard deviation: 0 | 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 107 count: 9 average: 17.5556 | standard deviation: 33.5764 | 0 0 0 0 1 2 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 817 count: 40 average: 411.375 | standard deviation: 184.832 | 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 2 1 0 0 0 1 0 0 0 0 0 0 0 3 2 1 2 0 1 0 0 0 0 1 1 2 1 0 1 1 0 0 0 0 1 0 0 0 1 0 2 1 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_FLUSH_L1Cache: [binsize: 32 max: 4122 count: 5 average: 3751 | standard deviation: 332.267 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -91,60 +91,60 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11775
|
||||
page_reclaims: 8466
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 88
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 2475 19800
|
||||
total_msg_count_Response_Data: 2469 177768
|
||||
total_msg_count_Writeback_Data: 2211 159192
|
||||
total_msg_count_Writeback_Control: 5145 41160
|
||||
total_msg_count_Unblock_Control: 2460 19680
|
||||
total_msgs: 14760 total_bytes: 417600
|
||||
total_msg_count_Request_Control: 2554 20432
|
||||
total_msg_count_Response_Data: 2550 183600
|
||||
total_msg_count_Writeback_Data: 2303 165816
|
||||
total_msg_count_Writeback_Control: 5288 42304
|
||||
total_msg_count_Unblock_Control: 2535 20280
|
||||
total_msgs: 15230 total_bytes: 432432
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.11565
|
||||
links_utilized_percent_switch_0_link_0: 2.00014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.23115 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.61656
|
||||
links_utilized_percent_switch_0_link_0: 2.4663 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.76682 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 844 6752 [ 0 0 0 844 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 0 768 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 920 7360 [ 0 0 845 0 0 75 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.11565
|
||||
links_utilized_percent_switch_1_link_0: 2.23115 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.00014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.61482
|
||||
links_utilized_percent_switch_1_link_0: 2.76334 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.4663 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 918 7344 [ 0 0 843 0 0 75 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 844 6752 [ 0 0 0 844 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.11565
|
||||
links_utilized_percent_switch_2_link_0: 2.00014 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.23115 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 2.61613
|
||||
links_utilized_percent_switch_2_link_0: 2.4663 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.76595 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 823 59256 [ 0 0 0 0 823 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 818 6544 [ 0 0 0 818 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 825 6600 [ 0 0 825 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 737 53064 [ 0 0 0 0 0 737 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 897 7176 [ 0 0 817 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 820 6560 [ 0 0 0 0 0 820 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 844 6752 [ 0 0 0 844 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 0 768 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 918 7344 [ 0 0 843 0 0 75 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 49
|
||||
|
|
@ -158,42 +158,42 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 49 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 812
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 812
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 849
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 849
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.41872%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4581%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_FLUSH: 0.123153%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.41814%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4641%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_FLUSH: 0.117786%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 812 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 849 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 863
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 863
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 902
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 902
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.09849%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 88.876%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.67787%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_FLUSH: 0.347625%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.09978%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 88.9135%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.43237%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_FLUSH: 0.554324%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 863 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 902 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [53 ] 53
|
||||
Ifetch [49 ] 49
|
||||
Store [861 ] 861
|
||||
L2_Replacement [814 ] 814
|
||||
L1_to_L2 [15927 ] 15927
|
||||
Trigger_L2_to_L1D [35 ] 35
|
||||
Trigger_L2_to_L1I [4 ] 4
|
||||
Complete_L2_to_L1 [39 ] 39
|
||||
Load [52 ] 52
|
||||
Ifetch [53 ] 53
|
||||
Store [888 ] 888
|
||||
L2_Replacement [840 ] 840
|
||||
L1_to_L2 [16587 ] 16587
|
||||
Trigger_L2_to_L1D [41 ] 41
|
||||
Trigger_L2_to_L1I [9 ] 9
|
||||
Complete_L2_to_L1 [50 ] 50
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
|
|
@ -204,18 +204,18 @@ Ack [0 ] 0
|
|||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [823 ] 823
|
||||
Writeback_Ack [817 ] 817
|
||||
Exclusive_Data [850 ] 850
|
||||
Writeback_Ack [843 ] 843
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [823 ] 823
|
||||
Flush_line [3 ] 3
|
||||
All_acks_no_sharers [850 ] 850
|
||||
Flush_line [5 ] 5
|
||||
Block_Ack [1 ] 1
|
||||
|
||||
- Transitions -
|
||||
I Load [42 ] 42
|
||||
I Ifetch [45 ] 45
|
||||
I Store [735 ] 735
|
||||
I Load [46 ] 46
|
||||
I Ifetch [40 ] 40
|
||||
I Store [762 ] 762
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
|
|
@ -225,7 +225,7 @@ I Other_GETS [0 ] 0
|
|||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [2 ] 2
|
||||
I Flush_line [4 ] 4
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
|
|
@ -257,11 +257,11 @@ O Invalidate [0 ] 0
|
|||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Store [0 ] 0
|
||||
M L2_Replacement [78 ] 78
|
||||
M L1_to_L2 [84 ] 84
|
||||
M Trigger_L2_to_L1D [6 ] 6
|
||||
M L2_Replacement [71 ] 71
|
||||
M L1_to_L2 [83 ] 83
|
||||
M Trigger_L2_to_L1D [11 ] 11
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
|
|
@ -271,13 +271,13 @@ M NC_DMA_GETS [0 ] 0
|
|||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [6 ] 6
|
||||
MM Load [5 ] 5
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [69 ] 69
|
||||
MM L2_Replacement [736 ] 736
|
||||
MM L1_to_L2 [771 ] 771
|
||||
MM Trigger_L2_to_L1D [29 ] 29
|
||||
MM Trigger_L2_to_L1I [4 ] 4
|
||||
MM Store [62 ] 62
|
||||
MM L2_Replacement [769 ] 769
|
||||
MM L1_to_L2 [809 ] 809
|
||||
MM Trigger_L2_to_L1D [30 ] 30
|
||||
MM Trigger_L2_to_L1I [9 ] 9
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
|
|
@ -306,21 +306,21 @@ OR Flush_line [0 ] 0
|
|||
|
||||
MR Load [0 ] 0
|
||||
MR Ifetch [0 ] 0
|
||||
MR Store [6 ] 6
|
||||
MR L1_to_L2 [25 ] 25
|
||||
MR Store [11 ] 11
|
||||
MR L1_to_L2 [90 ] 90
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [2 ] 2
|
||||
MMR Ifetch [4 ] 4
|
||||
MMR Store [26 ] 26
|
||||
MMR L1_to_L2 [91 ] 91
|
||||
MMR Load [0 ] 0
|
||||
MMR Ifetch [9 ] 9
|
||||
MMR Store [29 ] 29
|
||||
MMR L1_to_L2 [25 ] 25
|
||||
MMR Flush_line [1 ] 1
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [9582 ] 9582
|
||||
IM L1_to_L2 [9996 ] 9996
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -328,7 +328,7 @@ IM NC_DMA_GETS [0 ] 0
|
|||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [734 ] 734
|
||||
IM Exclusive_Data [761 ] 761
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -375,25 +375,25 @@ M_W Load [0 ] 0
|
|||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [253 ] 253
|
||||
M_W L1_to_L2 [306 ] 306
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [87 ] 87
|
||||
M_W All_acks_no_sharers [85 ] 85
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [2 ] 2
|
||||
MM_W Store [3 ] 3
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [4505 ] 4505
|
||||
MM_W L1_to_L2 [4592 ] 4592
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [734 ] 734
|
||||
MM_W All_acks_no_sharers [761 ] 761
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [525 ] 525
|
||||
IS L1_to_L2 [529 ] 529
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -403,7 +403,7 @@ IS Ack [0 ] 0
|
|||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [87 ] 87
|
||||
IS Exclusive_Data [85 ] 85
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
|
|
@ -431,9 +431,9 @@ OI Invalidate [0 ] 0
|
|||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [0 ] 0
|
||||
MI Store [2 ] 2
|
||||
MI Load [1 ] 1
|
||||
MI Ifetch [3 ] 3
|
||||
MI Store [1 ] 1
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
|
|
@ -442,7 +442,7 @@ MI Merged_GETS [0 ] 0
|
|||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [814 ] 814
|
||||
MI Writeback_Ack [838 ] 838
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
|
|
@ -482,23 +482,23 @@ OT Complete_L2_to_L1 [0 ] 0
|
|||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [1 ] 1
|
||||
MT Store [2 ] 2
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [14 ] 14
|
||||
MT Complete_L2_to_L1 [6 ] 6
|
||||
MT L1_to_L2 [54 ] 54
|
||||
MT Complete_L2_to_L1 [11 ] 11
|
||||
|
||||
MMT Load [2 ] 2
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [20 ] 20
|
||||
MMT Store [18 ] 18
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [77 ] 77
|
||||
MMT Complete_L2_to_L1 [33 ] 33
|
||||
MMT L1_to_L2 [103 ] 103
|
||||
MMT Complete_L2_to_L1 [39 ] 39
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [3 ] 3
|
||||
MI_F Writeback_Ack [5 ] 5
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
|
|
@ -529,7 +529,7 @@ IM_F NC_DMA_GETS [0 ] 0
|
|||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [2 ] 2
|
||||
IM_F Exclusive_Data [4 ] 4
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
|
|
@ -578,7 +578,7 @@ MM_WF Store [0 ] 0
|
|||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [2 ] 2
|
||||
MM_WF All_acks_no_sharers [4 ] 4
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
|
@ -590,42 +590,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
|
|||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1560
|
||||
memory_reads: 824
|
||||
memory_writes: 736
|
||||
memory_refreshes: 429
|
||||
memory_total_request_delays: 1115
|
||||
memory_delays_per_request: 0.714744
|
||||
memory_delays_in_input_queue: 138
|
||||
memory_delays_behind_head_of_bank_queue: 10
|
||||
memory_delays_stalled_at_head_of_bank_queue: 967
|
||||
memory_stalls_for_bank_busy: 228
|
||||
memory_total_requests: 1617
|
||||
memory_reads: 850
|
||||
memory_writes: 767
|
||||
memory_refreshes: 1196
|
||||
memory_total_request_delays: 599
|
||||
memory_delays_per_request: 0.370439
|
||||
memory_delays_in_input_queue: 48
|
||||
memory_delays_behind_head_of_bank_queue: 1
|
||||
memory_delays_stalled_at_head_of_bank_queue: 550
|
||||
memory_stalls_for_bank_busy: 172
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 72
|
||||
memory_stalls_for_bus: 362
|
||||
memory_stalls_for_arbitration: 40
|
||||
memory_stalls_for_bus: 204
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 186
|
||||
memory_stalls_for_read_read_turnaround: 119
|
||||
accesses_per_bank: 47 55 53 77 82 53 68 47 52 57 48 52 53 45 30 61 44 37 47 47 54 41 43 45 39 47 27 43 41 34 39 52
|
||||
memory_stalls_for_read_write_turnaround: 52
|
||||
memory_stalls_for_read_read_turnaround: 82
|
||||
accesses_per_bank: 60 50 58 80 69 77 71 48 48 38 42 44 39 57 47 44 42 45 53 54 55 41 48 56 29 45 43 51 47 51 42 43
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [735 ] 735
|
||||
GETS [88 ] 88
|
||||
PUT [864 ] 864
|
||||
GETX [761 ] 761
|
||||
GETS [87 ] 87
|
||||
PUT [913 ] 913
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [820 ] 820
|
||||
UnblockM [845 ] 845
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [80 ] 80
|
||||
Writeback_Exclusive_Dirty [736 ] 736
|
||||
Writeback_Exclusive_Clean [75 ] 75
|
||||
Writeback_Exclusive_Dirty [767 ] 767
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [823 ] 823
|
||||
Memory_Ack [735 ] 735
|
||||
Memory_Data [850 ] 850
|
||||
Memory_Ack [767 ] 767
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
|
|
@ -635,8 +635,8 @@ All_acks_and_shared_data [0 ] 0
|
|||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [3 ] 3
|
||||
PUTF [3 ] 3
|
||||
GETF [5 ] 5
|
||||
PUTF [5 ] 5
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
|
|
@ -649,7 +649,7 @@ NX GETF [0 ] 0
|
|||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [814 ] 814
|
||||
NO PUT [838 ] 838
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
|
@ -671,12 +671,12 @@ O DMA_READ [0 ] 0
|
|||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [735 ] 735
|
||||
E GETS [87 ] 87
|
||||
E GETX [761 ] 761
|
||||
E GETS [85 ] 85
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [2 ] 2
|
||||
E GETF [4 ] 4
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
|
|
@ -713,9 +713,9 @@ NO_R GETF [0 ] 0
|
|||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [50 ] 50
|
||||
NO_B PUT [75 ] 75
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [820 ] 820
|
||||
NO_B UnblockM [845 ] 845
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
|
|
@ -769,7 +769,7 @@ NO_B_W UnblockM [0 ] 0
|
|||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [821 ] 821
|
||||
NO_B_W Memory_Data [846 ] 846
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
|
|
@ -896,8 +896,8 @@ WB PUT [0 ] 0
|
|||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [80 ] 80
|
||||
WB Writeback_Exclusive_Dirty [736 ] 736
|
||||
WB Writeback_Exclusive_Clean [75 ] 75
|
||||
WB Writeback_Exclusive_Dirty [767 ] 767
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
|
|
@ -913,12 +913,12 @@ WB_O_W Memory_Ack [0 ] 0
|
|||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [0 ] 0
|
||||
WB_E_W GETS [1 ] 1
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [735 ] 735
|
||||
WB_E_W Memory_Ack [767 ] 767
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
|
|
@ -927,7 +927,7 @@ NO_F PUT [0 ] 0
|
|||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [3 ] 3
|
||||
NO_F PUTF [5 ] 5
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
|
|
@ -935,6 +935,6 @@ NO_F_W PUT [0 ] 0
|
|||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [2 ] 2
|
||||
NO_F_W Memory_Data [4 ] 4
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:27:37
|
||||
gem5 started Jul 28 2012 11:35:39
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Sep 1 2012 13:53:26
|
||||
gem5 started Sep 1 2012 13:57:00
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 205611 because Ruby Tester completed
|
||||
Exiting @ tick 172201 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000206 # Number of seconds simulated
|
||||
sim_ticks 205611 # Number of ticks simulated
|
||||
final_tick 205611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000172 # Number of seconds simulated
|
||||
sim_ticks 172201 # Number of ticks simulated
|
||||
final_tick 172201 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 2054687 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229284 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 1185587 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260796 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
clock=1
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
|
|
@ -56,9 +57,9 @@ bank_busy_time=11
|
|||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clock=3
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
|
|
@ -67,6 +68,7 @@ rank_rank_delay=1
|
|||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
|
|
@ -103,6 +105,7 @@ tagArrayBanks=1
|
|||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
clock=1
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
|
|
@ -118,6 +121,7 @@ slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
clock=1
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
|
|
@ -219,6 +223,7 @@ ruby_system=system.ruby
|
|||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
clock=1
|
||||
ruby_system=system.ruby
|
||||
support_data_reqs=true
|
||||
support_inst_reqs=true
|
||||
|
|
@ -232,6 +237,7 @@ slave=system.system_port
|
|||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
clock=1
|
||||
deadlock_threshold=50000
|
||||
num_cpus=1
|
||||
system=system
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Real time: Jul/10/2012 17:29:08
|
||||
Real time: Sep/01/2012 13:48:35
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -7,20 +7,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.44
|
||||
Virtual_time_in_minutes: 0.00733333
|
||||
Virtual_time_in_hours: 0.000122222
|
||||
Virtual_time_in_days: 5.09259e-06
|
||||
Virtual_time_in_seconds: 0.41
|
||||
Virtual_time_in_minutes: 0.00683333
|
||||
Virtual_time_in_hours: 0.000113889
|
||||
Virtual_time_in_days: 4.74537e-06
|
||||
|
||||
Ruby_current_time: 280571
|
||||
Ruby_current_time: 221941
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 280571
|
||||
Ruby_cycles: 221941
|
||||
|
||||
mbytes_resident: 41.2305
|
||||
mbytes_total: 224.867
|
||||
resident_ratio: 0.18339
|
||||
mbytes_resident: 43.6133
|
||||
mbytes_total: 254.102
|
||||
resident_ratio: 0.171699
|
||||
|
||||
ruby_cycles_executed: [ 280572 ]
|
||||
ruby_cycles_executed: [ 221942 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -29,16 +29,16 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1000 average: 15.774 | standard deviation: 1.14469 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 8 93 886 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.7379 | standard deviation: 1.20089 | 0 1 1 1 1 1 1 2 1 1 1 1 1 1 9 110 836 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 6185 count: 986 average: 4512.83 | standard deviation: 564.917 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 3 0 1 1 2 5 4 6 5 8 7 2 12 9 11 7 16 19 21 19 24 15 26 28 20 22 22 30 33 30 27 30 31 27 29 27 19 18 31 35 23 21 29 18 15 18 17 12 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 6185 count: 886 average: 4517.13 | standard deviation: 578.837 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 2 0 1 1 2 5 4 6 4 6 4 2 12 9 10 5 15 13 17 16 20 14 20 25 18 21 19 29 32 26 25 26 30 26 26 25 16 17 28 32 21 17 25 17 14 15 16 11 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5314 count: 57 average: 4436.05 | standard deviation: 407.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 5682 count: 39 average: 3989.69 | standard deviation: 543.603 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 2 0 0 1 0 2 1 1 2 1 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6185 count: 947 average: 4534.38 | standard deviation: 555.581 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 3 7 6 2 9 8 11 7 16 19 20 17 24 15 26 26 19 20 22 29 33 30 25 30 30 27 29 27 18 18 29 35 23 21 29 18 15 18 17 11 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency: [binsize: 32 max: 5298 count: 954 average: 3683.39 | standard deviation: 578.018 | 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 2 0 1 2 1 0 0 4 1 1 3 4 7 5 7 8 7 5 12 10 2 14 13 15 12 17 17 14 19 13 18 33 11 18 28 22 17 19 33 19 21 25 18 14 24 16 14 26 22 18 13 28 16 20 20 19 12 15 20 16 17 12 14 11 10 14 7 5 6 12 1 4 6 2 1 1 0 0 2 2 0 0 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4587 count: 42 average: 3722.1 | standard deviation: 463.961 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 4 0 1 1 0 0 1 0 0 1 2 1 0 0 2 0 0 5 1 1 0 0 4 1 2 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 5298 count: 854 average: 3677.29 | standard deviation: 585.222 | 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 2 0 1 2 1 0 0 3 1 1 3 4 7 5 6 6 6 5 11 6 2 12 12 15 9 15 13 14 18 11 16 33 7 17 27 19 14 18 32 19 18 23 17 8 22 15 14 24 16 14 10 27 14 18 20 17 11 13 19 15 13 11 13 11 9 13 5 4 5 9 0 4 6 2 1 1 0 0 2 2 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5106 count: 58 average: 3745.14 | standard deviation: 548.056 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 3 0 1 1 0 3 2 0 0 0 1 2 0 3 1 1 2 1 0 1 0 1 2 1 1 1 0 0 2 2 3 1 1 1 1 0 1 0 2 1 1 3 0 0 0 1 1 2 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4375 count: 38 average: 3245.53 | standard deviation: 508.825 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 2 1 0 2 2 1 2 1 2 1 0 0 0 0 1 2 0 0 3 1 3 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 5298 count: 916 average: 3701.55 | standard deviation: 573.776 | 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 4 1 1 2 3 7 4 7 6 6 5 10 8 1 12 12 13 11 17 17 14 19 12 16 33 11 15 27 19 17 19 33 19 21 24 17 14 23 16 13 25 22 18 13 28 16 20 20 19 11 15 19 16 17 12 13 11 10 14 7 5 6 12 1 4 6 2 1 1 0 0 2 2 0 0 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -48,12 +48,12 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 947
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 5682 count: 37 average: 4008.19 | standard deviation: 551.275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 2 1 1 2 0 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6185 count: 849 average: 4539.31 | standard deviation: 570.066 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 2 6 3 2 9 8 10 5 15 13 16 14 20 14 20 23 17 19 19 28 32 26 23 26 29 26 26 25 15 17 26 32 21 17 25 17 14 15 16 10 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3792 count: 2 average: 3647.5 | standard deviation: 204.355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5314 count: 55 average: 4464.73 | standard deviation: 384.051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 916
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4587 count: 42 average: 3722.1 | standard deviation: 463.961 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 4 0 1 1 0 0 1 0 0 1 2 1 0 0 2 0 0 5 1 1 0 0 4 1 2 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 4375 count: 36 average: 3241 | standard deviation: 520.843 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 2 1 0 2 2 1 2 1 2 0 0 0 0 0 1 2 0 0 3 1 2 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 5298 count: 818 average: 3696.49 | standard deviation: 580.688 | 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 3 1 1 2 3 7 4 6 4 5 5 9 4 1 10 11 13 9 15 13 14 18 10 14 33 7 14 26 17 14 18 32 19 18 22 16 8 21 15 13 23 16 14 10 27 14 18 20 17 10 13 18 15 13 11 12 11 9 13 5 4 5 9 0 4 6 2 1 1 0 0 2 2 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3515 count: 2 average: 3327 | standard deviation: 265.872 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5106 count: 56 average: 3760.07 | standard deviation: 550.834 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 3 0 1 1 0 2 2 0 0 0 1 2 0 3 1 1 1 1 0 1 0 1 2 1 1 1 0 0 2 2 3 1 1 1 1 0 1 0 2 1 1 3 0 0 0 1 1 2 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -67,11 +67,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 12 count: 1828 average: 0.280088 | standard deviation: 1.03285 | 1658 32 43 46 23 10 9 2 2 2 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 12 count: 1828 average: 0.280088 | standard deviation: 1.03285 | 1658 32 43 46 23 10 9 2 2 2 0 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 947 average: 0.198522 | standard deviation: 0.78638 | 871 19 27 18 5 5 0 0 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 943 average: 0.0816543 | standard deviation: 0.596344 | 921 2 5 7 2 3 1 1 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 7 count: 916 average: 0.265284 | standard deviation: 0.915561 | 824 19 30 28 3 6 4 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 12 count: 912 average: 0.294956 | standard deviation: 1.13907 | 834 13 13 18 20 4 5 0 2 2 0 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,83 +85,83 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 11714
|
||||
page_reclaims: 8164
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 80
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 2841 22728
|
||||
total_msg_count_Data: 2833 203976
|
||||
total_msg_count_Response_Data: 2841 204552
|
||||
total_msg_count_Writeback_Control: 2829 22632
|
||||
total_msgs: 11344 total_bytes: 453888
|
||||
total_msg_count_Control: 2748 21984
|
||||
total_msg_count_Data: 2742 197424
|
||||
total_msg_count_Response_Data: 2748 197856
|
||||
total_msg_count_Writeback_Control: 2739 21912
|
||||
total_msgs: 10977 total_bytes: 439176
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.68505
|
||||
links_utilized_percent_switch_0_link_0: 1.68692 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.68317 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.06125
|
||||
links_utilized_percent_switch_0_link_0: 2.06294 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.05956 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 945 68040 [ 0 0 945 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 913 7304 [ 0 0 0 913 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 1.68487
|
||||
links_utilized_percent_switch_1_link_0: 1.68282 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.68692 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.06125
|
||||
links_utilized_percent_switch_1_link_0: 2.05956 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.06294 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 913 7304 [ 0 0 0 913 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.68487
|
||||
links_utilized_percent_switch_2_link_0: 1.68692 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.68282 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 2.06125
|
||||
links_utilized_percent_switch_2_link_0: 2.06294 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.05956 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 913 7304 [ 0 0 0 913 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 949
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 949
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 917
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 917
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 4.63646%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 89.568%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 5.79557%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 4.58015%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 89.313%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 6.10687%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 949 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 917 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [44 ] 44
|
||||
Ifetch [57 ] 57
|
||||
Store [887 ] 887
|
||||
Data [947 ] 947
|
||||
Load [42 ] 42
|
||||
Ifetch [58 ] 58
|
||||
Store [855 ] 855
|
||||
Data [916 ] 916
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [946 ] 946
|
||||
Writeback_Ack [943 ] 943
|
||||
Replacement [914 ] 914
|
||||
Writeback_Ack [912 ] 912
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [44 ] 44
|
||||
I Ifetch [55 ] 55
|
||||
I Store [850 ] 850
|
||||
I Load [42 ] 42
|
||||
I Ifetch [56 ] 56
|
||||
I Store [819 ] 819
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
|
|
@ -169,61 +169,61 @@ II Writeback_Nack [0 ] 0
|
|||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [2 ] 2
|
||||
M Store [37 ] 37
|
||||
M Store [36 ] 36
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [946 ] 946
|
||||
M Replacement [914 ] 914
|
||||
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [943 ] 943
|
||||
MI Writeback_Ack [912 ] 912
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data [98 ] 98
|
||||
|
||||
IM Data [849 ] 849
|
||||
IM Data [818 ] 818
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1891
|
||||
memory_reads: 947
|
||||
memory_writes: 944
|
||||
memory_refreshes: 585
|
||||
memory_total_request_delays: 2814
|
||||
memory_delays_per_request: 1.4881
|
||||
memory_delays_in_input_queue: 676
|
||||
memory_delays_behind_head_of_bank_queue: 12
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2126
|
||||
memory_stalls_for_bank_busy: 294
|
||||
memory_total_requests: 1830
|
||||
memory_reads: 916
|
||||
memory_writes: 914
|
||||
memory_refreshes: 1542
|
||||
memory_total_request_delays: 1930
|
||||
memory_delays_per_request: 1.05464
|
||||
memory_delays_in_input_queue: 182
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1745
|
||||
memory_stalls_for_bank_busy: 343
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 265
|
||||
memory_stalls_for_bus: 935
|
||||
memory_stalls_for_arbitration: 167
|
||||
memory_stalls_for_bus: 617
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 518
|
||||
memory_stalls_for_read_read_turnaround: 114
|
||||
accesses_per_bank: 46 50 40 88 149 74 58 50 50 48 58 62 54 60 56 58 60 62 54 54 63 54 56 44 54 77 52 48 46 62 46 58
|
||||
memory_stalls_for_read_write_turnaround: 556
|
||||
memory_stalls_for_read_read_turnaround: 62
|
||||
accesses_per_bank: 64 60 44 96 107 64 62 38 55 54 54 36 48 34 66 48 56 54 60 70 56 62 44 62 48 58 64 72 46 46 36 66
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [947 ] 947
|
||||
GETX [916 ] 916
|
||||
GETS [0 ] 0
|
||||
PUTX [944 ] 944
|
||||
PUTX [914 ] 914
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [947 ] 947
|
||||
Memory_Ack [944 ] 944
|
||||
Memory_Data [916 ] 916
|
||||
Memory_Ack [914 ] 914
|
||||
|
||||
- Transitions -
|
||||
I GETX [947 ] 947
|
||||
I GETX [916 ] 916
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [0 ] 0
|
||||
M PUTX [944 ] 944
|
||||
M PUTX [914 ] 914
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
|
@ -246,7 +246,7 @@ IM PUTX [0 ] 0
|
|||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [947 ] 947
|
||||
IM Memory_Data [916 ] 916
|
||||
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
|
|
@ -254,7 +254,7 @@ MI PUTX [0 ] 0
|
|||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [944 ] 944
|
||||
MI Memory_Ack [914 ] 914
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 10 2012 16:32:12
|
||||
gem5 started Jul 10 2012 17:29:08
|
||||
gem5 executing on sc2b0605
|
||||
gem5 compiled Sep 1 2012 13:41:29
|
||||
gem5 started Sep 1 2012 13:48:35
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 280571 because Ruby Tester completed
|
||||
Exiting @ tick 221941 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000281 # Number of seconds simulated
|
||||
sim_ticks 280571 # Number of ticks simulated
|
||||
final_tick 280571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000222 # Number of seconds simulated
|
||||
sim_ticks 221941 # Number of ticks simulated
|
||||
final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 2647246 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230268 # Number of bytes of host memory used
|
||||
host_tick_rate 2057251 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260204 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
|
|
|
|||
Loading…
Reference in a new issue