EIO: update stats (mostly order change, some renames)
This commit is contained in:
Steve Reinhardt
parent
5917fb3292
commit
13e14ba93c
16 changed files with 2338 additions and 2034 deletions
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
children=dtb interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -37,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -44,13 +57,16 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -76,7 +92,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -86,5 +103,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 11:52:53
|
||||
M5 started Apr 19 2011 11:58:24
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
|
||||
gem5 compiled Feb 29 2012 00:47:21
|
||||
gem5 started Feb 29 2012 00:51:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
main dictionary has 1245 entries
|
||||
|
|
|
|||
|
|
@ -1,66 +1,80 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 5358491 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 194108 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 2674844665 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500001 # Number of instructions simulated
|
||||
sim_seconds 0.000250 # Number of seconds simulated
|
||||
sim_ticks 250015500 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 180793 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 180775 # DTB hits
|
||||
system.cpu.dtb.data_misses 18 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3174528 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 203780 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 500001 # Number of instructions simulated
|
||||
sim_ops 500001 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2872676 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 417562 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 624454 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 56340 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 124443 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 124435 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 56350 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 124443 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 56340 # DTB write hits
|
||||
system.cpu.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 500032 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 56350 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 180775 # DTB hits
|
||||
system.cpu.dtb.data_misses 18 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 180793 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 500019 # ITB hits
|
||||
system.cpu.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 500032 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 500032 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 32 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 14357 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 500001 # Number of instructions executed
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 500001 # Number of instructions committed
|
||||
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 14357 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 474689 # number of integer instructions
|
||||
system.cpu.num_fp_insts 32 # number of float instructions
|
||||
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 124443 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 180793 # number of memory refs
|
||||
system.cpu.num_load_insts 124443 # Number of load instructions
|
||||
system.cpu.num_store_insts 56350 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 500032 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -37,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
|
|
@ -55,26 +68,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=262144
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -91,26 +97,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=131072
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -127,26 +129,19 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=2097152
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -156,7 +151,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -179,7 +175,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -189,5 +186,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 11:52:53
|
||||
M5 started Apr 19 2011 11:58:24
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
|
||||
gem5 compiled Feb 29 2012 00:47:21
|
||||
gem5 started Feb 29 2012 00:51:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
main dictionary has 1245 entries
|
||||
|
|
|
|||
|
|
@ -1,249 +1,330 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2553874 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201796 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 3714828011 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500001 # Number of instructions simulated
|
||||
sim_seconds 0.000728 # Number of seconds simulated
|
||||
sim_ticks 727929000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.070111 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 454 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dtb.data_accesses 180793 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 180775 # DTB hits
|
||||
system.cpu.dtb.data_misses 18 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
final_tick 727929000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1742138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1742023 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2535976572 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212652 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
sim_insts 500001 # Number of instructions simulated
|
||||
sim_ops 500001 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 54848 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 25792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 857 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 75348008 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 35432027 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 75348008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 124443 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 124435 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 56350 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 124443 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 56340 # DTB write hits
|
||||
system.cpu.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.129371 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 499617 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 403 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 500033 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 56350 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 180775 # DTB hits
|
||||
system.cpu.dtb.data_misses 18 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 180793 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 500020 # ITB hits
|
||||
system.cpu.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 500033 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.014692 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 857 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 1455858 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 1455858 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 32 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 14357 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 500001 # Number of instructions executed
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 500001 # Number of instructions committed
|
||||
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 14357 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 474689 # number of integer instructions
|
||||
system.cpu.num_fp_insts 32 # number of float instructions
|
||||
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 124443 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 180793 # number of memory refs
|
||||
system.cpu.num_load_insts 124443 # Number of load instructions
|
||||
system.cpu.num_store_insts 56350 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1455858 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 264.952126 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.129371 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.129371 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 499617 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 403 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 22568000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 22568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 22568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 22568000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 22568000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21359000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21359000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21359000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21359000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 287.175167 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.070111 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.070111 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 180321 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 454 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 17640000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 17640000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7784000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7784000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 25424000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 25424000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 25424000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 25424000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 264.958770 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 216.460700 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.008086 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.006606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.014692 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20956000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16380000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 37336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7228000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7228000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 23608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 44564000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20956000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 23608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 44564000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 34280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -37,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -58,26 +71,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.port[2]
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -94,26 +100,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.port[1]
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -134,16 +136,18 @@ system=system
|
|||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -151,6 +155,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -172,26 +177,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.port[4]
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -208,26 +206,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.port[3]
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -248,16 +242,18 @@ system=system
|
|||
|
||||
[system.cpu2]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=2
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu2.interrupts
|
||||
itb=system.cpu2.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -265,6 +261,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -286,26 +283,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.dcache_port
|
||||
mem_side=system.toL2Bus.port[6]
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -322,26 +312,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.icache_port
|
||||
mem_side=system.toL2Bus.port[5]
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -362,16 +348,18 @@ system=system
|
|||
|
||||
[system.cpu3]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=3
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu3.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu3.interrupts
|
||||
itb=system.cpu3.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -379,6 +367,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
|
|
@ -400,26 +389,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.dcache_port
|
||||
mem_side=system.toL2Bus.port[8]
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu3.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -436,26 +418,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.icache_port
|
||||
mem_side=system.toL2Bus.port[7]
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu3.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu3.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -485,26 +463,19 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
num_cpus=4
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[0]
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -514,7 +485,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.l2c.mem_side system.physmem.port[0]
|
||||
master=system.physmem.port[0]
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -524,7 +496,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:1073741823
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -534,5 +506,6 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 11:52:53
|
||||
M5 started Apr 19 2011 11:58:24
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
|
||||
gem5 compiled Feb 29 2012 00:47:21
|
||||
gem5 started Feb 29 2012 00:51:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
main dictionary has 1245 entries
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
|
@ -8,8 +9,16 @@ time_sync_spin_threshold=100000000
|
|||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -17,19 +26,22 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu0]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -37,6 +49,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
|
|
@ -55,26 +68,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
mem_side=system.toL2Bus.port[2]
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -91,26 +97,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
mem_side=system.toL2Bus.port[1]
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -131,16 +133,18 @@ system=system
|
|||
|
||||
[system.cpu1]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -148,6 +152,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
|
|
@ -166,26 +171,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.toL2Bus.port[4]
|
||||
mem_side=system.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -202,26 +200,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.toL2Bus.port[3]
|
||||
mem_side=system.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -242,16 +236,18 @@ system=system
|
|||
|
||||
[system.cpu2]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=2
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu2.interrupts
|
||||
itb=system.cpu2.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -259,6 +255,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
|
|
@ -277,26 +274,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.dcache_port
|
||||
mem_side=system.toL2Bus.port[6]
|
||||
mem_side=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -313,26 +303,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.icache_port
|
||||
mem_side=system.toL2Bus.port[5]
|
||||
mem_side=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu2.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -353,16 +339,18 @@ system=system
|
|||
|
||||
[system.cpu3]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb tracer workload
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=3
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu3.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu3.interrupts
|
||||
itb=system.cpu3.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
|
|
@ -370,6 +358,7 @@ max_loads_all_threads=0
|
|||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu3.tracer
|
||||
|
|
@ -388,26 +377,19 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.dcache_port
|
||||
mem_side=system.toL2Bus.port[8]
|
||||
mem_side=system.toL2Bus.slave[7]
|
||||
|
||||
[system.cpu3.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -424,26 +406,22 @@ is_top_level=true
|
|||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
num_cpus=1
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.icache_port
|
||||
mem_side=system.toL2Bus.port[7]
|
||||
mem_side=system.toL2Bus.slave[6]
|
||||
|
||||
[system.cpu3.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu3.itb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -473,26 +451,19 @@ is_top_level=false
|
|||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
num_cpus=4
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=100000
|
||||
prefetch_on_access=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[0]
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[0]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -502,7 +473,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.l2c.mem_side system.physmem.port[0]
|
||||
master=system.physmem.port[0]
|
||||
slave=system.l2c.mem_side system.system_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -512,7 +484,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -522,5 +494,6 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,6 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
hack: be nice to actually delete the event here
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
@ -11,5 +8,3 @@ gzip: stdout: Broken pipe
|
|||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 11:52:53
|
||||
M5 started Apr 19 2011 12:04:57
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
gem5 compiled Feb 29 2012 00:47:21
|
||||
gem5 started Feb 29 2012 00:51:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
main dictionary has 1245 entries
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue