MIPS: Update MIPS stats for cleaned up operand checks.
This commit is contained in:
Gabe Black
parent
a1ad9e652a
commit
c5fd6f4fec
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@ -102,6 +102,7 @@ smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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squashWidth=8
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store_set_clear_period=250000
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system=system
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tracer=system.cpu.tracer
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trapLatency=13
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@ -499,7 +500,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
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executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -1,9 +1,9 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jul 15 2011 17:48:05
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gem5 started Jul 15 2011 20:13:48
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gem5 executing on u200439-lin.austin.arm.com
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gem5 compiled Sep 9 2011 01:24:08
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gem5 started Sep 9 2011 01:24:15
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gem5 executing on chips
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command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -3,10 +3,10 @@
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 12273500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 33014 # Simulator instruction rate (inst/s)
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host_tick_rate 78373339 # Simulator tick rate (ticks/s)
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host_mem_usage 244788 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
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host_inst_rate 39169 # Simulator instruction rate (inst/s)
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host_tick_rate 92983194 # Simulator tick rate (ticks/s)
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host_mem_usage 242872 # Number of bytes of host memory used
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host_seconds 0.13 # Real time elapsed on the host
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sim_insts 5169 # Number of instructions simulated
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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@ -86,9 +86,9 @@ system.cpu.rename.UnblockCycles 111 # Nu
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system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename
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system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made
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system.cpu.rename.RenameLookups 13124 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups
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system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
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@ -290,7 +290,7 @@ system.cpu.int_regfile_reads 10287 # nu
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system.cpu.int_regfile_writes 4991 # number of integer regfile writes
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system.cpu.fp_regfile_reads 3 # number of floating regfile reads
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system.cpu.fp_regfile_writes 1 # number of floating regfile writes
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system.cpu.misc_regfile_reads 154 # number of misc regfile reads
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system.cpu.misc_regfile_reads 153 # number of misc regfile reads
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system.cpu.icache.replacements 17 # number of replacements
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system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use
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system.cpu.icache.total_refs 1364 # Total number of references to valid blocks.
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@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -1,3 +1,2 @@
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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hack: be nice to actually delete the event here
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@ -1,14 +1,10 @@
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M5 Simulator System
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Apr 19 2011 12:18:54
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M5 started Apr 19 2011 12:18:58
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M5 executing on maize
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command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
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gem5 compiled Sep 9 2011 01:24:08
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gem5 started Sep 9 2011 01:24:15
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gem5 executing on chips
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command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -1,52 +1,52 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 798153 # Simulator instruction rate (inst/s)
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host_mem_usage 195780 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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host_tick_rate 390049435 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5827 # Number of instructions simulated
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 2913500 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 550881 # Simulator instruction rate (inst/s)
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host_tick_rate 274282730 # Simulator tick rate (ticks/s)
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host_mem_usage 232848 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 5827 # Number of instructions simulated
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.numCycles 5828 # number of cpu cycles simulated
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 5828 # Number of busy cycles
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system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
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system.cpu.num_fp_insts 2 # number of float instructions
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system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
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system.cpu.num_func_calls 194 # number of times a function call or return occured
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 5827 # Number of instructions executed
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system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
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system.cpu.num_func_calls 194 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
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system.cpu.num_int_insts 5126 # number of integer instructions
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system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
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system.cpu.num_fp_insts 2 # number of float instructions
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system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
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system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
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system.cpu.num_load_insts 1164 # Number of load instructions
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system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
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system.cpu.num_mem_refs 2090 # number of memory refs
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system.cpu.num_load_insts 1164 # Number of load instructions
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system.cpu.num_store_insts 926 # Number of store instructions
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 5828 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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---------- End Simulation Statistics ----------
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@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
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type=System
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children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
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mem_mode=timing
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memories=system.physmem
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -41,8 +42,8 @@ progress_interval=0
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.ruby.cpu_ruby_ports.port[1]
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icache_port=system.ruby.cpu_ruby_ports.port[0]
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dcache_port=system.l1_cntrl0.sequencer.port[1]
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icache_port=system.l1_cntrl0.sequencer.port[0]
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[system.cpu.dtb]
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type=MipsTLB
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@ -78,11 +79,13 @@ uid=100
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type=Directory_Controller
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children=directory memBuffer
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buffer_size=0
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cntrl_id=1
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directory=system.dir_cntrl0.directory
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directory_latency=12
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memBuffer=system.dir_cntrl0.memBuffer
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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transitions_per_cycle=32
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version=0
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@ -117,16 +120,42 @@ version=0
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[system.l1_cntrl0]
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type=L1Cache_Controller
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children=cacheMemory sequencer
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buffer_size=0
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cacheMemory=system.ruby.cpu_ruby_ports.dcache
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cacheMemory=system.l1_cntrl0.cacheMemory
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cache_response_latency=12
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cntrl_id=0
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issue_latency=2
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number_of_TBEs=256
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recycle_latency=10
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sequencer=system.ruby.cpu_ruby_ports
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ruby_system=system.ruby
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sequencer=system.l1_cntrl0.sequencer
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transitions_per_cycle=32
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version=0
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[system.l1_cntrl0.cacheMemory]
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type=RubyCache
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assoc=2
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latency=3
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.l1_cntrl0.sequencer]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.cacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.cacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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file=
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@ -135,44 +164,18 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.ruby.cpu_ruby_ports.physMemPort
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port=system.l1_cntrl0.sequencer.physMemPort
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[system.ruby]
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type=RubySystem
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children=cpu_ruby_ports network profiler tracer
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children=network profiler tracer
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block_size_bytes=64
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clock=1
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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profiler=system.ruby.profiler
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random_seed=1234
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randomization=false
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stats_filename=ruby.stats
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tracer=system.ruby.tracer
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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children=dcache
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access_phys_mem=true
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dcache=system.ruby.cpu_ruby_ports.dcache
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deadlock_threshold=500000
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icache=system.ruby.cpu_ruby_ports.dcache
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max_outstanding_requests=16
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physmem=system.physmem
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.ruby.cpu_ruby_ports.dcache]
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type=RubyCache
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assoc=2
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latency=3
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.ruby.network]
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type=SimpleNetwork
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@ -180,59 +183,77 @@ children=topology
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adaptive_routing=false
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buffer_size=0
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control_msg_size=8
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endpoint_bandwidth=10000
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link_latency=1
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endpoint_bandwidth=1000
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number_of_virtual_networks=10
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ruby_system=system.ruby
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topology=system.ruby.network.topology
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[system.ruby.network.topology]
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type=Topology
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children=ext_links0 ext_links1 int_links0 int_links1
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children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
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description=Crossbar
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ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
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int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
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num_int_nodes=3
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print_config=false
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routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
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[system.ruby.network.topology.ext_links0]
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type=ExtLink
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bw_multiplier=64
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type=SimpleExtLink
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bandwidth_factor=16
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ext_node=system.l1_cntrl0
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int_node=0
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int_node=system.ruby.network.topology.routers0
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latency=1
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link_id=0
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weight=1
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[system.ruby.network.topology.ext_links1]
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type=ExtLink
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bw_multiplier=64
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type=SimpleExtLink
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bandwidth_factor=16
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ext_node=system.dir_cntrl0
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int_node=1
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int_node=system.ruby.network.topology.routers1
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latency=1
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link_id=1
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weight=1
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[system.ruby.network.topology.int_links0]
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type=IntLink
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bw_multiplier=16
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type=SimpleIntLink
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bandwidth_factor=16
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latency=1
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node_a=0
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node_b=2
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link_id=2
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node_a=system.ruby.network.topology.routers0
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node_b=system.ruby.network.topology.routers2
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weight=1
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[system.ruby.network.topology.int_links1]
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type=IntLink
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bw_multiplier=16
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type=SimpleIntLink
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bandwidth_factor=16
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||||
latency=1
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node_a=1
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node_b=2
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link_id=3
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node_a=system.ruby.network.topology.routers1
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node_b=system.ruby.network.topology.routers2
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weight=1
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[system.ruby.network.topology.routers0]
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type=BasicRouter
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||||
router_id=0
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||||
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||||
[system.ruby.network.topology.routers1]
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||||
type=BasicRouter
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||||
router_id=1
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[system.ruby.network.topology.routers2]
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type=BasicRouter
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router_id=2
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[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
ruby_system=system.ruby
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:18:54
|
||||
M5 started Apr 19 2011 12:18:57
|
||||
M5 executing on maize
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
|
||||
gem5 compiled Sep 9 2011 01:24:08
|
||||
gem5 started Sep 9 2011 01:24:15
|
||||
gem5 executing on chips
|
||||
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,52 +1,52 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 81519 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213976 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 4090793 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000293 # Number of seconds simulated
|
||||
sim_ticks 292960 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24172 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1215173 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251116 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 292960 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 292960 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 5126 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2090 # number of memory refs
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 292960 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:18:54
|
||||
M5 started Apr 19 2011 12:18:57
|
||||
M5 executing on maize
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
|
||||
gem5 compiled Sep 9 2011 01:24:08
|
||||
gem5 started Sep 9 2011 01:24:15
|
||||
gem5 executing on chips
|
||||
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,236 +1,236 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 524923 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203516 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 2843944401 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000032 # Number of seconds simulated
|
||||
sim_ticks 32088000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1951 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 138 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 266984 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1467506046 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241568 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5526 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 439 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.numCycles 64176 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 64176 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 5126 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
|
||||
system.cpu.num_fp_insts 2 # number of float instructions
|
||||
system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2090 # number of memory refs
|
||||
system.cpu.num_load_insts 1164 # Number of load instructions
|
||||
system.cpu.num_store_insts 926 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 8 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 64176 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 5526 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 1951 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 138 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 439 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue