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stats: update stats for icache change not allowing dirty data

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This commit is contained in:
Ali Saidi 2012-07-27 16:08:05 -04:00
parent 630068be6f
commit b1a58933e0
108 changed files with 9834 additions and 12302 deletions
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2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -1005,7 +1005,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

9
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 11:07:21
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 22:30:48
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 112168000
Exiting @ tick 1900530800500 because m5_exit instruction encountered
Exiting @ tick 1900530295500 because m5_exit instruction encountered

2568
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -581,7 +581,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

9
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 11:00:25
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 22:30:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1865402113500 because m5_exit instruction encountered
Exiting @ tick 1864423957500 because m5_exit instruction encountered

1424
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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File diff suppressed because it is too large Load diff

4
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -168,7 +168,7 @@ type=O3Checker
children=dtb itb tracer
checker=Null
clock=1
cpu_id=-1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
@ -640,7 +640,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

33
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -4,31 +4,8 @@ warn: Sockets disabled, not accepting gdb connections
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: The ccsidr register isn't implemented and always reads as 0.
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here
panic: Not supported on checker!
@ cycle 197694500
[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130]
Memory Usage: 355632 KBytes
Program aborted at cycle 197694500

7
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 17:05:39
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 02:25:32
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2502549875500 because m5_exit instruction encountered

978
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -1,978 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.502550 # Number of seconds simulated
sim_ticks 2502549875500 # Number of ticks simulated
final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 75474 # Simulator instruction rate (inst/s)
host_op_rate 97450 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3170228022 # Simulator tick rate (ticks/s)
host_mem_usage 386888 # Number of bytes of host memory used
host_seconds 789.39 # Real time elapsed on the host
sim_insts 59578267 # Number of instructions simulated
sim_ops 76925839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory
system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 64431 # number of replacements
system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use
system.l2c.total_refs 2028510 # Total number of references to valid blocks.
system.l2c.sampled_refs 129827 # Sample count of references to valid blocks.
system.l2c.avg_refs 15.624716 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits
system.l2c.Writeback_hits::total 675442 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits
system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits
system.l2c.overall_hits::cpu.inst 977935 # number of overall hits
system.l2c.overall_hits::cpu.data 496445 # number of overall hits
system.l2c.overall_hits::total 1608169 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses
system.l2c.demand_misses::total 156364 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses
system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu.inst 12384 # number of overall misses
system.l2c.overall_misses::cpu.data 143920 # number of overall misses
system.l2c.overall_misses::total 156364 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 59159 # number of writebacks
system.l2c.writebacks::total 59159 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 15048164 # DTB read hits
system.cpu.checker.dtb.read_misses 7309 # DTB read misses
system.cpu.checker.dtb.write_hits 11293826 # DTB write hits
system.cpu.checker.dtb.write_misses 2190 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses
system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 26341990 # DTB hits
system.cpu.checker.dtb.misses 9499 # DTB misses
system.cpu.checker.dtb.accesses 26351489 # DTB accesses
system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses
system.cpu.checker.itb.hits 60744881 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
system.cpu.checker.itb.accesses 60749352 # DTB accesses
system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 51771660 # DTB read hits
system.cpu.dtb.read_misses 81258 # DTB read misses
system.cpu.dtb.write_hits 11880398 # DTB write hits
system.cpu.dtb.write_misses 17961 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51852918 # DTB read accesses
system.cpu.dtb.write_accesses 11898359 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 63652058 # DTB hits
system.cpu.dtb.misses 99219 # DTB misses
system.cpu.dtb.accesses 63751277 # DTB accesses
system.cpu.itb.inst_hits 13142261 # ITB inst hits
system.cpu.itb.inst_misses 12247 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 13154508 # ITB inst accesses
system.cpu.itb.hits 13142261 # DTB hits
system.cpu.itb.misses 12247 # DTB misses
system.cpu.itb.accesses 13154508 # DTB accesses
system.cpu.numCycles 413642740 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued
system.cpu.iq.rate 0.301258 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 256054 # number of nop insts executed
system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed
system.cpu.iew.exec_branches 11412736 # Number of branches executed
system.cpu.iew.exec_stores 12391364 # Number of stores executed
system.cpu.iew.exec_rate 0.293583 # Inst execution rate
system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back
system.cpu.iew.wb_producers 46459932 # num instructions producing a value
system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions
system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle
system.cpu.commit.committedInsts 59728648 # Number of instructions committed
system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27513345 # Number of memory references committed
system.cpu.commit.loads 15715170 # Number of loads committed
system.cpu.commit.membars 413057 # Number of memory barriers committed
system.cpu.commit.branches 9904308 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
system.cpu.commit.int_insts 68616986 # Number of committed integer instructions.
system.cpu.commit.function_calls 995953 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 246021016 # The number of ROB reads
system.cpu.rob.rob_writes 206855771 # The number of ROB writes
system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 59578267 # Number of Instructions Simulated
system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated
system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads
system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 551124725 # number of integer regfile reads
system.cpu.int_regfile_writes 87730819 # number of integer regfile writes
system.cpu.fp_regfile_reads 8186 # number of floating regfile reads
system.cpu.fp_regfile_writes 2858 # number of floating regfile writes
system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads
system.cpu.misc_regfile_writes 912697 # number of misc regfile writes
system.cpu.icache.replacements 991190 # number of replacements
system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use
system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits
system.cpu.icache.overall_hits::total 12061455 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses
system.cpu.icache.overall_misses::total 1076423 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 67899 # number of writebacks
system.cpu.icache.writebacks::total 67899 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 643139 # number of replacements
system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use
system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits
system.cpu.dcache.overall_hits::total 21161261 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses
system.cpu.dcache.overall_misses::total 3758563 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks
system.cpu.dcache.writebacks::total 607543 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed
---------- End Simulation Statistics ----------

4
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.realview.nvmem system.physmem
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
@ -1023,7 +1023,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View file

@ -10,10 +10,10 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 17:16:08
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 02:25:35
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2581527583500 because m5_exit instruction encountered
Exiting @ tick 2582310281500 because m5_exit instruction encountered

2810
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -581,7 +581,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 17:04:56
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 02:23:14
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2502549875500 because m5_exit instruction encountered
Exiting @ tick 2503329223500 because m5_exit instruction encountered

1462
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@ -1261,7 +1261,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1281,7 +1281,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

12
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,15 +1,13 @@
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 22 2012 08:05:39
gem5 started Jul 22 2012 08:05:57
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jul 26 2012 21:30:36
gem5 started Jul 27 2012 00:44:18
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5172902281500 because m5_exit instruction encountered
Exiting @ tick 5172910256500 because m5_exit instruction encountered

1658
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

123
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@ -642,30 +642,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -706,30 +696,20 @@ version=1
[system.l1_cntrl1.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.sequencer]
type=RubySequencer
@ -766,16 +746,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=4194304
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.pc]
type=Pc
@ -1020,7 +995,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1040,7 +1015,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
@ -1215,9 +1190,9 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=true
width=8
width=64
default=system.pc.pciconfig.pio
master=system.physmem.port system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master
[system.ruby]
@ -1244,104 +1219,74 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl1
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.ext_links3]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links3.int_node
int_node=system.ruby.network.topology.routers3
latency=1
link_id=3
weight=1
[system.ruby.network.topology.ext_links3.int_node]
type=BasicRouter
router_id=3
[system.ruby.network.topology.ext_links4]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dma_cntrl0
int_node=system.ruby.network.topology.ext_links4.int_node
int_node=system.ruby.network.topology.routers4
latency=1
link_id=4
weight=1
[system.ruby.network.topology.ext_links4.int_node]
type=BasicRouter
router_id=4
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers5
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=5
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=6
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers5
weight=1
[system.ruby.network.topology.int_links2]
@ -1349,8 +1294,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=7
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers5
weight=1
[system.ruby.network.topology.int_links3]
@ -1358,8 +1303,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=8
node_a=system.ruby.network.topology.ext_links3.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers3
node_b=system.ruby.network.topology.routers5
weight=1
[system.ruby.network.topology.int_links4]
@ -1367,10 +1312,34 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=9
node_a=system.ruby.network.topology.ext_links4.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers4
node_b=system.ruby.network.topology.routers5
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.network.topology.routers4]
type=BasicRouter
router_id=4
[system.ruby.network.topology.routers5]
type=BasicRouter
router_id=5
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

2
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
View file

@ -3,10 +3,8 @@ warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: instruction 'wbinvd' unimplemented
warn: instruction 'wbinvd' unimplemented
warn: x86 cpuid: unknown family 0x8086
hack: Assuming logical destinations are 1 << id.
warn: Tried to clear PCI interrupt 14
warn: Unknown mouse command 0xe1.

12
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,15 +1,13 @@
Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 22 2012 08:55:10
gem5 started Jul 22 2012 08:55:16
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jun 4 2012 13:44:12
gem5 started Jun 4 2012 17:11:29
gem5 executing on zizzer
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5305568377500 because m5_exit instruction encountered
Exiting @ tick 5304689685500 because m5_exit instruction encountered

222
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -1,107 +1,77 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.305568 # Number of seconds simulated
sim_ticks 5305568377500 # Number of ticks simulated
final_tick 5305568377500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 5.304690 # Number of seconds simulated
sim_ticks 5304689685500 # Number of ticks simulated
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 148548 # Simulator instruction rate (inst/s)
host_op_rate 304739 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5673062484 # Simulator tick rate (ticks/s)
host_mem_usage 518516 # Number of bytes of host memory used
host_seconds 935.22 # Real time elapsed on the host
sim_insts 138925597 # Number of instructions simulated
sim_ops 284998538 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 843619360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 40106316 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 468873856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 53484588 # Number of bytes read from this memory
system.physmem.bytes_read::total 1406451096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 843619360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 468873856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1312493216 # Number of instructions bytes read from this memory
host_inst_rate 163049 # Simulator instruction rate (inst/s)
host_op_rate 333085 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6301127704 # Simulator tick rate (ticks/s)
host_mem_usage 481488 # Number of bytes of host memory used
host_seconds 841.86 # Real time elapsed on the host
sim_insts 137264752 # Number of instructions simulated
sim_ops 280412254 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory
system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 32433610 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 35512400 # Number of bytes written to this memory
system.physmem.bytes_written::total 70937130 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 105452420 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 6721793 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 58609232 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 8980167 # Number of read requests responded to by this memory
system.physmem.num_reads::total 179805900 # Number of read requests responded to by this memory
system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory
system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory
system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4872539 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 4951932 # Number of write requests responded to by this memory
system.physmem.num_writes::total 9871209 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 159006406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 7559287 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 88373916 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 10080840 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 265089618 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 159006406 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 88373916 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 247380322 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s)
system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory
system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6113126 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 6693420 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13370317 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 159006406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13672414 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 88373916 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 16774261 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 278459935 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
@ -114,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.numCycles 10611136755 # number of cpu cycles simulated
system.cpu0.numCycles 10608177450 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 90467113 # Number of instructions committed
system.cpu0.committedOps 191744891 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 172320091 # Number of integer alu accesses
system.cpu0.committedInsts 88690468 # Number of instructions committed
system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 18433408 # number of instructions that are conditional controls
system.cpu0.num_int_insts 172320091 # number of integer instructions
system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls
system.cpu0.num_int_insts 168469813 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 529438037 # number of times the integer registers were read
system.cpu0.num_int_register_writes 286410601 # number of times the integer registers were written
system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read
system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 19683230 # number of memory refs
system.cpu0.num_load_insts 14799913 # Number of load instructions
system.cpu0.num_store_insts 4883317 # Number of store instructions
system.cpu0.num_idle_cycles 10087385086.886099 # Number of idle cycles
system.cpu0.num_busy_cycles 523751668.113901 # Number of busy cycles
system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles
system.cpu0.num_mem_refs 19132508 # number of memory refs
system.cpu0.num_load_insts 14284566 # Number of load instructions
system.cpu0.num_store_insts 4847942 # Number of store instructions
system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles
system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles
system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.numCycles 10608184676 # number of cpu cycles simulated
system.cpu1.numCycles 10609379371 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 48458484 # Number of instructions committed
system.cpu1.committedOps 93253647 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 88897203 # Number of integer alu accesses
system.cpu1.committedInsts 48574284 # Number of instructions committed
system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 8156142 # number of instructions that are conditional controls
system.cpu1.num_int_insts 88897203 # number of integer instructions
system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls
system.cpu1.num_int_insts 89110416 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 272264147 # number of times the integer registers were read
system.cpu1.num_int_register_writes 138280138 # number of times the integer registers were written
system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read
system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 14383325 # number of memory refs
system.cpu1.num_load_insts 9129593 # Number of load instructions
system.cpu1.num_store_insts 5253732 # Number of store instructions
system.cpu1.num_idle_cycles 10274264583.773684 # Number of idle cycles
system.cpu1.num_busy_cycles 333920092.226317 # Number of busy cycles
system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles
system.cpu1.num_mem_refs 14426742 # number of memory refs
system.cpu1.num_load_insts 9181010 # Number of load instructions
system.cpu1.num_store_insts 5245732 # Number of store instructions
system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles
system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles
system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed

4
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -507,7 +507,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
egid=100
env=
errout=cerr
@ -530,7 +530,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 15:42:24
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 01:18:01
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 213265939500 because target called exit()
Exiting @ tick 213305827500 because target called exit()

1034
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -510,7 +510,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
egid=100
env=
errout=cerr
@ -533,7 +533,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

8
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 13:33:28
gem5 compiled Jul 26 2012 21:30:36
gem5 started Jul 26 2012 23:13:36
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -80,4 +80,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 460577560500 because target called exit()
Exiting @ tick 460506550000 because target called exit()

1052
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -287,7 +287,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=true
width=64
width=8
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@ -349,9 +349,9 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
@ -406,7 +406,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side

7
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
View file

@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18
gem5 started Jun 28 2012 22:10:04
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 21:40:04
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
Exiting @ tick 1870335522500 because m5_exit instruction encountered

116
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu
sim_ticks 1870335522500 # Number of ticks simulated
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 4061827 # Simulator instruction rate (inst/s)
host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 120292600618 # Simulator tick rate (ticks/s)
host_mem_usage 301032 # Number of bytes of host memory used
host_seconds 15.55 # Real time elapsed on the host
host_inst_rate 3051606 # Simulator instruction rate (inst/s)
host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 90374561583 # Simulator tick rate (ticks/s)
host_mem_usage 305448 # Number of bytes of host memory used
host_seconds 20.70 # Real time elapsed on the host
sim_insts 63154034 # Number of instructions simulated
sim_ops 63154034 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory
@ -50,9 +50,9 @@ system.physmem.bw_total::cpu1.data 357514 # To
system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 1000626 # number of replacements
system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use
system.l2c.total_refs 2464692 # Total number of references to valid blocks.
system.l2c.total_refs 2464737 # Total number of references to valid blocks.
system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.312597 # Average number of references to valid blocks.
system.l2c.avg_refs 2.312639 # Average number of references to valid blocks.
system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor
@ -66,31 +66,31 @@ system.l2c.occ_percent::cpu1.inst 0.002661 # Av
system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits
system.l2c.Writeback_hits::total 816766 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits
system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits
system.l2c.Writeback_hits::total 816653 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits
system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits
system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits
system.l2c.overall_hits::cpu0.data 929204 # number of overall hits
system.l2c.overall_hits::cpu0.data 929311 # number of overall hits
system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits
system.l2c.overall_hits::cpu1.data 50984 # number of overall hits
system.l2c.overall_hits::total 1955170 # number of overall hits
system.l2c.overall_hits::cpu1.data 51019 # number of overall hits
system.l2c.overall_hits::total 1955312 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses
@ -116,55 +116,55 @@ system.l2c.overall_misses::cpu1.inst 1734 # nu
system.l2c.overall_misses::cpu1.data 10570 # number of overall misses
system.l2c.overall_misses::total 1066665 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -448,8 +448,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 95 # number of writebacks
system.cpu0.icache.writebacks::total 95 # number of writebacks
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1978686 # number of replacements
system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use
@ -687,8 +685,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 18 # number of writebacks
system.cpu1.icache.writebacks::total 18 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 62044 # number of replacements
system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use

8
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -190,7 +190,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=true
width=64
width=8
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@ -252,9 +252,9 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
@ -309,7 +309,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

7
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:05:18
gem5 started Jun 28 2012 22:10:03
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 21:39:53
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered

84
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
sim_ticks 1829332258000 # Number of ticks simulated
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 4017982 # Simulator instruction rate (inst/s)
host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 122425314574 # Simulator tick rate (ticks/s)
host_mem_usage 297960 # Number of bytes of host memory used
host_seconds 14.94 # Real time elapsed on the host
host_inst_rate 2962809 # Simulator instruction rate (inst/s)
host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 90274916526 # Simulator tick rate (ticks/s)
host_mem_usage 302384 # Number of bytes of host memory used
host_seconds 20.26 # Real time elapsed on the host
sim_insts 60038305 # Number of instructions simulated
sim_ops 60038305 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
@ -40,9 +40,9 @@ system.physmem.bw_total::tsunami.ide 1449867 # To
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 992301 # number of replacements
system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use
system.l2c.total_refs 2433195 # Total number of references to valid blocks.
system.l2c.total_refs 2433239 # Total number of references to valid blocks.
system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.300972 # Average number of references to valid blocks.
system.l2c.avg_refs 2.301014 # Average number of references to valid blocks.
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
@ -52,20 +52,20 @@ system.l2c.occ_percent::cpu.inst 0.074270 # Av
system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits
system.l2c.Writeback_hits::total 833599 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits
system.l2c.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1718026 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 833491 # number of Writeback hits
system.l2c.Writeback_hits::total 833491 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 187229 # number of ReadExReq hits
system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits
system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 998458 # number of demand (read+write) hits
system.l2c.demand_hits::total 1905255 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.inst 906797 # number of overall hits
system.l2c.overall_hits::cpu.data 998308 # number of overall hits
system.l2c.overall_hits::total 1905105 # number of overall hits
system.l2c.overall_hits::cpu.data 998458 # number of overall hits
system.l2c.overall_hits::total 1905255 # number of overall hits
system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses
@ -80,33 +80,33 @@ system.l2c.overall_misses::cpu.inst 13406 # nu
system.l2c.overall_misses::cpu.data 1044757 # number of overall misses
system.l2c.overall_misses::total 1058163 # number of overall misses
system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2963418 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2963418 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.357075 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.357075 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -385,8 +385,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 108 # number of writebacks
system.cpu.icache.writebacks::total 108 # number of writebacks
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2042702 # number of replacements
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use

2
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -343,7 +343,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

9
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
View file

@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 09:09:26
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 21:40:05
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 573593000
Exiting @ tick 1954209106000 because m5_exit instruction encountered
Exiting @ tick 1954209529000 because m5_exit instruction encountered

1060
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -250,7 +250,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port[0]
master=system.bridge.slave system.physmem.port
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

9
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
View file

@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 09:09:16
gem5 compiled Jul 26 2012 21:20:05
gem5 started Jul 26 2012 21:40:05
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1920852274000 because m5_exit instruction encountered
Exiting @ tick 1920853042000 because m5_exit instruction encountered

506
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.920852 # Number of seconds simulated
sim_ticks 1920852274000 # Number of ticks simulated
final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.920853 # Number of seconds simulated
sim_ticks 1920853042000 # Number of ticks simulated
final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1904642 # Simulator instruction rate (inst/s)
host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 65112526106 # Simulator tick rate (ticks/s)
host_mem_usage 294856 # Number of bytes of host memory used
host_seconds 29.50 # Real time elapsed on the host
host_inst_rate 1381815 # Simulator instruction rate (inst/s)
host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47239093914 # Simulator tick rate (ticks/s)
host_mem_usage 299308 # Number of bytes of host memory used
host_seconds 40.66 # Real time elapsed on the host
sim_insts 56187824 # Number of instructions simulated
sim_ops 56187824 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory
@ -26,113 +26,113 @@ system.physmem.num_reads::total 442978 # Nu
system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 336066 # number of replacements
system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use
system.l2c.total_refs 2448229 # Total number of references to valid blocks.
system.l2c.sampled_refs 401229 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.101825 # Average number of references to valid blocks.
system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use
system.l2c.total_refs 2448197 # Total number of references to valid blocks.
system.l2c.sampled_refs 401228 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.101760 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor
system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits
system.l2c.Writeback_hits::total 835223 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits
system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits
system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.inst 916210 # number of overall hits
system.l2c.overall_hits::cpu.data 1002336 # number of overall hits
system.l2c.overall_hits::total 1918546 # number of overall hits
system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits
system.l2c.Writeback_hits::total 835149 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits
system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits
system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.inst 916208 # number of overall hits
system.l2c.overall_hits::cpu.data 1002538 # number of overall hits
system.l2c.overall_hits::total 1918746 # number of overall hits
system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 116714 # number of ReadExReq misses
system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses
system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 388629 # number of demand (read+write) misses
system.l2c.demand_misses::total 401921 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses
system.l2c.demand_misses::total 401925 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.inst 13292 # number of overall misses
system.l2c.overall_misses::cpu.data 388629 # number of overall misses
system.l2c.overall_misses::total 401921 # number of overall misses
system.l2c.overall_misses::cpu.data 388633 # number of overall misses
system.l2c.overall_misses::total 401925 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6069807000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6069807000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 20214662000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20906435000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 20214662000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20906435000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.inst 929502 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1086794 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2016296 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835223 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835223 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 304171 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 304171 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.inst 929502 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1390965 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2320467 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.inst 929502 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1390965 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2320467 # number of overall (read+write) accesses
system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.250199 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.141451 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.571429 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.571429 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.383712 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.383712 # miss rate for ReadExReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.279395 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.173207 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.279395 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.173207 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 40000 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 40000 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52005.817640 # average ReadExReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52016.279319 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52016.279319 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -146,29 +146,29 @@ system.l2c.writebacks::total 73942 # nu
system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 388629 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 401921 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 388629 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 401921 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 380000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 380000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669239000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4669239000 # number of ReadExReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 15551114000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16083380000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 15551114000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16083380000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles
@ -176,31 +176,31 @@ system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000
system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250199 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.141451 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.571429 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.571429 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383712 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.383712 # mshr miss rate for ReadExReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.173207 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.173207 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 47500 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 47500 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640 # average ReadExReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.356962 # Cycle average of tags in use
system.iocache.tagsinuse 1.356968 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy
system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@ -344,7 +344,7 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 3841704548 # number of cpu cycles simulated
system.cpu.numCycles 3841706084 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56187824 # Number of instructions committed
@ -362,10 +362,10 @@ system.cpu.num_fp_register_writes 166520 # nu
system.cpu.num_mem_refs 15475451 # number of memory refs
system.cpu.num_load_insts 9102635 # Number of load instructions
system.cpu.num_store_insts 6372816 # Number of store instructions
system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles
system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles
system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.934372 # Percentage of idle cycles
system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles
system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles
system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.934371 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed
@ -379,11 +379,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu
system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@ -447,9 +447,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323061 # fr
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@ -482,33 +482,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 928851 # number of replacements
system.cpu.icache.tagsinuse 508.732124 # Cycle average of tags in use
system.cpu.icache.total_refs 55270141 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 929362 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 59.471058 # Average number of references to valid blocks.
system.cpu.icache.replacements 928849 # number of replacements
system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use
system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 508.732124 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 55270141 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55270141 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55270141 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55270141 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55270141 # number of overall hits
system.cpu.icache.overall_hits::total 55270141 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 929522 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 929522 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 929522 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 929522 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 929522 # number of overall misses
system.cpu.icache.overall_misses::total 929522 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854472500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13854472500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13854472500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13854472500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13854472500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13854472500 # number of overall miss cycles
system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits
system.cpu.icache.overall_hits::total 55270143 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses
system.cpu.icache.overall_misses::total 929520 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses
@ -521,12 +521,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540
system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14904.943078 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14904.943078 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -535,74 +535,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1390643 # number of replacements
system.cpu.dcache.replacements 1390657 # number of replacements
system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 1391155 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.100032 # Average number of references to valid blocks.
system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy
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system.cpu.dcache.WriteReq_hits::total 5853082 # number of WriteReq hits
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system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits
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system.cpu.dcache.overall_hits::total 13668429 # number of overall hits
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system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
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system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits
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system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses
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system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses
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system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses)
@ -615,26 +613,26 @@ system.cpu.dcache.demand_accesses::cpu.data 15042278 #
system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses
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system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -643,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks
system.cpu.dcache.writebacks::total 835138 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks
system.cpu.dcache.writebacks::total 835149 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency

10
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
memories=system.realview.nvmem system.physmem
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
@ -306,7 +306,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
@ -367,9 +367,9 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
@ -780,7 +780,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14
gem5 started Jun 29 2012 00:36:18
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 00:55:21
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 911653589000 because m5_exit instruction encountered
Exiting @ tick 912096763500 because m5_exit instruction encountered

984
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
View file

@ -191,7 +191,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
@ -252,9 +252,9 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
@ -665,7 +665,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
width=8
master=system.l2c.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 28 2012 22:10:14
gem5 started Jun 29 2012 00:35:36
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 00:54:29
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2332330037000 because m5_exit instruction encountered
Exiting @ tick 2332810264000 because m5_exit instruction encountered

456
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.332330 # Number of seconds simulated
sim_ticks 2332330037000 # Number of ticks simulated
final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.332810 # Number of seconds simulated
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1988795 # Simulator instruction rate (inst/s)
host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 78099767101 # Simulator tick rate (ticks/s)
host_mem_usage 382744 # Number of bytes of host memory used
host_seconds 29.86 # Real time elapsed on the host
sim_insts 59392246 # Number of instructions simulated
sim_ops 76665494 # Number of ops (including micro ops) simulated
host_inst_rate 1498673 # Simulator instruction rate (inst/s)
host_op_rate 1927201 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 57874436068 # Simulator tick rate (ticks/s)
host_mem_usage 388524 # Number of bytes of host memory used
host_seconds 40.31 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory
system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory
system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory
system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s)
system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 62240 # number of replacements
system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use
system.l2c.total_refs 1717775 # Total number of references to valid blocks.
system.l2c.sampled_refs 127625 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.459549 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy
system.l2c.replacements 62243 # number of replacements
system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use
system.l2c.total_refs 1669922 # Total number of references to valid blocks.
system.l2c.sampled_refs 127628 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.084292 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits
system.l2c.Writeback_hits::total 642748 # number of Writeback hits
system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits
system.l2c.Writeback_hits::total 592643 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits
system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits
system.l2c.overall_hits::cpu.inst 838895 # number of overall hits
system.l2c.overall_hits::cpu.data 478181 # number of overall hits
system.l2c.overall_hits::total 1327761 # number of overall hits
system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits
system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits
system.l2c.overall_hits::cpu.inst 838871 # number of overall hits
system.l2c.overall_hits::cpu.data 480510 # number of overall hits
system.l2c.overall_hits::total 1330017 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses
system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses
system.l2c.demand_misses::total 153949 # number of demand (read+write) misses
system.l2c.demand_misses::total 153951 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu.inst 10602 # number of overall misses
system.l2c.overall_misses::cpu.inst 10604 # number of overall misses
system.l2c.overall_misses::cpu.data 143339 # number of overall misses
system.l2c.overall_misses::total 153949 # number of overall misses
system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses
system.l2c.overall_misses::total 153951 # number of overall misses
system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 57860 # number of writebacks
system.l2c.writebacks::total 57860 # number of writebacks
system.l2c.writebacks::writebacks 57863 # number of writebacks
system.l2c.writebacks::total 57863 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -177,26 +177,26 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14971229 # DTB read hits
system.cpu.dtb.read_misses 7293 # DTB read misses
system.cpu.dtb.write_hits 11217018 # DTB write hits
system.cpu.dtb.read_hits 14971214 # DTB read hits
system.cpu.dtb.read_misses 7294 # DTB read misses
system.cpu.dtb.write_hits 11217004 # DTB write hits
system.cpu.dtb.write_misses 2181 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 14978522 # DTB read accesses
system.cpu.dtb.write_accesses 11219199 # DTB write accesses
system.cpu.dtb.read_accesses 14978508 # DTB read accesses
system.cpu.dtb.write_accesses 11219185 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26188247 # DTB hits
system.cpu.dtb.misses 9474 # DTB misses
system.cpu.dtb.accesses 26197721 # DTB accesses
system.cpu.itb.inst_hits 60403303 # ITB inst hits
system.cpu.dtb.hits 26188218 # DTB hits
system.cpu.dtb.misses 9475 # DTB misses
system.cpu.dtb.accesses 26197693 # DTB accesses
system.cpu.itb.inst_hits 61431840 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@ -213,67 +213,67 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
system.cpu.itb.hits 60403303 # DTB hits
system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
system.cpu.itb.hits 61431840 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 60407774 # DTB accesses
system.cpu.numCycles 4664583062 # number of cpu cycles simulated
system.cpu.itb.accesses 61436311 # DTB accesses
system.cpu.numCycles 4665543516 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 59392246 # Number of instructions committed
system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
system.cpu.committedInsts 60408639 # Number of instructions committed
system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2136013 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
system.cpu.num_int_insts 68281415 # number of integer instructions
system.cpu.num_func_calls 2136008 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7904929 # number of instructions that are conditional controls
system.cpu.num_int_insts 68795605 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27361692 # number of memory refs
system.cpu.num_load_insts 15639569 # Number of load instructions
system.cpu.num_store_insts 11722123 # Number of store instructions
system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
system.cpu.num_mem_refs 27361637 # number of memory refs
system.cpu.num_load_insts 15639527 # Number of load instructions
system.cpu.num_store_insts 11722110 # Number of store instructions
system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles
system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles
system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
system.cpu.icache.replacements 850612 # number of replacements
system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
system.cpu.icache.replacements 850590 # number of replacements
system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use
system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
system.cpu.icache.overall_hits::total 59554939 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
system.cpu.icache.overall_misses::total 851124 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses
system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
system.cpu.icache.overall_hits::total 60583498 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
system.cpu.icache.overall_misses::total 851102 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -282,58 +282,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 50093 # number of writebacks
system.cpu.icache.writebacks::total 50093 # number of writebacks
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 623347 # number of replacements
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
system.cpu.dcache.replacements 623337 # number of replacements
system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
system.cpu.dcache.overall_misses::total 615615 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
system.cpu.dcache.overall_misses::total 615611 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
@ -346,8 +344,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks
system.cpu.dcache.writebacks::total 592655 # number of writebacks
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
system.cpu.dcache.writebacks::total 592643 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use

2
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View file

@ -361,7 +361,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 15:21:03
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 00:58:01
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1171612619000 because m5_exit instruction encountered
Exiting @ tick 1172544977000 because m5_exit instruction encountered

1624
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View file

@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.realview.nvmem system.physmem
memories=system.physmem system.realview.nvmem
midr_regval=890224640
multi_proc=true
num_work_ids=16
@ -250,7 +250,7 @@ header_cycles=1
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 09:08:16
gem5 started Jul 2 2012 15:20:44
gem5 compiled Jul 26 2012 21:40:00
gem5 started Jul 27 2012 00:56:10
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2593402521000 because m5_exit instruction encountered
Exiting @ tick 2594327510000 because m5_exit instruction encountered

846
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View file

@ -1,16 +1,54 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.593403 # Number of seconds simulated
sim_ticks 2593402521000 # Number of ticks simulated
final_tick 2593402521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.594328 # Number of seconds simulated
sim_ticks 2594327510000 # Number of ticks simulated
final_tick 2594327510000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 766927 # Simulator instruction rate (inst/s)
host_op_rate 979485 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33608362861 # Simulator tick rate (ticks/s)
host_mem_usage 384708 # Number of bytes of host memory used
host_seconds 77.17 # Real time elapsed on the host
sim_insts 59180230 # Number of instructions simulated
sim_ops 75582343 # Number of ops (including micro ops) simulated
host_inst_rate 600896 # Simulator instruction rate (inst/s)
host_op_rate 764626 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25897323777 # Simulator tick rate (ticks/s)
host_mem_usage 390576 # Number of bytes of host memory used
host_seconds 100.18 # Real time elapsed on the host
sim_insts 60196191 # Number of instructions simulated
sim_ops 76598245 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9067216 # Number of bytes read from this memory
system.physmem.bytes_read::total 132455344 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704288 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704288 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3695616 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6711688 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17207 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141709 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494347 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57744 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811762 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47289092 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 271472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3495016 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51055753 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 271472 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 271472 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1424499 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1162564 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2587063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1424499 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47289092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 271472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4657580 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53642816 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@ -23,179 +61,141 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9067536 # Number of bytes read from this memory
system.physmem.bytes_read::total 132455600 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704224 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704224 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3695808 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6711880 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17206 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141714 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494351 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57747 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811765 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47305958 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 271544 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3496386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51074062 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 271544 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 271544 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1425081 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1162979 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2588059 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1425081 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47305958 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 271544 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4659365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53662121 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 62163 # number of replacements
system.l2c.tagsinuse 51413.022429 # Cycle average of tags in use
system.l2c.total_refs 1730961 # Total number of references to valid blocks.
system.l2c.sampled_refs 127547 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.571162 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2544159444000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 38018.047073 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 3.884744 # Average occupied blocks per requestor
system.l2c.replacements 62159 # number of replacements
system.l2c.tagsinuse 51417.185894 # Cycle average of tags in use
system.l2c.total_refs 1682923 # Total number of references to valid blocks.
system.l2c.sampled_refs 127542 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.195049 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2544924960000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 38023.288706 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 3.884784 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.000558 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 7004.232123 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 6386.857931 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.580109 # Average percentage of cache occupancy
system.l2c.occ_blocks::cpu.inst 7004.395748 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 6385.616098 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.580189 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.106876 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.097456 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784500 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 8759 # number of ReadReq hits
system.l2c.occ_percent::cpu.inst 0.106879 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.097437 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784564 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 8754 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 3544 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 843511 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 367799 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1223613 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 646378 # number of Writeback hits
system.l2c.Writeback_hits::total 646378 # number of Writeback hits
system.l2c.ReadReq_hits::cpu.inst 843519 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 370124 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1225941 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596001 # number of Writeback hits
system.l2c.Writeback_hits::total 596001 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 114402 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114402 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 8759 # number of demand (read+write) hits
system.l2c.ReadExReq_hits::cpu.data 114391 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114391 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 8754 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 3544 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 843511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 482201 # number of demand (read+write) hits
system.l2c.demand_hits::total 1338015 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 8759 # number of overall hits
system.l2c.demand_hits::cpu.inst 843519 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 484515 # number of demand (read+write) hits
system.l2c.demand_hits::total 1340332 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 8754 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 3544 # number of overall hits
system.l2c.overall_hits::cpu.inst 843511 # number of overall hits
system.l2c.overall_hits::cpu.data 482201 # number of overall hits
system.l2c.overall_hits::total 1338015 # number of overall hits
system.l2c.overall_hits::cpu.inst 843519 # number of overall hits
system.l2c.overall_hits::cpu.data 484515 # number of overall hits
system.l2c.overall_hits::total 1340332 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 10590 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 10591 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 10247 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20844 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2881 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 133061 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133061 # number of ReadExReq misses
system.l2c.ReadReq_misses::total 20845 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 2879 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2879 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 133059 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133059 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 10590 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 143308 # number of demand (read+write) misses
system.l2c.demand_misses::total 153905 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 10591 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 143306 # number of demand (read+write) misses
system.l2c.demand_misses::total 153904 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu.inst 10590 # number of overall misses
system.l2c.overall_misses::cpu.data 143308 # number of overall misses
system.l2c.overall_misses::total 153905 # number of overall misses
system.l2c.overall_misses::cpu.inst 10591 # number of overall misses
system.l2c.overall_misses::cpu.data 143306 # number of overall misses
system.l2c.overall_misses::total 153904 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 260500 # number of ReadReq miss cycles
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system.l2c.overall_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.102998 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40144.381492 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40070.362057 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40107.944732 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.618188 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.618188 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.807893 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40041.807893 # average ReadExReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@ -307,26 +307,26 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14995175 # DTB read hits
system.cpu.dtb.read_misses 7360 # DTB read misses
system.cpu.dtb.write_hits 11229808 # DTB write hits
system.cpu.dtb.read_hits 14995137 # DTB read hits
system.cpu.dtb.read_misses 7357 # DTB read misses
system.cpu.dtb.write_hits 11229787 # DTB write hits
system.cpu.dtb.write_misses 2205 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_entries 3485 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15002535 # DTB read accesses
system.cpu.dtb.write_accesses 11232013 # DTB write accesses
system.cpu.dtb.read_accesses 15002494 # DTB read accesses
system.cpu.dtb.write_accesses 11231992 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26224983 # DTB hits
system.cpu.dtb.misses 9565 # DTB misses
system.cpu.dtb.accesses 26234548 # DTB accesses
system.cpu.itb.inst_hits 60461981 # ITB inst hits
system.cpu.dtb.hits 26224924 # DTB hits
system.cpu.dtb.misses 9562 # DTB misses
system.cpu.dtb.accesses 26234486 # DTB accesses
system.cpu.itb.inst_hits 61490084 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 60466452 # ITB inst accesses
system.cpu.itb.hits 60461981 # DTB hits
system.cpu.itb.inst_accesses 61494555 # ITB inst accesses
system.cpu.itb.hits 61490084 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 60466452 # DTB accesses
system.cpu.numCycles 5186805042 # number of cpu cycles simulated
system.cpu.itb.accesses 61494555 # DTB accesses
system.cpu.numCycles 5188655020 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 59180230 # Number of instructions committed
system.cpu.committedOps 75582343 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68351784 # Number of integer alu accesses
system.cpu.committedInsts 60196191 # Number of instructions committed
system.cpu.committedOps 76598245 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68865648 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2139562 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7653493 # number of instructions that are conditional controls
system.cpu.num_int_insts 68351784 # number of integer instructions
system.cpu.num_func_calls 2139540 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7910583 # number of instructions that are conditional controls
system.cpu.num_int_insts 68865648 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 391402858 # number of times the integer registers were read
system.cpu.num_int_register_writes 73137157 # number of times the integer registers were written
system.cpu.num_int_register_reads 394743471 # number of times the integer registers were read
system.cpu.num_int_register_writes 74177139 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27392171 # number of memory refs
system.cpu.num_load_insts 15659029 # Number of load instructions
system.cpu.num_store_insts 11733142 # Number of store instructions
system.cpu.num_idle_cycles 4570470450.554237 # Number of idle cycles
system.cpu.num_busy_cycles 616334591.445762 # Number of busy cycles
system.cpu.not_idle_fraction 0.118827 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.881173 # Percentage of idle cycles
system.cpu.num_mem_refs 27392126 # number of memory refs
system.cpu.num_load_insts 15659006 # Number of load instructions
system.cpu.num_store_insts 11733120 # Number of store instructions
system.cpu.num_idle_cycles 4570211154.554238 # Number of idle cycles
system.cpu.num_busy_cycles 618443865.445762 # Number of busy cycles
system.cpu.not_idle_fraction 0.119192 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.880808 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82989 # number of quiesce instructions executed
system.cpu.icache.replacements 855209 # number of replacements
system.cpu.icache.tagsinuse 510.928777 # Cycle average of tags in use
system.cpu.icache.total_refs 59606260 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855721 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 69.656185 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18855254000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.928777 # Average occupied blocks per requestor
system.cpu.icache.replacements 855220 # number of replacements
system.cpu.icache.tagsinuse 510.929118 # Cycle average of tags in use
system.cpu.icache.total_refs 60634352 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855732 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.856707 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18856022000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.929118 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997908 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997908 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 59606260 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59606260 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 59606260 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 59606260 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 59606260 # number of overall hits
system.cpu.icache.overall_hits::total 59606260 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 855721 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 855721 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 855721 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 855721 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 855721 # number of overall misses
system.cpu.icache.overall_misses::total 855721 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12570164500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12570164500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12570164500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12570164500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12570164500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12570164500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 60461981 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 60461981 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 60461981 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 60461981 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 60461981 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 60461981 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014153 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014153 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014153 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14689.559448 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14689.559448 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14689.559448 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14689.559448 # average overall miss latency
system.cpu.icache.ReadReq_hits::cpu.inst 60634352 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60634352 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60634352 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60634352 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60634352 # number of overall hits
system.cpu.icache.overall_hits::total 60634352 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 855732 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 855732 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 855732 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 855732 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 855732 # number of overall misses
system.cpu.icache.overall_misses::total 855732 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12556184500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12556184500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12556184500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12556184500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12556184500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12556184500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61490084 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61490084 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61490084 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61490084 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61490084 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61490084 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013917 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013917 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013917 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013917 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14673.033730 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14673.033730 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -424,114 +424,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 50294 # number of writebacks
system.cpu.icache.writebacks::total 50294 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855721 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855721 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855721 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855721 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855721 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855721 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10001095500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10001095500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10001095500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10001095500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10001095500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10001095500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855732 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855732 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855732 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855732 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855732 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855732 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9987081500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9987081500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9987081500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9987081500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9987081500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9987081500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014153 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014153 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014153 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11687.332086 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11687.332086 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11687.332086 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11687.332086 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11687.332086 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11687.332086 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013917 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 627384 # number of replacements
system.cpu.dcache.tagsinuse 511.875582 # Cycle average of tags in use
system.cpu.dcache.total_refs 23653412 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627896 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.670907 # Average number of references to valid blocks.
system.cpu.dcache.replacements 627309 # number of replacements
system.cpu.dcache.tagsinuse 511.875626 # Cycle average of tags in use
system.cpu.dcache.total_refs 23653426 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627821 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.675430 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.875582 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 511.875626 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13194595 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13194595 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9972161 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9972161 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236089 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236089 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247660 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247660 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23166756 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23166756 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23166756 # number of overall hits
system.cpu.dcache.overall_hits::total 23166756 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368861 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368861 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250370 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250370 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11572 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619231 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619231 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619231 # number of overall misses
system.cpu.dcache.overall_misses::total 619231 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722405000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5722405000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232056000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9232056000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 172133500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 172133500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14954461000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14954461000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14954461000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14954461000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13563456 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13563456 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247661 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247661 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247660 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247660 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23785987 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23785987 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23785987 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23785987 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027195 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024492 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046725 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046725 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15513.716549 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15513.716549 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36873.650997 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36873.650997 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14875 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14875 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24150.052242 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24150.052242 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24150.052242 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24150.052242 # average overall miss latency
system.cpu.dcache.ReadReq_hits::cpu.data 13194612 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13194612 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9972158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9972158 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236094 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236094 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247657 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247657 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23166770 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23166770 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23166770 # number of overall hits
system.cpu.dcache.overall_hits::total 23166770 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368807 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368807 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250355 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250355 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11564 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11564 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619162 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619162 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619162 # number of overall misses
system.cpu.dcache.overall_misses::total 619162 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5738700500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5738700500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9229453000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9229453000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171857500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 171857500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14968153500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14968153500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14968153500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14968153500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13563419 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13563419 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222513 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222513 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247658 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247658 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247657 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247657 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23785932 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23785932 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23785932 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23785932 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027191 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027191 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024491 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046693 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046693 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026031 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026031 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026031 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026031 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24174.858115 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24174.858115 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -540,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 596084 # number of writebacks
system.cpu.dcache.writebacks::total 596084 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368861 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368861 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250370 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250370 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11572 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619231 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619231 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619231 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619231 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4614667500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4614667500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480868000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480868000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137416000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137416000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13095535500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13095535500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13095535500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13095535500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146835601000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146835601000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40324843500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40324843500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027195 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024492 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046725 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046725 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency
system.cpu.dcache.writebacks::writebacks 596001 # number of writebacks
system.cpu.dcache.writebacks::total 596001 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368807 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368807 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250355 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250355 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11564 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11564 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619162 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619162 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619162 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619162 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4631124500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4631124500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8478310000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8478310000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137164000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137164000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13109434500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13109434500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13109434500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13109434500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40357680500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40357680500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027191 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027191 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024491 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046693 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046693 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@ -609,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1341484384445 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1342178832750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency

6
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=atomic
memories=system.physmem
@ -934,7 +934,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -954,7 +954,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
View file

@ -1,15 +1,13 @@
Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 22 2012 08:05:39
gem5 started Jul 22 2012 08:43:43
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jul 26 2012 21:30:36
gem5 started Jul 26 2012 22:49:04
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112043255000 because m5_exit instruction encountered

24
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.112043 # Nu
sim_ticks 5112043255000 # Number of ticks simulated
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1067695 # Simulator instruction rate (inst/s)
host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27315912254 # Simulator tick rate (ticks/s)
host_mem_usage 409548 # Number of bytes of host memory used
host_seconds 187.15 # Real time elapsed on the host
host_inst_rate 1419112 # Simulator instruction rate (inst/s)
host_op_rate 2905734 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36306590178 # Simulator tick rate (ticks/s)
host_mem_usage 362152 # Number of bytes of host memory used
host_seconds 140.80 # Real time elapsed on the host
sim_insts 199813914 # Number of instructions simulated
sim_ops 409133298 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory
@ -48,9 +48,9 @@ system.physmem.bw_total::cpu.data 2073572 # To
system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 106561 # number of replacements
system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use
system.l2c.total_refs 3457342 # Total number of references to valid blocks.
system.l2c.total_refs 3456533 # Total number of references to valid blocks.
system.l2c.sampled_refs 170680 # Sample count of references to valid blocks.
system.l2c.avg_refs 20.256281 # Average number of references to valid blocks.
system.l2c.avg_refs 20.251541 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
@ -68,8 +68,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker 2700 # nu
system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits
system.l2c.Writeback_hits::total 1538939 # number of Writeback hits
system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits
system.l2c.Writeback_hits::total 1538130 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
@ -108,8 +108,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker 2705 #
system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
@ -275,8 +275,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 809 # number of writebacks
system.cpu.icache.writebacks::total 809 # number of writebacks
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3335 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use

6
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@ -930,7 +930,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -950,7 +950,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
View file

@ -1,15 +1,13 @@
Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout
Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 22 2012 08:05:39
gem5 started Jul 22 2012 08:43:19
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jul 26 2012 21:30:36
gem5 started Jul 26 2012 22:51:36
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5191766314000 because m5_exit instruction encountered

24
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.191766 # Nu
sim_ticks 5191766314000 # Number of ticks simulated
final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 672863 # Simulator instruction rate (inst/s)
host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25283717995 # Simulator tick rate (ticks/s)
host_mem_usage 405876 # Number of bytes of host memory used
host_seconds 205.34 # Real time elapsed on the host
host_inst_rate 787684 # Simulator instruction rate (inst/s)
host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29598304712 # Simulator tick rate (ticks/s)
host_mem_usage 358992 # Number of bytes of host memory used
host_seconds 175.41 # Real time elapsed on the host
sim_insts 138165780 # Number of instructions simulated
sim_ops 265203824 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory
@ -44,9 +44,9 @@ system.physmem.bw_total::cpu.data 1721828 # To
system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 86221 # number of replacements
system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use
system.l2c.total_refs 3491043 # Total number of references to valid blocks.
system.l2c.total_refs 3490237 # Total number of references to valid blocks.
system.l2c.sampled_refs 150947 # Sample count of references to valid blocks.
system.l2c.avg_refs 23.127608 # Average number of references to valid blocks.
system.l2c.avg_refs 23.122268 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor
@ -62,8 +62,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker 2757 # nu
system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits
system.l2c.Writeback_hits::total 1542135 # number of Writeback hits
system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits
system.l2c.Writeback_hits::total 1541329 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits
@ -115,8 +115,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker 2762 #
system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses)
@ -431,8 +431,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 806 # number of writebacks
system.cpu.icache.writebacks::total 806 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses

75
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -155,30 +155,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -214,16 +204,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -260,76 +245,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -337,10 +302,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:30:17
gem5 started Jul 10 2012 17:30:49
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 13:42:35
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000279 # Nu
sim_ticks 279353 # Number of ticks simulated
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 24575 # Simulator instruction rate (inst/s)
host_op_rate 24573 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1071866 # Simulator tick rate (ticks/s)
host_mem_usage 236072 # Number of bytes of host memory used
host_seconds 0.26 # Real time elapsed on the host
host_inst_rate 12119 # Simulator instruction rate (inst/s)
host_op_rate 12118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 528605 # Simulator tick rate (ticks/s)
host_mem_usage 226340 # Number of bytes of host memory used
host_seconds 0.53 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 23969673 # Wr
system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

75
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -152,30 +152,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -210,16 +200,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -256,76 +241,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -333,10 +298,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:36:02
gem5 started Jul 10 2012 17:36:36
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:54:55
gem5 started Jun 4 2012 14:41:04
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000224 # Nu
sim_ticks 223694 # Number of ticks simulated
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 21381 # Simulator instruction rate (inst/s)
host_op_rate 21380 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 746759 # Simulator tick rate (ticks/s)
host_mem_usage 236312 # Number of bytes of host memory used
host_seconds 0.30 # Real time elapsed on the host
host_inst_rate 30014 # Simulator instruction rate (inst/s)
host_op_rate 30012 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1048235 # Simulator tick rate (ticks/s)
host_mem_usage 226460 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 29933749 # Wr
system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

75
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -161,30 +161,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -221,16 +211,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -267,76 +252,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -344,10 +309,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:34:13
gem5 started Jul 10 2012 17:45:14
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:56:32
gem5 started Jun 4 2012 14:42:12
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000232 # Nu
sim_ticks 231701 # Number of ticks simulated
final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 36777 # Simulator instruction rate (inst/s)
host_op_rate 36773 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1330353 # Simulator tick rate (ticks/s)
host_mem_usage 234436 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_inst_rate 50012 # Simulator instruction rate (inst/s)
host_op_rate 50005 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1808952 # Simulator tick rate (ticks/s)
host_mem_usage 224692 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 28899314 # Wr
system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

65
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -138,16 +138,11 @@ version=0
[system.dir_cntrl0.probeFilter]
type=RubyCache
assoc=4
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=1024
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0]
type=L1Cache_Controller
@ -172,44 +167,29 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -262,64 +242,61 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:16:15
gem5 started Jul 10 2012 17:50:25
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:51:44
gem5 started Jun 4 2012 13:41:27
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

34
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000208 # Nu
sim_ticks 208400 # Number of ticks simulated
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 40149 # Simulator instruction rate (inst/s)
host_op_rate 40144 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1306231 # Simulator tick rate (ticks/s)
host_mem_usage 233684 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_inst_rate 52133 # Simulator instruction rate (inst/s)
host_op_rate 52125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1696034 # Simulator tick rate (ticks/s)
host_mem_usage 224184 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
@ -33,30 +33,6 @@ system.physmem.bw_write::total 32130518 # Wr
system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads
system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes
system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

75
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -155,30 +155,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -214,16 +204,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -260,76 +245,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -337,10 +302,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:30:17
gem5 started Jul 10 2012 17:31:25
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 13:42:35
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000105 # Nu
sim_ticks 104867 # Number of ticks simulated
final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 25231 # Simulator instruction rate (inst/s)
host_op_rate 25226 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1026377 # Simulator tick rate (ticks/s)
host_mem_usage 233832 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 4864 # Simulator instruction rate (inst/s)
host_op_rate 4864 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 197908 # Simulator tick rate (ticks/s)
host_mem_usage 224040 # Number of bytes of host memory used
host_seconds 0.53 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 19624858 # Wr
system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

75
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -152,30 +152,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -210,16 +200,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -256,76 +241,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -333,10 +298,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:36:02
gem5 started Jul 10 2012 17:37:10
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:54:55
gem5 started Jun 4 2012 14:41:15
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000085 # Nu
sim_ticks 85418 # Number of ticks simulated
final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 21617 # Simulator instruction rate (inst/s)
host_op_rate 21614 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 716318 # Simulator tick rate (ticks/s)
host_mem_usage 234076 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_inst_rate 30509 # Simulator instruction rate (inst/s)
host_op_rate 30502 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1010829 # Simulator tick rate (ticks/s)
host_mem_usage 224228 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 24093282 # Wr
system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

75
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -161,30 +161,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -221,16 +211,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -267,76 +252,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -344,10 +309,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:34:13
gem5 started Jul 10 2012 17:45:47
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:56:32
gem5 started Jun 4 2012 14:42:22
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

28
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
sim_ticks 87899 # Number of ticks simulated
final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 36684 # Simulator instruction rate (inst/s)
host_op_rate 36675 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1250644 # Simulator tick rate (ticks/s)
host_mem_usage 233044 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 49141 # Simulator instruction rate (inst/s)
host_op_rate 49125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1675041 # Simulator tick rate (ticks/s)
host_mem_usage 223232 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
@ -33,24 +33,6 @@ system.physmem.bw_write::total 23413236 # Wr
system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

65
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -138,16 +138,11 @@ version=0
[system.dir_cntrl0.probeFilter]
type=RubyCache
assoc=4
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=1024
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0]
type=L1Cache_Controller
@ -172,44 +167,29 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -262,64 +242,61 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=2
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:16:15
gem5 started Jul 10 2012 17:50:59
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:51:44
gem5 started Jun 4 2012 13:42:34
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

34
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000078 # Nu
sim_ticks 78448 # Number of ticks simulated
final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 40059 # Simulator instruction rate (inst/s)
host_op_rate 40048 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1218818 # Simulator tick rate (ticks/s)
host_mem_usage 232472 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_inst_rate 9618 # Simulator instruction rate (inst/s)
host_op_rate 9618 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 292754 # Simulator tick rate (ticks/s)
host_mem_usage 222892 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
@ -33,30 +33,6 @@ system.physmem.bw_write::total 26233938 # Wr
system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads
system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes
system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

250
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
View file

@ -14,7 +14,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem system.funcmem
memories=system.funcmem system.physmem
num_work_ids=16
readfile=
symbolfile=
@ -249,30 +249,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -312,30 +302,20 @@ version=1
[system.l1_cntrl1.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.sequencer]
type=RubySequencer
@ -375,30 +355,20 @@ version=2
[system.l1_cntrl2.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.sequencer]
type=RubySequencer
@ -438,30 +408,20 @@ version=3
[system.l1_cntrl3.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.sequencer]
type=RubySequencer
@ -501,30 +461,20 @@ version=4
[system.l1_cntrl4.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.sequencer]
type=RubySequencer
@ -564,30 +514,20 @@ version=5
[system.l1_cntrl5.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.sequencer]
type=RubySequencer
@ -627,30 +567,20 @@ version=6
[system.l1_cntrl6.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.sequencer]
type=RubySequencer
@ -690,30 +620,20 @@ version=7
[system.l1_cntrl7.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.sequencer]
type=RubySequencer
@ -749,16 +669,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -795,174 +710,119 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers00
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl1
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers01
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl2
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers02
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.ext_links3]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl3
int_node=system.ruby.network.topology.ext_links3.int_node
int_node=system.ruby.network.topology.routers03
latency=1
link_id=3
weight=1
[system.ruby.network.topology.ext_links3.int_node]
type=BasicRouter
router_id=3
[system.ruby.network.topology.ext_links4]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl4
int_node=system.ruby.network.topology.ext_links4.int_node
int_node=system.ruby.network.topology.routers04
latency=1
link_id=4
weight=1
[system.ruby.network.topology.ext_links4.int_node]
type=BasicRouter
router_id=4
[system.ruby.network.topology.ext_links5]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl5
int_node=system.ruby.network.topology.ext_links5.int_node
int_node=system.ruby.network.topology.routers05
latency=1
link_id=5
weight=1
[system.ruby.network.topology.ext_links5.int_node]
type=BasicRouter
router_id=5
[system.ruby.network.topology.ext_links6]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl6
int_node=system.ruby.network.topology.ext_links6.int_node
int_node=system.ruby.network.topology.routers06
latency=1
link_id=6
weight=1
[system.ruby.network.topology.ext_links6.int_node]
type=BasicRouter
router_id=6
[system.ruby.network.topology.ext_links7]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl7
int_node=system.ruby.network.topology.ext_links7.int_node
int_node=system.ruby.network.topology.routers07
latency=1
link_id=7
weight=1
[system.ruby.network.topology.ext_links7.int_node]
type=BasicRouter
router_id=7
[system.ruby.network.topology.ext_links8]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links8.int_node
int_node=system.ruby.network.topology.routers08
latency=1
link_id=8
weight=1
[system.ruby.network.topology.ext_links8.int_node]
type=BasicRouter
router_id=8
[system.ruby.network.topology.ext_links9]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links9.int_node
int_node=system.ruby.network.topology.routers09
latency=1
link_id=9
weight=1
[system.ruby.network.topology.ext_links9.int_node]
type=BasicRouter
router_id=9
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=10
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers00
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=10
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=11
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers01
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links2]
@ -970,8 +830,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=12
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers02
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links3]
@ -979,8 +839,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=13
node_a=system.ruby.network.topology.ext_links3.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers03
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links4]
@ -988,8 +848,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=14
node_a=system.ruby.network.topology.ext_links4.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers04
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links5]
@ -997,8 +857,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=15
node_a=system.ruby.network.topology.ext_links5.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers05
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links6]
@ -1006,8 +866,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=16
node_a=system.ruby.network.topology.ext_links6.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers06
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links7]
@ -1015,8 +875,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=17
node_a=system.ruby.network.topology.ext_links7.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers07
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links8]
@ -1024,8 +884,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=18
node_a=system.ruby.network.topology.ext_links8.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers08
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links9]
@ -1033,10 +893,54 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=19
node_a=system.ruby.network.topology.ext_links9.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers09
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.routers00]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers01]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers02]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers03]
type=BasicRouter
router_id=3
[system.ruby.network.topology.routers04]
type=BasicRouter
router_id=4
[system.ruby.network.topology.routers05]
type=BasicRouter
router_id=5
[system.ruby.network.topology.routers06]
type=BasicRouter
router_id=6
[system.ruby.network.topology.routers07]
type=BasicRouter
router_id=7
[system.ruby.network.topology.routers08]
type=BasicRouter
router_id=8
[system.ruby.network.topology.routers09]
type=BasicRouter
router_id=9
[system.ruby.network.topology.routers10]
type=BasicRouter
router_id=10
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:30:17
gem5 started Jul 10 2012 17:31:57
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 14:40:22
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

108
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,111 +4,9 @@ sim_seconds 0.022495 # Nu
sim_ticks 22495354 # Number of ticks simulated
final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 170886 # Simulator tick rate (ticks/s)
host_mem_usage 380372 # Number of bytes of host memory used
host_seconds 131.64 # Real time elapsed on the host
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
host_tick_rate 256726 # Simulator tick rate (ticks/s)
host_mem_usage 370452 # Number of bytes of host memory used
host_seconds 87.62 # Real time elapsed on the host
system.cpu0.num_reads 99326 # number of read accesses completed
system.cpu0.num_writes 53132 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed

248
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
View file

@ -246,30 +246,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -307,30 +297,20 @@ version=1
[system.l1_cntrl1.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.sequencer]
type=RubySequencer
@ -368,30 +348,20 @@ version=2
[system.l1_cntrl2.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.sequencer]
type=RubySequencer
@ -429,30 +399,20 @@ version=3
[system.l1_cntrl3.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.sequencer]
type=RubySequencer
@ -490,30 +450,20 @@ version=4
[system.l1_cntrl4.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.sequencer]
type=RubySequencer
@ -551,30 +501,20 @@ version=5
[system.l1_cntrl5.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.sequencer]
type=RubySequencer
@ -612,30 +552,20 @@ version=6
[system.l1_cntrl6.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.sequencer]
type=RubySequencer
@ -673,30 +603,20 @@ version=7
[system.l1_cntrl7.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.sequencer]
type=RubySequencer
@ -731,16 +651,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -777,174 +692,119 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers00
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl1
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers01
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl2
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers02
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.ext_links3]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl3
int_node=system.ruby.network.topology.ext_links3.int_node
int_node=system.ruby.network.topology.routers03
latency=1
link_id=3
weight=1
[system.ruby.network.topology.ext_links3.int_node]
type=BasicRouter
router_id=3
[system.ruby.network.topology.ext_links4]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl4
int_node=system.ruby.network.topology.ext_links4.int_node
int_node=system.ruby.network.topology.routers04
latency=1
link_id=4
weight=1
[system.ruby.network.topology.ext_links4.int_node]
type=BasicRouter
router_id=4
[system.ruby.network.topology.ext_links5]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl5
int_node=system.ruby.network.topology.ext_links5.int_node
int_node=system.ruby.network.topology.routers05
latency=1
link_id=5
weight=1
[system.ruby.network.topology.ext_links5.int_node]
type=BasicRouter
router_id=5
[system.ruby.network.topology.ext_links6]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl6
int_node=system.ruby.network.topology.ext_links6.int_node
int_node=system.ruby.network.topology.routers06
latency=1
link_id=6
weight=1
[system.ruby.network.topology.ext_links6.int_node]
type=BasicRouter
router_id=6
[system.ruby.network.topology.ext_links7]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl7
int_node=system.ruby.network.topology.ext_links7.int_node
int_node=system.ruby.network.topology.routers07
latency=1
link_id=7
weight=1
[system.ruby.network.topology.ext_links7.int_node]
type=BasicRouter
router_id=7
[system.ruby.network.topology.ext_links8]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links8.int_node
int_node=system.ruby.network.topology.routers08
latency=1
link_id=8
weight=1
[system.ruby.network.topology.ext_links8.int_node]
type=BasicRouter
router_id=8
[system.ruby.network.topology.ext_links9]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links9.int_node
int_node=system.ruby.network.topology.routers09
latency=1
link_id=9
weight=1
[system.ruby.network.topology.ext_links9.int_node]
type=BasicRouter
router_id=9
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=10
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers00
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=10
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=11
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers01
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links2]
@ -952,8 +812,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=12
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers02
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links3]
@ -961,8 +821,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=13
node_a=system.ruby.network.topology.ext_links3.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers03
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links4]
@ -970,8 +830,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=14
node_a=system.ruby.network.topology.ext_links4.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers04
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links5]
@ -979,8 +839,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=15
node_a=system.ruby.network.topology.ext_links5.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers05
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links6]
@ -988,8 +848,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=16
node_a=system.ruby.network.topology.ext_links6.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers06
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links7]
@ -997,8 +857,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=17
node_a=system.ruby.network.topology.ext_links7.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers07
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links8]
@ -1006,8 +866,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=18
node_a=system.ruby.network.topology.ext_links8.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers08
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links9]
@ -1015,10 +875,54 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=19
node_a=system.ruby.network.topology.ext_links9.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers09
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.routers00]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers01]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers02]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers03]
type=BasicRouter
router_id=3
[system.ruby.network.topology.routers04]
type=BasicRouter
router_id=4
[system.ruby.network.topology.routers05]
type=BasicRouter
router_id=5
[system.ruby.network.topology.routers06]
type=BasicRouter
router_id=6
[system.ruby.network.topology.routers07]
type=BasicRouter
router_id=7
[system.ruby.network.topology.routers08]
type=BasicRouter
router_id=8
[system.ruby.network.topology.routers09]
type=BasicRouter
router_id=9
[system.ruby.network.topology.routers10]
type=BasicRouter
router_id=10
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:36:02
gem5 started Jul 10 2012 17:37:43
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:54:55
gem5 started Jun 4 2012 14:41:26
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

108
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,111 +4,9 @@ sim_seconds 0.019401 # Nu
sim_ticks 19400856 # Number of ticks simulated
final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 50488 # Simulator tick rate (ticks/s)
host_mem_usage 380584 # Number of bytes of host memory used
host_seconds 384.27 # Real time elapsed on the host
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
host_tick_rate 79524 # Simulator tick rate (ticks/s)
host_mem_usage 370632 # Number of bytes of host memory used
host_seconds 243.96 # Real time elapsed on the host
system.cpu0.num_reads 98844 # number of read accesses completed
system.cpu0.num_writes 53478 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed

248
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
View file

@ -255,30 +255,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -322,30 +312,20 @@ version=1
[system.l1_cntrl1.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.sequencer]
type=RubySequencer
@ -389,30 +369,20 @@ version=2
[system.l1_cntrl2.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.sequencer]
type=RubySequencer
@ -456,30 +426,20 @@ version=3
[system.l1_cntrl3.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.sequencer]
type=RubySequencer
@ -523,30 +483,20 @@ version=4
[system.l1_cntrl4.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.sequencer]
type=RubySequencer
@ -590,30 +540,20 @@ version=5
[system.l1_cntrl5.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.sequencer]
type=RubySequencer
@ -657,30 +597,20 @@ version=6
[system.l1_cntrl6.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.sequencer]
type=RubySequencer
@ -724,30 +654,20 @@ version=7
[system.l1_cntrl7.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.sequencer]
type=RubySequencer
@ -784,16 +704,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -830,174 +745,119 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers00
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl1
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers01
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl2
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers02
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.ext_links3]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl3
int_node=system.ruby.network.topology.ext_links3.int_node
int_node=system.ruby.network.topology.routers03
latency=1
link_id=3
weight=1
[system.ruby.network.topology.ext_links3.int_node]
type=BasicRouter
router_id=3
[system.ruby.network.topology.ext_links4]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl4
int_node=system.ruby.network.topology.ext_links4.int_node
int_node=system.ruby.network.topology.routers04
latency=1
link_id=4
weight=1
[system.ruby.network.topology.ext_links4.int_node]
type=BasicRouter
router_id=4
[system.ruby.network.topology.ext_links5]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl5
int_node=system.ruby.network.topology.ext_links5.int_node
int_node=system.ruby.network.topology.routers05
latency=1
link_id=5
weight=1
[system.ruby.network.topology.ext_links5.int_node]
type=BasicRouter
router_id=5
[system.ruby.network.topology.ext_links6]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl6
int_node=system.ruby.network.topology.ext_links6.int_node
int_node=system.ruby.network.topology.routers06
latency=1
link_id=6
weight=1
[system.ruby.network.topology.ext_links6.int_node]
type=BasicRouter
router_id=6
[system.ruby.network.topology.ext_links7]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl7
int_node=system.ruby.network.topology.ext_links7.int_node
int_node=system.ruby.network.topology.routers07
latency=1
link_id=7
weight=1
[system.ruby.network.topology.ext_links7.int_node]
type=BasicRouter
router_id=7
[system.ruby.network.topology.ext_links8]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links8.int_node
int_node=system.ruby.network.topology.routers08
latency=1
link_id=8
weight=1
[system.ruby.network.topology.ext_links8.int_node]
type=BasicRouter
router_id=8
[system.ruby.network.topology.ext_links9]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links9.int_node
int_node=system.ruby.network.topology.routers09
latency=1
link_id=9
weight=1
[system.ruby.network.topology.ext_links9.int_node]
type=BasicRouter
router_id=9
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=10
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers00
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=10
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=11
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers01
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links2]
@ -1005,8 +865,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=12
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers02
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links3]
@ -1014,8 +874,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=13
node_a=system.ruby.network.topology.ext_links3.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers03
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links4]
@ -1023,8 +883,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=14
node_a=system.ruby.network.topology.ext_links4.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers04
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links5]
@ -1032,8 +892,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=15
node_a=system.ruby.network.topology.ext_links5.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers05
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links6]
@ -1041,8 +901,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=16
node_a=system.ruby.network.topology.ext_links6.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers06
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links7]
@ -1050,8 +910,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=17
node_a=system.ruby.network.topology.ext_links7.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers07
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links8]
@ -1059,8 +919,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=18
node_a=system.ruby.network.topology.ext_links8.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers08
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.int_links9]
@ -1068,10 +928,54 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=19
node_a=system.ruby.network.topology.ext_links9.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers09
node_b=system.ruby.network.topology.routers10
weight=1
[system.ruby.network.topology.routers00]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers01]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers02]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers03]
type=BasicRouter
router_id=3
[system.ruby.network.topology.routers04]
type=BasicRouter
router_id=4
[system.ruby.network.topology.routers05]
type=BasicRouter
router_id=5
[system.ruby.network.topology.routers06]
type=BasicRouter
router_id=6
[system.ruby.network.topology.routers07]
type=BasicRouter
router_id=7
[system.ruby.network.topology.routers08]
type=BasicRouter
router_id=8
[system.ruby.network.topology.routers09]
type=BasicRouter
router_id=9
[system.ruby.network.topology.routers10]
type=BasicRouter
router_id=10
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:34:13
gem5 started Jul 10 2012 17:46:20
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:56:32
gem5 started Jun 4 2012 14:42:33
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

108
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,111 +4,9 @@ sim_seconds 0.019665 # Nu
sim_ticks 19665440 # Number of ticks simulated
final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 111694 # Simulator tick rate (ticks/s)
host_mem_usage 379960 # Number of bytes of host memory used
host_seconds 176.06 # Real time elapsed on the host
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
host_tick_rate 168119 # Simulator tick rate (ticks/s)
host_mem_usage 370164 # Number of bytes of host memory used
host_seconds 116.97 # Real time elapsed on the host
system.cpu0.num_reads 99534 # number of read accesses completed
system.cpu0.num_writes 53920 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed

273
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
View file

@ -220,16 +220,11 @@ version=0
[system.dir_cntrl0.probeFilter]
type=RubyCache
assoc=4
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=1024
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.funcmem]
type=SimpleMemory
@ -266,44 +261,29 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -344,44 +324,29 @@ version=1
[system.l1_cntrl1.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl1.sequencer]
type=RubySequencer
@ -422,44 +387,29 @@ version=2
[system.l1_cntrl2.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl2.sequencer]
type=RubySequencer
@ -500,44 +450,29 @@ version=3
[system.l1_cntrl3.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl3.sequencer]
type=RubySequencer
@ -578,44 +513,29 @@ version=4
[system.l1_cntrl4.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl4.sequencer]
type=RubySequencer
@ -656,44 +576,29 @@ version=5
[system.l1_cntrl5.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl5.sequencer]
type=RubySequencer
@ -734,44 +639,29 @@ version=6
[system.l1_cntrl6.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl6.sequencer]
type=RubySequencer
@ -812,44 +702,29 @@ version=7
[system.l1_cntrl7.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl7.sequencer]
type=RubySequencer
@ -902,160 +777,110 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl1
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl2
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.ext_links3]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl3
int_node=system.ruby.network.topology.ext_links3.int_node
int_node=system.ruby.network.topology.routers3
latency=1
link_id=3
weight=1
[system.ruby.network.topology.ext_links3.int_node]
type=BasicRouter
router_id=3
[system.ruby.network.topology.ext_links4]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl4
int_node=system.ruby.network.topology.ext_links4.int_node
int_node=system.ruby.network.topology.routers4
latency=1
link_id=4
weight=1
[system.ruby.network.topology.ext_links4.int_node]
type=BasicRouter
router_id=4
[system.ruby.network.topology.ext_links5]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl5
int_node=system.ruby.network.topology.ext_links5.int_node
int_node=system.ruby.network.topology.routers5
latency=1
link_id=5
weight=1
[system.ruby.network.topology.ext_links5.int_node]
type=BasicRouter
router_id=5
[system.ruby.network.topology.ext_links6]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl6
int_node=system.ruby.network.topology.ext_links6.int_node
int_node=system.ruby.network.topology.routers6
latency=1
link_id=6
weight=1
[system.ruby.network.topology.ext_links6.int_node]
type=BasicRouter
router_id=6
[system.ruby.network.topology.ext_links7]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl7
int_node=system.ruby.network.topology.ext_links7.int_node
int_node=system.ruby.network.topology.routers7
latency=1
link_id=7
weight=1
[system.ruby.network.topology.ext_links7.int_node]
type=BasicRouter
router_id=7
[system.ruby.network.topology.ext_links8]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links8.int_node
int_node=system.ruby.network.topology.routers8
latency=1
link_id=8
weight=1
[system.ruby.network.topology.ext_links8.int_node]
type=BasicRouter
router_id=8
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=9
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=9
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=10
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links2]
@ -1063,8 +888,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=11
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links3]
@ -1072,8 +897,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=12
node_a=system.ruby.network.topology.ext_links3.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers3
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links4]
@ -1081,8 +906,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=13
node_a=system.ruby.network.topology.ext_links4.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers4
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links5]
@ -1090,8 +915,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=14
node_a=system.ruby.network.topology.ext_links5.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers5
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links6]
@ -1099,8 +924,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=15
node_a=system.ruby.network.topology.ext_links6.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers6
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links7]
@ -1108,8 +933,8 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=16
node_a=system.ruby.network.topology.ext_links7.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers7
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.int_links8]
@ -1117,10 +942,50 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=17
node_a=system.ruby.network.topology.ext_links8.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers8
node_b=system.ruby.network.topology.routers9
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.network.topology.routers4]
type=BasicRouter
router_id=4
[system.ruby.network.topology.routers5]
type=BasicRouter
router_id=5
[system.ruby.network.topology.routers6]
type=BasicRouter
router_id=6
[system.ruby.network.topology.routers7]
type=BasicRouter
router_id=7
[system.ruby.network.topology.routers8]
type=BasicRouter
router_id=8
[system.ruby.network.topology.routers9]
type=BasicRouter
router_id=9
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 15:16:15
gem5 started Jul 10 2012 17:51:31
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:51:44
gem5 started Jun 4 2012 13:42:34
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

156
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
View file

@ -4,159 +4,9 @@ sim_seconds 0.019129 # Nu
sim_ticks 19129199 # Number of ticks simulated
final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 120686 # Simulator tick rate (ticks/s)
host_mem_usage 379940 # Number of bytes of host memory used
host_seconds 158.50 # Real time elapsed on the host
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl4.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl4.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl4.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl4.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl4.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl4.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl5.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl5.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl5.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl5.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl5.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl5.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl6.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl6.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl6.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl6.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl6.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl6.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl7.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl7.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl7.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl7.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl7.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl7.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl1.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl1.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl2.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl2.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl2.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl2.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl2.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl2.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl3.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl3.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl3.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl3.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl3.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl3.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads
system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes
system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
host_tick_rate 171697 # Simulator tick rate (ticks/s)
host_mem_usage 369968 # Number of bytes of host memory used
host_seconds 111.41 # Real time elapsed on the host
system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 53893 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed

73
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
View file

@ -93,30 +93,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -152,16 +142,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -198,76 +183,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -275,10 +240,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

6
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 17:30:17
gem5 started Jul 10 2012 17:34:42
gem5 executing on sc2b0605
gem5 compiled Jun 4 2012 11:53:20
gem5 started Jun 4 2012 14:40:53
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,26 +4,8 @@ sim_seconds 0.000350 # Nu
sim_ticks 349711 # Number of ticks simulated
final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 1546655 # Simulator tick rate (ticks/s)
host_mem_usage 230968 # Number of bytes of host memory used
host_seconds 0.23 # Real time elapsed on the host
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
host_tick_rate 2288501 # Simulator tick rate (ticks/s)
host_mem_usage 221264 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
---------- End Simulation Statistics ----------

73
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
View file

@ -90,30 +90,20 @@ version=0
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=256
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.l1_cntrl0.sequencer]
type=RubySequencer
@ -148,16 +138,11 @@ version=0
[system.l2_cntrl0.L2cacheMemory]
type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
resourceStalls=false
size=512
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
[system.physmem]
type=SimpleMemory
@ -194,76 +179,56 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
print_config=false
routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
[system.ruby.network.topology.ext_links0]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l1_cntrl0
int_node=system.ruby.network.topology.ext_links0.int_node
int_node=system.ruby.network.topology.routers0
latency=1
link_id=0
weight=1
[system.ruby.network.topology.ext_links0.int_node]
type=BasicRouter
router_id=0
[system.ruby.network.topology.ext_links1]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.l2_cntrl0
int_node=system.ruby.network.topology.ext_links1.int_node
int_node=system.ruby.network.topology.routers1
latency=1
link_id=1
weight=1
[system.ruby.network.topology.ext_links1.int_node]
type=BasicRouter
router_id=1
[system.ruby.network.topology.ext_links2]
type=SimpleExtLink
children=int_node
bandwidth_factor=16
ext_node=system.dir_cntrl0
int_node=system.ruby.network.topology.ext_links2.int_node
int_node=system.ruby.network.topology.routers2
latency=1
link_id=2
weight=1
[system.ruby.network.topology.ext_links2.int_node]
type=BasicRouter
router_id=2
[system.ruby.network.topology.int_links0]
type=SimpleIntLink
children=node_b
bandwidth_factor=16
latency=1
link_id=3
node_a=system.ruby.network.topology.ext_links0.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers0
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links0.node_b]
type=BasicRouter
router_id=3
[system.ruby.network.topology.int_links1]
type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=4
node_a=system.ruby.network.topology.ext_links1.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers1
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.int_links2]
@ -271,10 +236,26 @@ type=SimpleIntLink
bandwidth_factor=16
latency=1
link_id=5
node_a=system.ruby.network.topology.ext_links2.int_node
node_b=system.ruby.network.topology.int_links0.node_b
node_a=system.ruby.network.topology.routers2
node_b=system.ruby.network.topology.routers3
weight=1
[system.ruby.network.topology.routers0]
type=BasicRouter
router_id=0
[system.ruby.network.topology.routers1]
type=BasicRouter
router_id=1
[system.ruby.network.topology.routers2]
type=BasicRouter
router_id=2
[system.ruby.network.topology.routers3]
type=BasicRouter
router_id=3
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false

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