From b1a58933e07d7af0eb5f43942f8ad9bc93f28039 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 27 Jul 2012 16:08:05 -0400
Subject: [PATCH] stats: update stats for icache change not allowing dirty data

---
 .../alpha/linux/tsunami-o3-dual/config.ini    |    2 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |    9 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 2568 ++++++++-------
 .../ref/alpha/linux/tsunami-o3/config.ini     |    2 +-
 .../ref/alpha/linux/tsunami-o3/simout         |    9 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      | 1424 ++++-----
 .../arm/linux/realview-o3-checker/config.ini  |    4 +-
 .../ref/arm/linux/realview-o3-checker/simerr  |   33 +-
 .../ref/arm/linux/realview-o3-checker/simout  |    7 +-
 .../arm/linux/realview-o3-checker/stats.txt   |  978 ------
 .../ref/arm/linux/realview-o3-dual/config.ini |    4 +-
 .../ref/arm/linux/realview-o3-dual/simerr     |    2 +-
 .../ref/arm/linux/realview-o3-dual/simout     |    8 +-
 .../ref/arm/linux/realview-o3-dual/stats.txt  | 2810 ++++++++---------
 .../ref/arm/linux/realview-o3/config.ini      |    2 +-
 .../ref/arm/linux/realview-o3/simout          |    8 +-
 .../ref/arm/linux/realview-o3/stats.txt       | 1462 +++++----
 .../ref/x86/linux/pc-o3-timing/config.ini     |    6 +-
 .../ref/x86/linux/pc-o3-timing/simout         |   12 +-
 .../ref/x86/linux/pc-o3-timing/stats.txt      | 1658 +++++-----
 .../config.ini                                |  123 +-
 .../simerr                                    |    2 -
 .../simout                                    |   12 +-
 .../stats.txt                                 |  222 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1034 +++---
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1052 +++---
 .../tsunami-simple-atomic-dual/config.ini     |    8 +-
 .../linux/tsunami-simple-atomic-dual/simout   |    7 +-
 .../tsunami-simple-atomic-dual/stats.txt      |  116 +-
 .../linux/tsunami-simple-atomic/config.ini    |    8 +-
 .../alpha/linux/tsunami-simple-atomic/simout  |    7 +-
 .../linux/tsunami-simple-atomic/stats.txt     |   84 +-
 .../tsunami-simple-timing-dual/config.ini     |    2 +-
 .../linux/tsunami-simple-timing-dual/simout   |    9 +-
 .../tsunami-simple-timing-dual/stats.txt      | 1060 ++++---
 .../linux/tsunami-simple-timing/config.ini    |    2 +-
 .../alpha/linux/tsunami-simple-timing/simout  |    9 +-
 .../linux/tsunami-simple-timing/stats.txt     |  506 ++-
 .../realview-simple-atomic-dual/config.ini    |   10 +-
 .../linux/realview-simple-atomic-dual/simout  |    8 +-
 .../realview-simple-atomic-dual/stats.txt     |  984 +++---
 .../linux/realview-simple-atomic/config.ini   |    8 +-
 .../arm/linux/realview-simple-atomic/simout   |    8 +-
 .../linux/realview-simple-atomic/stats.txt    |  456 ++-
 .../realview-simple-timing-dual/config.ini    |    2 +-
 .../linux/realview-simple-timing-dual/simout  |    8 +-
 .../realview-simple-timing-dual/stats.txt     | 1624 +++++-----
 .../linux/realview-simple-timing/config.ini   |    4 +-
 .../arm/linux/realview-simple-timing/simout   |    8 +-
 .../linux/realview-simple-timing/stats.txt    |  846 +++--
 .../ref/x86/linux/pc-simple-atomic/config.ini |    6 +-
 .../ref/x86/linux/pc-simple-atomic/simout     |   10 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt  |   24 +-
 .../ref/x86/linux/pc-simple-timing/config.ini |    6 +-
 .../ref/x86/linux/pc-simple-timing/simout     |   10 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  |   24 +-
 .../config.ini                                |   75 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   75 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   75 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   65 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |    6 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   34 +-
 .../config.ini                                |   75 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   75 +-
 .../simout                                    |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   75 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    6 +-
 .../stats.txt                                 |   28 +-
 .../config.ini                                |   65 +-
 .../simple-timing-ruby-MOESI_hammer/simout    |    6 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   34 +-
 .../config.ini                                |  250 +-
 .../memtest-ruby-MESI_CMP_directory/simout    |    6 +-
 .../memtest-ruby-MESI_CMP_directory/stats.txt |  108 +-
 .../config.ini                                |  248 +-
 .../memtest-ruby-MOESI_CMP_directory/simout   |    6 +-
 .../stats.txt                                 |  108 +-
 .../memtest-ruby-MOESI_CMP_token/config.ini   |  248 +-
 .../linux/memtest-ruby-MOESI_CMP_token/simout |    6 +-
 .../memtest-ruby-MOESI_CMP_token/stats.txt    |  108 +-
 .../memtest-ruby-MOESI_hammer/config.ini      |  273 +-
 .../linux/memtest-ruby-MOESI_hammer/simout    |    6 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt |  156 +-
 .../config.ini                                |   73 +-
 .../rubytest-ruby-MESI_CMP_directory/simout   |    6 +-
 .../stats.txt                                 |   24 +-
 .../config.ini                                |   73 +-
 .../rubytest-ruby-MOESI_CMP_directory/simout  |    6 +-
 .../stats.txt                                 |   24 +-
 .../rubytest-ruby-MOESI_CMP_token/config.ini  |   73 +-
 .../rubytest-ruby-MOESI_CMP_token/simout      |    6 +-
 .../rubytest-ruby-MOESI_CMP_token/stats.txt   |   24 +-
 .../rubytest-ruby-MOESI_hammer/config.ini     |   63 +-
 .../linux/rubytest-ruby-MOESI_hammer/simout   |    6 +-
 .../rubytest-ruby-MOESI_hammer/stats.txt      |   30 +-
 108 files changed, 9834 insertions(+), 12302 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 1c28eff64..028711e47 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -1005,7 +1005,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 11f244941..acdd4bc1c 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 11:07:21
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 22:30:48
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 112168000
-Exiting @ tick 1900530800500 because m5_exit instruction encountered
+Exiting @ tick 1900530295500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 3f76d2026..a7a1d7396 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,218 +1,218 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.900531                       # Number of seconds simulated
-sim_ticks                                1900530800500                       # Number of ticks simulated
-final_tick                               1900530800500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.900530                       # Number of seconds simulated
+sim_ticks                                1900530295500                       # Number of ticks simulated
+final_tick                               1900530295500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119697                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119697                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3968630665                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303044                       # Number of bytes of host memory used
-host_seconds                                   478.89                       # Real time elapsed on the host
-sim_insts                                    57321719                       # Number of instructions simulated
-sim_ops                                      57321719                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           875648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24657536                       # Number of bytes read from this memory
+host_inst_rate                                 128893                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128893                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4273489918                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307500                       # Number of bytes of host memory used
+host_seconds                                   444.73                       # Real time elapsed on the host
+sim_insts                                    57321882                       # Number of instructions simulated
+sim_ops                                      57321882                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           875200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24658176                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           107456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           693056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28984512                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       875648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       107456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          983104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7921792                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7921792                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13682                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            385274                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst           108032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           692736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28984960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       875200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       108032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          983232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7922432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7922432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13675                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            385284                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1679                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10829                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                452883                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123778                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123778                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              460739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12974026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst              1688                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10824                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                452890                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123788                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123788                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              460503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12974366                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide           1394777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56540                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              364664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15250746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         460739                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56540                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4168200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4168200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4168200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             460739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12974026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              364496                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15250986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         460503                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517346                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4168538                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4168538                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4168538                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             460503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12974366                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide          1394777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56540                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             364664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19418945                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        345959                       # number of replacements
-system.l2c.tagsinuse                     65264.030293                       # Cycle average of tags in use
-system.l2c.total_refs                         2564962                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        411131                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.238795                       # Average number of references to valid blocks.
+system.physmem.bw_total::cpu1.inst              56843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             364496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19419523                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        345965                       # number of replacements
+system.l2c.tagsinuse                     65264.028554                       # Cycle average of tags in use
+system.l2c.total_refs                         2565305                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        411137                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.239538                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    6370050000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53566.099176                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          5313.179425                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          6099.564968                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           209.813021                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data            75.373703                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.817354                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.081073                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.093072                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.003201                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        53566.065326                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          5313.128544                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          6099.641645                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           209.824884                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data            75.368156                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.817353                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.081072                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.093073                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.003202                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.data            0.001150                       # Average percentage of cache occupancy
 system.l2c.occ_percent::total                0.995850                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             777532                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             689515                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             314287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             100987                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1882321                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          806312                       # number of Writeback hits
-system.l2c.Writeback_hits::total               806312                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             176                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             440                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 616                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            51                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                81                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           128023                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            44351                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172374                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              777532                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              817538                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              314287                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              145338                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2054695                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             777532                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             817538                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             314287                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             145338                       # number of overall hits
-system.l2c.overall_hits::total                2054695                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13684                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           272967                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1696                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              861                       # number of ReadReq misses
+system.l2c.ReadReq_hits::cpu0.inst             778193                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             689575                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             314248                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             100958                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1882974                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          806039                       # number of Writeback hits
+system.l2c.Writeback_hits::total               806039                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             174                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             439                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 613                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            52                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                83                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           128167                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            44386                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               172553                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              778193                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              817742                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              314248                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              145344                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2055527                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             778193                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             817742                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             314248                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             145344                       # number of overall hits
+system.l2c.overall_hits::total                2055527                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            13677                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           272973                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1705                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              853                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               289208                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2867                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1568                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4435                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          726                       # number of SCUpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2871                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1574                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4445                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          724                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data          747                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1473                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113091                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          10063                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             123154                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13684                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            386058                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1696                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10924                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                412362                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13684                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           386058                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1696                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10924                       # number of overall misses
-system.l2c.overall_misses::total               412362                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    728665998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14214168999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     90803000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     47077499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15080715496                       # number of ReadReq miss cycles
+system.l2c.SCUpgradeReq_misses::total            1471                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113108                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          10072                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             123180                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             13677                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            386081                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1705                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10925                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                412388                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13677                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           386081                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1705                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10925                       # number of overall misses
+system.l2c.overall_misses::total               412388                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    728382998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  14214430499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     91270500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     46668499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15080752496                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu0.data      2584000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     19661414                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     22245414                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2793000                       # number of SCUpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     19818914                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     22402914                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2792500                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu1.data       314000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      3107000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6061091997                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    549004499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6610096496                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    728665998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  20275260996                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     90803000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    596081998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21690811992                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    728665998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  20275260996                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     90803000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    596081998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21690811992                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         791216                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         962482                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         315983                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         101848                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2171529                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       806312                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           806312                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3043                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2008                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5051                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          777                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          777                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_miss_latency::total      3106500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   6061979997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    549631499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6611611496                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    728382998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  20276410496                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     91270500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    596299998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21692363992                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    728382998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  20276410496                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     91270500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    596299998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21692363992                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         791870                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         962548                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         315953                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         101811                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2172182                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       806039                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           806039                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3045                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2013                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5058                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          776                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          778                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total          1554                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       241114                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        54414                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295528                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          791216                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1203596                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          315983                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          156262                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2467057                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         791216                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1203596                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         315983                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         156262                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2467057                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.017295                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.283607                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.005367                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.008454                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.133182                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942162                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780876                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.878044                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.934363                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.961390                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.947876                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.469035                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.184934                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.416725                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.017295                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.320754                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005367                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.069908                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.167147                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.017295                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.320754                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005367                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.069908                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.167147                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52144.876684                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   901.290548                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5015.876888                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3847.107438                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_accesses::cpu0.data       241275                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        54458                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           295733                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          791870                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1203823                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          315953                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          156269                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2467915                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         791870                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1203823                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         315953                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         156269                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2467915                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.017272                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.283594                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.005396                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.008378                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.133142                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942857                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781918                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.878806                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.932990                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.960154                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.946589                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.468793                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.184950                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.416524                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.017272                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.320712                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005396                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.069911                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.167100                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.017272                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.320712                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005396                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.069911                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.167100                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52145.004620                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   900.034831                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5040.025647                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3857.044199                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   420.348059                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2109.300747                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53673.421050                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52601.384201                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52601.384201                       # average overall miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2111.828688                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53674.391102                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52601.831266                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52601.831266                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82258                       # number of writebacks
-system.l2c.writebacks::total                    82258                       # number of writebacks
+system.l2c.writebacks::writebacks               82268                       # number of writebacks
+system.l2c.writebacks::total                    82268                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
@@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total                 18                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13683                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       272967                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1679                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          861                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        13676                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       272973                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1688                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          853                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total          289190                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2867                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1568                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         4435                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          726                       # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2871                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1574                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         4445                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          724                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          747                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1473                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       113091                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        10063                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        123154                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13683                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       386058                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1679                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10924                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           412344                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13683                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       386058                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1679                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10924                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          412344                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561385998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10939069000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69521500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     36634000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11606610498                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    114796000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     62749500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    177545500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29087500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_misses::total         1471                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       113108                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        10072                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        123180                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13676                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       386081                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1688                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10925                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           412370                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13676                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       386081                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1688                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10925                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          412370                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561190998                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10939303500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69880000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     36325000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11606699498                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    114956000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     62989500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    177945500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29007500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     29880000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     58967500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4695316997                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    427005999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5122322996                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    561385998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  15634385997                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     69521500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    463639999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16728933494                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    561385998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  15634385997                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     69521500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    463639999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16728933494                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    820941530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     58887500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4696029997                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    427574999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5123604996                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    561190998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  15635333497                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     69880000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    463899999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16730304494                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    561190998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  15635333497                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     69880000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    463899999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16730304494                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    820944530                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16650000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    837591530                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1194248500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    837594530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1194274500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    359420000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1553668500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2015190030                       # number of overall MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1553694500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2015219030                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.data    376070000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2391260030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.283607                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008454                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.133173                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942162                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.780876                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.878044                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.934363                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.961390                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.947876                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.469035                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.184934                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.416725                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.320754                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.069908                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167140                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.320754                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.069908                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167140                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997                       # average SCUpgradeReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::total   2391289030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.283594                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008378                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.133133                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942857                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781918                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.878806                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.932990                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.960154                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.946589                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.468793                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.184950                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.416524                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.167092                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.167092                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40570.333251                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40570.333251                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -348,12 +348,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41698                       # number of replacements
-system.iocache.tagsinuse                     0.465240                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.465235                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1711281170000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       0.465240                       # Average occupied blocks per requestor
+system.iocache.occ_blocks::tsunami.ide       0.465235                       # Average occupied blocks per requestor
 system.iocache.occ_percent::tsunami.ide      0.029077                       # Average percentage of cache occupancy
 system.iocache.occ_percent::total            0.029077                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
@@ -366,12 +366,12 @@ system.iocache.overall_misses::tsunami.ide        41730                       #
 system.iocache.overall_misses::total            41730                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21238998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21238998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7637775806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7637775806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7659014804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7659014804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7659014804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7659014804                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7637828806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7637828806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7659067804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7659067804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7659067804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7659067804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -390,17 +390,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119320.213483                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183812.471265                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183537.378481                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183537.378481                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7710000                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183813.746775                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183538.648550                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183538.648550                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7685000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7151                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7152                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1078.170885                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1074.524609                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -416,12 +416,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41730
 system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11982000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     11982000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5476916000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5476916000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5488898000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5488898000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5488898000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5488898000                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5476969000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5476969000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5488951000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5488951000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5488951000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5488951000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -432,12 +432,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131533.620896                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131533.620896                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8334313                       # DTB read hits
-system.cpu0.dtb.read_misses                     29661                       # DTB read misses
-system.cpu0.dtb.read_acv                          416                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  650050                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5360515                       # DTB write hits
-system.cpu0.dtb.write_misses                     6017                       # DTB write misses
-system.cpu0.dtb.write_acv                         275                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 211537                       # DTB write accesses
-system.cpu0.dtb.data_hits                    13694828                       # DTB hits
-system.cpu0.dtb.data_misses                     35678                       # DTB misses
-system.cpu0.dtb.data_acv                          691                       # DTB access violations
-system.cpu0.dtb.data_accesses                  861587                       # DTB accesses
-system.cpu0.itb.fetch_hits                     972456                       # ITB hits
-system.cpu0.itb.fetch_misses                    29747                       # ITB misses
-system.cpu0.itb.fetch_acv                         802                       # ITB acv
-system.cpu0.itb.fetch_accesses                1002203                       # ITB accesses
+system.cpu0.dtb.read_hits                     8334041                       # DTB read hits
+system.cpu0.dtb.read_misses                     29708                       # DTB read misses
+system.cpu0.dtb.read_acv                          432                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  650283                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5360343                       # DTB write hits
+system.cpu0.dtb.write_misses                     6029                       # DTB write misses
+system.cpu0.dtb.write_acv                         281                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 211361                       # DTB write accesses
+system.cpu0.dtb.data_hits                    13694384                       # DTB hits
+system.cpu0.dtb.data_misses                     35737                       # DTB misses
+system.cpu0.dtb.data_acv                          713                       # DTB access violations
+system.cpu0.dtb.data_accesses                  861644                       # DTB accesses
+system.cpu0.itb.fetch_hits                     975254                       # ITB hits
+system.cpu0.itb.fetch_misses                    26821                       # ITB misses
+system.cpu0.itb.fetch_acv                         801                       # ITB acv
+system.cpu0.itb.fetch_accesses                1002075                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -483,143 +483,143 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       107494535                       # number of cpu cycles simulated
+system.cpu0.numCycles                       107505653                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                11769770                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           9862090                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            345528                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              8388023                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 5075121                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                11783453                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           9875598                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            345606                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              8356965                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 5072042                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  768289                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              29261                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          25151812                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      60423976                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   11769770                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5843410                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     11477495                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1678868                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              36441754                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               35468                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       189532                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       310248                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          196                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7504127                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               232204                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          74712100                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.808758                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.135218                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  768478                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              29315                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          25158431                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      60438649                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   11783453                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5840520                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     11478099                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1678793                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              36446213                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               35059                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       187963                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       310129                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          172                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7506544                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               232672                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          74721559                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.808852                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.135528                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                63234605     84.64%     84.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  741221      0.99%     85.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1559530      2.09%     87.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  686170      0.92%     88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2492076      3.34%     91.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  531561      0.71%     92.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  568906      0.76%     93.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  718608      0.96%     94.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4179423      5.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                63243460     84.64%     84.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  740935      0.99%     85.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1559450      2.09%     87.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  686263      0.92%     88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2492339      3.34%     91.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  528695      0.71%     92.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  568727      0.76%     93.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  718688      0.96%     94.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4183002      5.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            74712100                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.109492                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.562112                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26235752                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             36073897                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 10433111                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               896014                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1073325                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              504398                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                32602                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              59387121                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                93497                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1073325                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27172169                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               15317742                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17291837                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9793019                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              4064006                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              56407383                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 7139                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                656540                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1492805                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           37953017                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             68861567                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        68508934                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           352633                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33050954                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4902063                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1333181                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        200244                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 10589201                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8773580                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5638577                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1132250                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          738910                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  50116652                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1669804                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 48856794                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           108488                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5944129                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      3041029                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1132337                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     74712100                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.653934                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.297915                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            74721559                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.109608                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.562190                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26241114                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             36078495                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 10432905                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               895868                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1073176                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              504459                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                32663                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              59394337                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                93513                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1073176                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27177088                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               15322085                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17293060                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9793199                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              4062949                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              56409108                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 7164                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                656382                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1492215                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           37953965                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             68862069                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        68509500                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           352569                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33051447                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4902518                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1333146                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        200213                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 10586539                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             8773665                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5638420                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1132750                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          738704                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  50116530                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1671338                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 48856724                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           108345                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5942974                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3041199                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1133867                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     74721559                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.653850                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.297886                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           52667189     70.49%     70.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10185163     13.63%     84.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4563652      6.11%     90.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2983683      3.99%     94.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2257783      3.02%     97.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1142078      1.53%     98.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             582516      0.78%     99.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             283628      0.38%     99.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              46408      0.06%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           52677257     70.50%     70.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10184833     13.63%     84.13% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4563049      6.11%     90.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2984127      3.99%     94.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2257312      3.02%     97.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1142410      1.53%     98.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             582471      0.78%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             283512      0.38%     99.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              46588      0.06%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       74712100                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       74721559                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  73121     11.93%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                287582     46.92%     58.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               252262     41.15%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  73394     11.97%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                287556     46.90%     58.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               252163     41.13%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             4467      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             33934109     69.46%     69.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               53582      0.11%     69.58% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.58% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             33933939     69.46%     69.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               53607      0.11%     69.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.57% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd              16546      0.03%     69.61% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.61% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.61% # Type of FU issued
@@ -646,116 +646,116 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.61% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.61% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.61% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             8675974     17.76%     87.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5426955     11.11%     98.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            742930      1.52%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             8676123     17.76%     87.37% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5426873     11.11%     98.48% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            742938      1.52%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              48856794                       # Type of FU issued
-system.cpu0.iq.rate                          0.454505                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     612965                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.012546                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         172645923                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         57499135                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     47860626                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             501218                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            243758                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       236014                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              49202996                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 262296                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          518056                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              48856724                       # Type of FU issued
+system.cpu0.iq.rate                          0.454457                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     613113                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.012549                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         172655307                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         57499462                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     47860573                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             501158                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            243682                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       236026                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              49203092                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 262278                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          518007                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1116510                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2510                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        12661                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       476371                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1116542                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2532                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        12656                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       476196                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18849                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked        94368                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18844                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked        94055                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1073325                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               10798667                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               779958                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           54837290                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           559703                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8773580                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5638577                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1469305                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                544312                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 8344                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         12661                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        186183                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       327984                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              514167                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             48431427                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8385093                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           425367                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1073176                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               10803844                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               780020                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           54838073                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           560128                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              8773665                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5638420                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1470903                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                544426                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 8361                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         12656                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        186168                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       328100                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              514268                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             48431034                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8384906                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           425690                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3050834                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    13764236                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7758760                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5379143                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.450548                       # Inst execution rate
-system.cpu0.iew.wb_sent                      48183951                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     48096640                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 24100280                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 32401803                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3050205                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    13763900                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7759085                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5378994                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.450498                       # Inst execution rate
+system.cpu0.iew.wb_sent                      48183963                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     48096599                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 24100955                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 32404442                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.447433                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.743794                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.447387                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.743755                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      48294177                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        48294177                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        6449436                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         537467                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           480768                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     73638775                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.655825                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.560295                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      48294855                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        48294855                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        6449755                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         537471                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           480800                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     73648383                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.655749                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.560255                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     55222738     74.99%     74.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7735232     10.50%     85.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4278280      5.81%     91.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2283958      3.10%     94.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1242509      1.69%     96.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       524248      0.71%     96.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       435052      0.59%     97.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       385141      0.52%     97.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1531617      2.08%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     55233499     75.00%     75.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7733418     10.50%     85.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4278651      5.81%     91.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2283988      3.10%     94.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1242605      1.69%     96.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       524240      0.71%     96.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       434900      0.59%     97.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       385505      0.52%     97.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1531577      2.08%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     73638775                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            48294177                       # Number of instructions committed
-system.cpu0.commit.committedOps              48294177                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     73648383                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            48294855                       # Number of instructions committed
+system.cpu0.commit.committedOps              48294855                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      12819276                       # Number of memory references committed
-system.cpu0.commit.loads                      7657070                       # Number of loads committed
+system.cpu0.commit.refs                      12819347                       # Number of memory references committed
+system.cpu0.commit.loads                      7657123                       # Number of loads committed
 system.cpu0.commit.membars                     181890                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7325526                       # Number of branches committed
+system.cpu0.commit.branches                   7325688                       # Number of branches committed
 system.cpu0.commit.fp_insts                    233448                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 44748110                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              610965                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1531617                       # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts                 44748779                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              610967                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1531577                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   126666255                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  110560293                       # The number of ROB writes
-system.cpu0.timesIdled                        1221795                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       32782435                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3693291566                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   45532520                       # Number of Instructions Simulated
-system.cpu0.committedOps                     45532520                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             45532520                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.360830                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.360830                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.423580                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.423580                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                63860317                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               34945795                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   117013                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  117648                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1550179                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                750147                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   126676900                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  110562172                       # The number of ROB writes
+system.cpu0.timesIdled                        1222053                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       32784094                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3693280483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   45533193                       # Number of Instructions Simulated
+system.cpu0.committedOps                     45533193                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             45533193                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.361039                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.361039                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.423542                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.423542                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                63859411                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               34945756                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   117042                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  117632                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1550181                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                750158                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -787,247 +787,245 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                790628                       # number of replacements
-system.cpu0.icache.tagsinuse               510.000717                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 6669453                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                791140                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  8.430180                       # Average number of references to valid blocks.
+system.cpu0.icache.replacements                791282                       # number of replacements
+system.cpu0.icache.tagsinuse               510.000823                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 6671308                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                791794                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.425560                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           23654486000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   510.000717                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu0.inst   510.000823                       # Average occupied blocks per requestor
 system.cpu0.icache.occ_percent::cpu0.inst     0.996095                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_percent::total        0.996095                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6669453                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6669453                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6669453                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6669453                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6669453                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6669453                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       834673                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       834673                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       834673                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        834673                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       834673                       # number of overall misses
-system.cpu0.icache.overall_misses::total       834673                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13767352493                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13767352493                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13767352493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13767352493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13767352493                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13767352493                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7504126                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7504126                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7504126                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7504126                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7504126                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7504126                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111229                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.111229                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111229                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.111229                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111229                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.111229                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 16494.306744                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 16494.306744                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1480996                       # number of cycles access was blocked
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6671308                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6671308                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6671308                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6671308                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6671308                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6671308                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       835236                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       835236                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       835236                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        835236                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       835236                       # number of overall misses
+system.cpu0.icache.overall_misses::total       835236                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13775160993                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13775160993                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13775160993                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13775160993                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13775160993                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13775160993                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7506544                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7506544                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7506544                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7506544                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7506544                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7506544                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111268                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.111268                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111268                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.111268                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111268                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.111268                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16492.537430                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16492.537430                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1463996                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              158                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs  9141.950617                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  9265.797468                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks          247                       # number of writebacks
-system.cpu0.icache.writebacks::total              247                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43336                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43336                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        43336                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43336                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        43336                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43336                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791337                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       791337                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       791337                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       791337                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       791337                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       791337                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10689365997                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10689365997                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10689365997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10689365997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10689365997                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10689365997                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105454                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.105454                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.105454                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43249                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43249                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        43249                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43249                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        43249                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43249                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791987                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       791987                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       791987                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       791987                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       791987                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       791987                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10696262996                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10696262996                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10696262996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10696262996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10696262996                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10696262996                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105506                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.105506                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.105506                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1206208                       # number of replacements
-system.cpu0.dcache.tagsinuse               505.878050                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 9822290                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1206649                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                  8.140139                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements               1206262                       # number of replacements
+system.cpu0.dcache.tagsinuse               505.874752                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 9821312                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1206702                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  8.138971                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              19675000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   505.878050                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.988043                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.988043                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6113680                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6113680                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3377171                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3377171                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150549                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       150549                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171656                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       171656                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9490851                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9490851                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9490851                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9490851                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1478314                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1478314                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1593619                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1593619                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        18637                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18637                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4699                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         4699                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3071933                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3071933                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3071933                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3071933                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41272950000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  41272950000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  65317405497                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  65317405497                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    315155000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    315155000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68652000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     68652000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 106590355497                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 106590355497                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7591994                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7591994                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4970790                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4970790                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169186                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       169186                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176355                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       176355                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12562784                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12562784                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12562784                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12562784                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.194720                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.194720                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320597                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.320597                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110157                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110157                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026645                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026645                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244526                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.244526                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244526                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.244526                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs    716537144                       # number of cycles access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data   505.874752                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.988037                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.988037                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6113380                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6113380                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3377082                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3377082                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150588                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       150588                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171660                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       171660                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9490462                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9490462                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9490462                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9490462                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1478592                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1478592                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1593723                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1593723                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        18660                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18660                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4698                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         4698                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3072315                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3072315                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3072315                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3072315                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41280324500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  41280324500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  65318664554                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  65318664554                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    315332000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    315332000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68573000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     68573000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 106598989054                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 106598989054                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7591972                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7591972                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4970805                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4970805                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       169248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176358                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       176358                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12562777                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12562777                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12562777                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12562777                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.194757                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.194757                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320617                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.320617                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110252                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110252                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026639                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026639                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244557                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.244557                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244557                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.244557                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs    716919646                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            65430                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            65391                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       693284                       # number of writebacks
-system.cpu0.dcache.writebacks::total           693284                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       515563                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       515563                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1344321                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1344321                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3732                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3732                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1859884                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1859884                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1859884                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1859884                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       962751                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       962751                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249298                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249298                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14905                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14905                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4699                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         4699                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1212049                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1212049                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1212049                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1212049                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25942792600                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25942792600                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8699231964                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8699231964                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186934001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186934001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     54037501                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     54037501                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34642024564                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  34642024564                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34642024564                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  34642024564                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    918343000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    918343000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1327727998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1327727998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2246070998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2246070998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126811                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126811                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050153                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050153                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088098                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088098                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026645                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026645                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096479                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096479                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096479                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096479                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       693314                       # number of writebacks
+system.cpu0.dcache.writebacks::total           693314                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       515793                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       515793                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1344404                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1344404                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3762                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3762                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1860197                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1860197                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1860197                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1860197                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       962799                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       962799                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249319                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249319                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14898                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14898                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4698                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         4698                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1212118                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1212118                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1212118                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1212118                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25944695097                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25944695097                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8701407966                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8701407966                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186837501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186837501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     53961001                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     53961001                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34646103063                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  34646103063                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34646103063                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  34646103063                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    918480000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    918480000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1327721998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1327721998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2246201998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2246201998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126818                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126818                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050157                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050157                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088025                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088025                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026639                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.096485                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.096485                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1039,22 +1037,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2499316                       # DTB read hits
-system.cpu1.dtb.read_misses                     12569                       # DTB read misses
+system.cpu1.dtb.read_hits                     2497958                       # DTB read hits
+system.cpu1.dtb.read_misses                     12385                       # DTB read misses
 system.cpu1.dtb.read_acv                          105                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  313735                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1734639                       # DTB write hits
-system.cpu1.dtb.write_misses                     3525                       # DTB write misses
-system.cpu1.dtb.write_acv                         140                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 132367                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4233955                       # DTB hits
-system.cpu1.dtb.data_misses                     16094                       # DTB misses
-system.cpu1.dtb.data_acv                          245                       # DTB access violations
-system.cpu1.dtb.data_accesses                  446102                       # DTB accesses
-system.cpu1.itb.fetch_hits                     489806                       # ITB hits
-system.cpu1.itb.fetch_misses                     8851                       # ITB misses
-system.cpu1.itb.fetch_acv                         360                       # ITB acv
-system.cpu1.itb.fetch_accesses                 498657                       # ITB accesses
+system.cpu1.dtb.read_accesses                  312687                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1734137                       # DTB write hits
+system.cpu1.dtb.write_misses                     3404                       # DTB write misses
+system.cpu1.dtb.write_acv                         137                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 131810                       # DTB write accesses
+system.cpu1.dtb.data_hits                     4232095                       # DTB hits
+system.cpu1.dtb.data_misses                     15789                       # DTB misses
+system.cpu1.dtb.data_acv                          242                       # DTB access violations
+system.cpu1.dtb.data_accesses                  444497                       # DTB accesses
+system.cpu1.itb.fetch_hits                     488697                       # ITB hits
+system.cpu1.itb.fetch_misses                     8773                       # ITB misses
+system.cpu1.itb.fetch_acv                         366                       # ITB acv
+system.cpu1.itb.fetch_accesses                 497470                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1067,144 +1065,144 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        22717311                       # number of cpu cycles simulated
+system.cpu1.numCycles                        22715640                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 3442703                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           2849702                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            108899                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              2361843                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 1192387                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 3441563                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           2848590                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            108508                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              2344214                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 1191088                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  236332                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              10679                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles           9037199                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      16321027                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3442703                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1428719                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      2924126                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 526603                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               8306285                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               28121                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        87140                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        64229                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1963514                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                75345                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          20778311                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.785484                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.154367                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  236176                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              10617                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles           9035553                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      16314409                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3441563                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1427264                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      2922038                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 525528                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               8308395                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               28029                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        86548                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        64086                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1962045                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                75286                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          20775175                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.785284                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.154306                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                17854185     85.93%     85.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  203613      0.98%     86.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  301133      1.45%     88.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  225724      1.09%     89.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  404540      1.95%     91.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  151692      0.73%     92.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  164507      0.79%     92.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  309022      1.49%     94.40% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1163895      5.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                17853137     85.93%     85.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  203247      0.98%     86.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  300737      1.45%     88.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  225181      1.08%     89.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  403762      1.94%     91.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  151742      0.73%     92.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  164996      0.79%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  308573      1.49%     94.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1163800      5.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            20778311                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.151545                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.718440                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 8812255                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8762880                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2709089                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               172906                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                321180                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              151088                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                10133                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              16020033                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                29351                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                321180                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 9094333                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 882455                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6951469                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2594850                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               934022                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              14843152                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  114                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 83650                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents               279958                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands            9660007                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             17630674                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        17422680                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           207994                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              8331005                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1328994                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            594043                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         64597                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2775458                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2641121                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1825529                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           246953                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          159017                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  12975245                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             664400                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 12700763                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            35708                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1746535                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       829425                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        468662                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     20778311                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.611251                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.284414                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            20775175                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.151506                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.718202                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 8809071                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              8765539                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2707216                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               172890                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                320458                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              151147                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                10158                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              16014026                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                29482                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                320458                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 9091295                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 884150                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       6951341                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2592964                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               934965                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              14837454                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  127                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 84091                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               280482                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            9656446                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             17623003                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        17415204                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           207799                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              8330618                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1325820                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            594023                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         64559                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2775443                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2639269                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1825014                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           248716                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          160479                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  12970444                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             664664                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 12696455                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            35550                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1743951                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       828101                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        468923                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     20775175                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.611136                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.284217                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           15115816     72.75%     72.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2653114     12.77%     85.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            1112593      5.35%     90.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             724594      3.49%     94.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             603153      2.90%     97.26% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             287847      1.39%     98.65% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             182303      0.88%     99.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              88112      0.42%     99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              10779      0.05%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           15113498     72.75%     72.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2653136     12.77%     85.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1113601      5.36%     90.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             723121      3.48%     94.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             602829      2.90%     97.26% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             288191      1.39%     98.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             181892      0.88%     99.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              88125      0.42%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              10782      0.05%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       20778311                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       20775175                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                   3869      1.53%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                134765     53.16%     54.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               114892     45.32%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                   3857      1.52%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                134714     53.16%     54.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               114823     45.31%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass             2823      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7927502     62.42%     62.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               20764      0.16%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              10543      0.08%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              7925481     62.42%     62.45% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               20760      0.16%     62.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10544      0.08%     62.69% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.69% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.69% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.69% # Type of FU issued
@@ -1230,357 +1228,355 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.70% # Ty
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.70% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.70% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2623377     20.66%     83.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1764952     13.90%     97.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            349391      2.75%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2621698     20.65%     83.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1764339     13.90%     97.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            349399      2.75%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              12700763                       # Type of FU issued
-system.cpu1.iq.rate                          0.559079                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     253526                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019961                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          46169663                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         15243166                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     12341001                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             299407                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            145151                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       140846                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              12794667                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 156799                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          115193                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              12696455                       # Type of FU issued
+system.cpu1.iq.rate                          0.558930                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     253394                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019958                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          46157750                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         15236198                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     12337265                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             299278                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            145041                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       140795                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              12790304                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 156722                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          115188                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       347930                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          808                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         2222                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       153073                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       346106                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          806                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         2268                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       152574                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          370                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        11635                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          376                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        11381                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                321180                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 537224                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                73444                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           14366092                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           206312                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2641121                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1825529                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            596088                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 55197                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 6016                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          2222                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         53937                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       130013                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              183950                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             12579473                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2523314                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           121289                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                320458                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 536973                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                73252                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           14361364                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           205800                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2639269                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1825014                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            596393                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 55379                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 5710                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          2268                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         53644                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       129908                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              183552                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             12575424                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2521777                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           121030                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       726447                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     4269906                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1887172                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1746592                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.553740                       # Inst execution rate
-system.cpu1.iew.wb_sent                      12515990                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     12481847                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5700900                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  8040202                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       726256                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     4267761                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1886646                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1745984                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.553602                       # Inst execution rate
+system.cpu1.iew.wb_sent                      12512047                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     12478060                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5698826                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  8037620                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.549442                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.709049                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.549316                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.709019                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      12433159                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps        12433159                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts        1857667                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         195738                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           173364                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     20457131                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.607767                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.554530                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      12432644                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        12432644                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts        1853978                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         195741                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           172939                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     20454717                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.607813                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.554325                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     15844350     77.45%     77.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      2122437     10.38%     87.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       810532      3.96%     91.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       497134      2.43%     94.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       362445      1.77%     95.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       133722      0.65%     96.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       129038      0.63%     97.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       154146      0.75%     98.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       403327      1.97%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     15840554     77.44%     77.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      2123906     10.38%     87.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       810748      3.96%     91.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       497113      2.43%     94.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       362163      1.77%     95.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       133438      0.65%     96.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       130960      0.64%     97.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       152379      0.74%     98.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       403456      1.97%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     20457131                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            12433159                       # Number of instructions committed
-system.cpu1.commit.committedOps              12433159                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     20454717                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            12432644                       # Number of instructions committed
+system.cpu1.commit.committedOps              12432644                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3965647                       # Number of memory references committed
-system.cpu1.commit.loads                      2293191                       # Number of loads committed
-system.cpu1.commit.membars                      64658                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1777478                       # Number of branches committed
+system.cpu1.commit.refs                       3965603                       # Number of memory references committed
+system.cpu1.commit.loads                      2293163                       # Number of loads committed
+system.cpu1.commit.membars                      64660                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1777364                       # Number of branches committed
 system.cpu1.commit.fp_insts                    139699                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 11488003                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                 11487490                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls              194670                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               403327                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events               403456                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    34238592                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   28901418                       # The number of ROB writes
-system.cpu1.timesIdled                         230949                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        1939000                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3778341690                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   11789199                       # Number of Instructions Simulated
-system.cpu1.committedOps                     11789199                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             11789199                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.926960                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.926960                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.518952                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.518952                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                16196586                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                8796247                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    73611                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   74214                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 699711                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                299448                       # number of misc regfile writes
-system.cpu1.icache.replacements                315447                       # number of replacements
-system.cpu1.icache.tagsinuse               471.003081                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1635327                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                315959                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                  5.175757                       # Average number of references to valid blocks.
+system.cpu1.rob.rob_reads                    34231845                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   28892260                       # The number of ROB writes
+system.cpu1.timesIdled                         230897                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        1940465                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3778342351                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   11788689                       # Number of Instructions Simulated
+system.cpu1.committedOps                     11788689                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             11788689                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.926901                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.926901                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.518968                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.518968                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                16191128                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                8793643                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    73550                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   74224                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 699686                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                299450                       # number of misc regfile writes
+system.cpu1.icache.replacements                315418                       # number of replacements
+system.cpu1.icache.tagsinuse               471.006638                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1633897                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                315930                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                  5.171706                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          1877367216000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   471.003081                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.919928                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.919928                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1635327                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1635327                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1635327                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1635327                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1635327                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1635327                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       328187                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       328187                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       328187                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        328187                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       328187                       # number of overall misses
-system.cpu1.icache.overall_misses::total       328187                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5323842998                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5323842998                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5323842998                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5323842998                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5323842998                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5323842998                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1963514                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1963514                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1963514                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1963514                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1963514                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1963514                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.167143                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.167143                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.167143                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.167143                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.167143                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.167143                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 16221.980145                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 16221.980145                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       228998                       # number of cycles access was blocked
+system.cpu1.icache.occ_blocks::cpu1.inst   471.006638                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.919935                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.919935                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1633897                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1633897                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1633897                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1633897                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1633897                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1633897                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       328148                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       328148                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       328148                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        328148                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       328148                       # number of overall misses
+system.cpu1.icache.overall_misses::total       328148                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5323185498                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5323185498                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5323185498                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5323185498                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5323185498                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5323185498                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1962045                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1962045                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1962045                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1962045                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1962045                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1962045                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.167248                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.167248                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.167248                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.167248                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.167248                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.167248                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 16221.904439                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 16221.904439                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       248998                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               37                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               42                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  6189.135135                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5928.523810                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks           38                       # number of writebacks
-system.cpu1.icache.writebacks::total               38                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12173                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        12173                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        12173                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        12173                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        12173                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        12173                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316014                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       316014                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       316014                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       316014                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       316014                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       316014                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4183208998                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4183208998                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4183208998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4183208998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4183208998                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4183208998                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.160943                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.160943                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.160943                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12162                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        12162                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        12162                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        12162                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        12162                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        12162                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       315986                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       315986                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       315986                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       315986                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       315986                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       315986                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4183764998                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4183764998                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4183764998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4183764998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4183764998                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4183764998                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.161049                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.161049                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.161049                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                159076                       # number of replacements
-system.cpu1.dcache.tagsinuse               488.854290                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3388834                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                159588                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 21.234892                       # Average number of references to valid blocks.
+system.cpu1.dcache.replacements                159031                       # number of replacements
+system.cpu1.dcache.tagsinuse               488.853384                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 3387429                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                159543                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 21.232075                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle           42819944000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   488.854290                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.954794                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.954794                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2022458                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2022458                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1251052                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1251052                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        49972                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        49972                       # number of LoadLockedReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   488.853384                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.954792                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.954792                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2021122                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2021122                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1250999                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1250999                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        49956                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        49956                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48601                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        48601                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3273510                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3273510                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3273510                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3273510                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       307183                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       307183                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       360837                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       360837                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8700                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8700                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5048                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5048                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       668020                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        668020                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       668020                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       668020                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6372115000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6372115000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11323925707                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11323925707                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    121529000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    121529000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     68413000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     68413000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  17696040707                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  17696040707                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  17696040707                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  17696040707                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2329641                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2329641                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1611889                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1611889                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        58672                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        58672                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        53649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        53649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3941530                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3941530                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3941530                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3941530                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131859                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.131859                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223860                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.223860                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148282                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.148282                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094093                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094093                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.169482                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.169482                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.169482                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.169482                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     57515988                       # number of cycles access was blocked
+system.cpu1.dcache.demand_hits::cpu1.data      3272121                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3272121                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3272121                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3272121                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       307358                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       307358                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       360875                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       360875                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8692                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8692                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5047                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         5047                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       668233                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        668233                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       668233                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       668233                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6376981500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   6376981500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11324805298                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11324805298                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    121402000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    121402000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     68410000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     68410000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  17701786798                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  17701786798                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  17701786798                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  17701786798                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2328480                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2328480                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1611874                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1611874                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        58648                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        58648                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        53648                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        53648                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3940354                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3940354                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3940354                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3940354                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131999                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.131999                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223885                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.223885                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148206                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.148206                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094076                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094076                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.169587                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.169587                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.169587                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.169587                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     57267488                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6825                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6761                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8427.250989                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8470.268895                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       112743                       # number of writebacks
-system.cpu1.dcache.writebacks::total           112743                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       196860                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       196860                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       298722                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       298722                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1021                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1021                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       495582                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       495582                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       495582                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       495582                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110323                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       110323                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62115                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        62115                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7679                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7679                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5048                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5048                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       172438                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       172438                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       172438                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       172438                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1760210564                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1760210564                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1471458330                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1471458330                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     78242000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     78242000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52885501                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52885501                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3231668894                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3231668894                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3231668894                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3231668894                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18623000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18623000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    400648500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    400648500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    419271500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    419271500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.047356                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.047356                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038536                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038536                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130880                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130880                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094093                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094093                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043749                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043749                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043749                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043749                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       112725                       # number of writebacks
+system.cpu1.dcache.writebacks::total           112725                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       197085                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       197085                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       298748                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       298748                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1016                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1016                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       495833                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       495833                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       495833                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       495833                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110273                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       110273                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62127                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        62127                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7676                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7676                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5047                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         5047                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       172400                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       172400                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       172400                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       172400                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1761266064                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1761266064                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1471935334                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1471935334                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     78208000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     78208000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52884501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52884501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3233201398                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3233201398                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3233201398                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3233201398                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18624000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18624000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    400633000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    400633000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    419257000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    419257000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.047358                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.047358                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038543                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038543                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130883                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130883                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094076                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094076                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.043752                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.043752                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1590,31 +1586,31 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6699                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    167510                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    167511                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   58590     40.24%     40.24% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    238      0.16%     40.40% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1924      1.32%     41.72% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    340      0.23%     41.96% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  84509     58.04%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              145601                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  84510     58.04%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              145602                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    57892     49.08%     49.08% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     238      0.20%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1924      1.63%     50.92% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     340      0.29%     51.20% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   57552     48.80%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               117946                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1862592276000     98.01%     98.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               96187500      0.01%     98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              394889000      0.02%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              155178500      0.01%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            37157854000      1.96%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1900396385000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1862592154000     98.01%     98.01% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               96215500      0.01%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              394866000      0.02%     98.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              155183500      0.01%     98.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            37157983500      1.96%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1900396402500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.988087                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.681016                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810063                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.681008                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810058                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         5      2.38%      2.38% # number of syscalls executed
 system.cpu0.kern.syscall::3                        18      8.57%     10.95% # number of syscalls executed
 system.cpu0.kern.syscall::4                         3      1.43%     12.38% # number of syscalls executed
@@ -1654,7 +1650,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.29% # nu
 system.cpu0.kern.callpal::swpctx                 3076      2.00%      2.29% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      37      0.02%      2.32% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.32% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               138810     90.43%     92.75% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               138811     90.43%     92.75% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6361      4.14%     96.89% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.89% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.89% # number of callpals executed
@@ -1663,44 +1659,44 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.90% # nu
 system.cpu0.kern.callpal::rti                    4288      2.79%     99.69% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 327      0.21%     99.90% # number of callpals executed
 system.cpu0.kern.callpal::imb                     146      0.10%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                153507                       # number of callpals executed
+system.cpu0.kern.callpal::total                153508                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             6690                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1098                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1099                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1098                      
-system.cpu0.kern.mode_good::user                 1098                      
+system.cpu0.kern.mode_good::kernel               1099                      
+system.cpu0.kern.mode_good::user                 1099                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.164126                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.164275                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.281972                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1897963397000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1861803000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.282193                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1897960603000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1864923000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3077                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2601                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     74467                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   24565     38.36%     38.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1923      3.00%     41.36% # number of times we switched to this ipl
+system.cpu1.kern.inst.hwrei                     74469                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   24566     38.36%     38.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1923      3.00%     41.37% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::30                    439      0.69%     42.05% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  37108     57.95%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               64035                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    23886     48.07%     48.07% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_count::31                  37109     57.95%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               64037                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    23887     48.07%     48.07% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::22                    1923      3.87%     51.93% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::30                     439      0.88%     52.82% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   23447     47.18%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                49695                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870827437000     98.44%     98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              343518500      0.02%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              182737500      0.01%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            29176221000      1.54%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1900529914000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.972359                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_good::31                   23448     47.18%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                49697                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1870827131500     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              343570500      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              182754500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29175936000      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900529392500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.972360                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.631858                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.776060                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.631868                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.776067                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::2                         3      2.59%      2.59% # number of syscalls executed
 system.cpu1.kern.syscall::3                        12     10.34%     12.93% # number of syscalls executed
 system.cpu1.kern.syscall::4                         1      0.86%     13.79% # number of syscalls executed
@@ -1730,9 +1726,9 @@ system.cpu1.kern.callpal::wrfen                     1      0.00%      0.52% # nu
 system.cpu1.kern.callpal::swpctx                 1824      2.74%      3.26% # number of callpals executed
 system.cpu1.kern.callpal::tbi                      16      0.02%      3.28% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      3.29% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                57992     87.22%     90.51% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                57994     87.22%     90.51% # number of callpals executed
 system.cpu1.kern.callpal::rdps                   2394      3.60%     94.11% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.11% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.12% # number of callpals executed
 system.cpu1.kern.callpal::wrusp                     4      0.01%     94.12% # number of callpals executed
 system.cpu1.kern.callpal::rdusp                     3      0.00%     94.13% # number of callpals executed
 system.cpu1.kern.callpal::whami                     3      0.00%     94.13% # number of callpals executed
@@ -1740,7 +1736,7 @@ system.cpu1.kern.callpal::rti                    3680      5.53%     99.66% # nu
 system.cpu1.kern.callpal::callsys                 188      0.28%     99.95% # number of callpals executed
 system.cpu1.kern.callpal::imb                      34      0.05%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 66490                       # number of callpals executed
+system.cpu1.kern.callpal::total                 66492                       # number of callpals executed
 system.cpu1.kern.mode_switch::kernel             2119                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                641                       # number of protection mode switches
 system.cpu1.kern.mode_switch::idle               2717                       # number of protection mode switches
@@ -1751,9 +1747,9 @@ system.cpu1.kern.mode_switch_good::kernel     0.473336                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.133235                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.366259                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        7877043500      0.41%      0.41% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           912149500      0.05%      0.46% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1891740713000     99.54%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        7877089500      0.41%      0.41% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           911545000      0.05%      0.46% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1891740750000     99.54%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    1825                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index b1df0f096..353ee4820 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -581,7 +581,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index a30a37ba8..f67dea3de 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 11:00:25
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 22:30:38
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1865402113500 because m5_exit instruction encountered
+Exiting @ tick 1864423957500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index a9a5c3cb0..0374f29ea 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,142 +1,146 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.865402                       # Number of seconds simulated
-sim_ticks                                1865402113500                       # Number of ticks simulated
-final_tick                               1865402113500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.864424                       # Number of seconds simulated
+sim_ticks                                1864423957500                       # Number of ticks simulated
+final_tick                               1864423957500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131129                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131129                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4607058697                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298956                       # Number of bytes of host memory used
-host_seconds                                   404.90                       # Real time elapsed on the host
-sim_insts                                    53094243                       # Number of instructions simulated
-sim_ops                                      53094243                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            967424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24877312                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28497024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       967424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          967424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7516928                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7516928                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15116                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388708                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445266                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117452                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117452                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               518614                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13336166                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1421832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15276612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          518614                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518614                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4029656                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4029656                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4029656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              518614                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13336166                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1421832                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19306267                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        338323                       # number of replacements
-system.l2c.tagsinuse                     65346.781313                       # Cycle average of tags in use
-system.l2c.total_refs                         2566599                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        403491                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.360982                       # Average number of references to valid blocks.
+host_inst_rate                                 128916                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128916                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4527170908                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303408                       # Number of bytes of host memory used
+host_seconds                                   411.83                       # Real time elapsed on the host
+sim_insts                                    53091408                       # Number of instructions simulated
+sim_ops                                      53091408                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            967616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24878144                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652032                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28497792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       967616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          967616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7517760                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7517760                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15119                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388721                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41438                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                445278                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117465                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117465                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               518989                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13343609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1422440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15285039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          518989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4032216                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4032216                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4032216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              518989                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13343609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1422440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19317254                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        338334                       # number of replacements
+system.l2c.tagsinuse                     65348.280232                       # Cycle average of tags in use
+system.l2c.total_refs                         2564971                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        403499                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.356821                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    4861120000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53937.288272                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           5357.413768                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6052.079273                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.823018                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.081748                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.092347                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.997113                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst             1010692                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              829338                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1840030                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          843192                       # number of Writeback hits
-system.l2c.Writeback_hits::total               843192                       # number of Writeback hits
+system.l2c.occ_blocks::writebacks        53937.270475                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5353.133006                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6057.876752                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.823017                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.081682                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.092436                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.997136                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst             1009873                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              829098                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1838971                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          842689                       # number of Writeback hits
+system.l2c.Writeback_hits::total               842689                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               35                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  35                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data              4                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 4                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            185767                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185767                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst              1010692                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1015105                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2025797                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst             1010692                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1015105                       # number of overall hits
-system.l2c.overall_hits::total                2025797                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             15118                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            273845                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               288963                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data             49                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                49                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          115352                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115352                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              15118                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             389197                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                404315                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             15118                       # number of overall misses
-system.l2c.overall_misses::cpu.data            389197                       # number of overall misses
-system.l2c.overall_misses::total               404315                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    805739998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14260725000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15066464998                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       501500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       501500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6190534997                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6190534997                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    805739998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20451259997                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21256999995                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    805739998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20451259997                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21256999995                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst         1025810                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1103183                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2128993                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       843192                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           843192                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           84                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              84                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            185872                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185872                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst              1009873                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1014970                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2024843                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst             1009873                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1014970                       # number of overall hits
+system.l2c.overall_hits::total                2024843                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.inst             15121                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            273859                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               288980                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data             50                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                50                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          115376                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115376                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.inst              15121                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             389235                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                404356                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.inst             15121                       # number of overall misses
+system.l2c.overall_misses::cpu.data            389235                       # number of overall misses
+system.l2c.overall_misses::total               404356                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.inst    805852997                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  14261584000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15067436997                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       397000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       397000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6192128996                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6192128996                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    805852997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20453712996                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21259565993                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    805852997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  20453712996                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21259565993                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst         1024994                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1102957                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2127951                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       842689                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           842689                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           85                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              85                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        301119                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           301119                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst          1025810                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1404302                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2430112                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1025810                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1404302                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2430112                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014738                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.248232                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.135728                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.583333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.583333                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383078                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383078                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014738                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.277146                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.166377                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014738                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.277146                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.166377                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52139.772213                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53666.473030                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52547.321786                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52575.343470                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52547.321786                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52575.343470                       # average overall miss latency
+system.l2c.ReadExReq_accesses::cpu.data        301248                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           301248                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst          1024994                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1404205                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2429199                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1024994                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1404205                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2429199                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.014752                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.248295                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.135802                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.588235                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.588235                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.382993                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.382993                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.014752                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.277192                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.166457                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.014752                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.277192                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.166457                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53293.631175                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52076.375069                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52140.068506                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data         7940                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total         7940                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53669.125260                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53669.125260                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53293.631175                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52548.493830                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52576.358439                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53293.631175                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52548.493830                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52576.358439                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -145,72 +149,80 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75940                       # number of writebacks
-system.l2c.writebacks::total                    75940                       # number of writebacks
+system.l2c.writebacks::writebacks               75953                       # number of writebacks
+system.l2c.writebacks::total                    75953                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.inst        15117                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       273845                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          288962                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data           49                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           49                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       115352                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        115352                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         15117                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        389197                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           404314                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        15117                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       389197                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          404314                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    620965998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10975082500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11596048498                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2065000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      2065000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4796966997                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4796966997                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    620965998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15772049497                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16393015495                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    620965998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15772049497                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16393015495                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    810224030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    810224030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1103797000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1103797000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   1914021030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1914021030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248232                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.135727                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.583333                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.583333                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383078                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383078                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.277146                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.166377                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.277146                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.166377                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40545.258129                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40545.258129                       # average overall mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu.inst        15120                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       273859                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          288979                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data           50                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           50                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       115376                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        115376                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         15120                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        389235                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           404355                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        15120                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       389235                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          404355                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    621011997                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  10975832000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11596843997                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2105000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      2105000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        40000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        40000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4797954496                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4797954496                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    621011997                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15773786496                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16394798493                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    621011997                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15773786496                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16394798493                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    809342530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    809342530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1103231500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1103231500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   1912574030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1912574030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248295                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.135802                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.588235                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.588235                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.382993                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.382993                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.277192                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.166456                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.277192                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.166456                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        42100                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        42100                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40545.556486                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40545.556486                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -219,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.294799                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.287077                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1711277767000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.294799                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.080925                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.080925                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1711278506000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.287077                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.080442                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.080442                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -237,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide        41725                       #
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7641897806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7641897806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7662570804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7662570804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7662570804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7662570804                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7639838806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7639838806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7660511804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7660511804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7660511804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7660511804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -261,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183911.672266                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183644.596860                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183644.596860                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7656000                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183862.119898                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183595.249946                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183595.249946                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7420000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7143                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7102                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1071.818564                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1044.776119                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -287,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41725
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5481043992                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5481043992                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5492719992                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5492719992                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5492719992                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5492719992                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5478984000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5478984000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5490660000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5490660000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5490660000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5490660000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -303,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131640.982433                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131640.982433                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131591.611744                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131591.611744                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -326,22 +338,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9972402                       # DTB read hits
-system.cpu.dtb.read_misses                      43929                       # DTB read misses
-system.cpu.dtb.read_acv                           494                       # DTB read access violations
-system.cpu.dtb.read_accesses                   957886                       # DTB read accesses
-system.cpu.dtb.write_hits                     6649938                       # DTB write hits
-system.cpu.dtb.write_misses                     10071                       # DTB write misses
-system.cpu.dtb.write_acv                          391                       # DTB write access violations
-system.cpu.dtb.write_accesses                  340693                       # DTB write accesses
-system.cpu.dtb.data_hits                     16622340                       # DTB hits
-system.cpu.dtb.data_misses                      54000                       # DTB misses
-system.cpu.dtb.data_acv                           885                       # DTB access violations
-system.cpu.dtb.data_accesses                  1298579                       # DTB accesses
-system.cpu.itb.fetch_hits                     1343669                       # ITB hits
-system.cpu.itb.fetch_misses                     37345                       # ITB misses
-system.cpu.itb.fetch_acv                         1146                       # ITB acv
-system.cpu.itb.fetch_accesses                 1381014                       # ITB accesses
+system.cpu.dtb.read_hits                      9968108                       # DTB read hits
+system.cpu.dtb.read_misses                      43556                       # DTB read misses
+system.cpu.dtb.read_acv                           496                       # DTB read access violations
+system.cpu.dtb.read_accesses                   957960                       # DTB read accesses
+system.cpu.dtb.write_hits                     6640476                       # DTB write hits
+system.cpu.dtb.write_misses                     10042                       # DTB write misses
+system.cpu.dtb.write_acv                          402                       # DTB write access violations
+system.cpu.dtb.write_accesses                  340316                       # DTB write accesses
+system.cpu.dtb.data_hits                     16608584                       # DTB hits
+system.cpu.dtb.data_misses                      53598                       # DTB misses
+system.cpu.dtb.data_acv                           898                       # DTB access violations
+system.cpu.dtb.data_accesses                  1298276                       # DTB accesses
+system.cpu.itb.fetch_hits                     1341124                       # ITB hits
+system.cpu.itb.fetch_misses                     40235                       # ITB misses
+system.cpu.itb.fetch_acv                         1160                       # ITB acv
+system.cpu.itb.fetch_accesses                 1381359                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -354,143 +366,143 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        122571263                       # number of cpu cycles simulated
+system.cpu.numCycles                        122531860                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14075987                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11741614                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             452517                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10126525                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  5926302                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14045558                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11719354                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             447776                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10129156                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  5920510                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   942334                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               45003                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           31564050                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       71567580                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14075987                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6868636                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13486844                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2151091                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               41804632                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                33708                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        276041                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       314295                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          187                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8859322                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                305645                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           88896899                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.805063                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.137281                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                   939631                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               44501                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           31544288                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       71453130                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14045558                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6860141                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      13465921                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2135846                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               41803348                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                34171                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        276891                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       309124                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8845261                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                302298                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           88840406                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.804286                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.136255                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 75410055     84.83%     84.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   885656      1.00%     85.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1762066      1.98%     87.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   856601      0.96%     88.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2772547      3.12%     91.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   605003      0.68%     92.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   676052      0.76%     93.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1014878      1.14%     94.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4914041      5.53%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 75374485     84.84%     84.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   882693      0.99%     85.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1758870      1.98%     87.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   855110      0.96%     88.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2773745      3.12%     91.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   603499      0.68%     92.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   673337      0.76%     93.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1014466      1.14%     94.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4904201      5.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             88896899                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.114839                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.583885                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32604567                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              41610698                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12250426                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1057078                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1374129                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               617310                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 43428                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               70293890                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                133239                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1374129                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33752767                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                16324711                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       21058224                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11548980                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4838086                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               66572257                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  7187                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 753146                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1801877                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            44498273                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              80714962                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         80226097                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            488865                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38261328                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  6236937                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1703640                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         251709                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12757763                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10570492                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6981683                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1316603                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           922104                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58981346                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2097651                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57326676                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            120953                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7579711                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3887654                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1429592                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      88896899                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.644867                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.291957                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             88840406                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.114628                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.583139                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32595578                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              41593167                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  12233698                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1054489                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1363473                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               614789                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 43441                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               70185288                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                133206                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1363473                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33740803                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                16340010                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       21029757                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11532133                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4834228                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               66486071                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7165                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 750706                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1800875                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            44431145                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              80611615                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         80123142                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            488473                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38259358                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  6171779                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1702958                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         251555                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12743501                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10564267                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6974375                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1310956                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           921637                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58920823                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2093860                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57272597                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            128544                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7527772                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3875760                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1425872                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      88840406                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.644668                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.291770                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            62967728     70.83%     70.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            12048856     13.55%     84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5390899      6.06%     90.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3449544      3.88%     94.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2613461      2.94%     97.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1329807      1.50%     98.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              686975      0.77%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              354371      0.40%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               55258      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            62934632     70.84%     70.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            12040664     13.55%     84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5383860      6.06%     90.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3443587      3.88%     94.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2613267      2.94%     97.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1328836      1.50%     98.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              686879      0.77%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              354518      0.40%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               54163      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        88896899                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        88840406                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   75491     10.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 363771     48.19%     58.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                315594     41.81%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   73519      9.73%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 364094     48.19%     57.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                318003     42.09%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7291      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39127581     68.25%     68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61956      0.11%     68.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39090989     68.25%     68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61973      0.11%     68.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.42% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.42% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.42% # Type of FU issued
@@ -517,116 +529,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.43% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.43% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10418296     18.17%     86.60% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6729507     11.74%     98.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             952802      1.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10411715     18.18%     86.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6718707     11.73%     98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             952679      1.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57326676                       # Type of FU issued
-system.cpu.iq.rate                           0.467701                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      754856                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013168                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          203729346                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          68333375                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     56036726                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              696713                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             339202                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327718                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57709702                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  364539                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           594776                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57272597                       # Type of FU issued
+system.cpu.iq.rate                           0.467410                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      755616                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013193                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          203573547                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          68217667                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55990659                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              696212                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             338599                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       327577                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               57656594                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  364328                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           594908                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1456655                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2870                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14252                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       588832                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1450991                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2769                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14176                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       581838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18348                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        104302                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18337                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        105015                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1374129                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11393417                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                869281                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64652535                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            684492                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10570492                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6981683                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1845589                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 621506                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12714                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14252                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         241539                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       423865                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               665404                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56791406                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10044983                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            535269                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1363473                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                11404151                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                871964                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64586243                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            684405                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10564267                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6974375                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1841535                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 624319                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12765                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14176                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         237440                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       422569                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               660009                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56745623                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10040371                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            526973                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3573538                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16720258                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  9005988                       # Number of branches executed
-system.cpu.iew.exec_stores                    6675275                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.463334                       # Inst execution rate
-system.cpu.iew.wb_sent                       56476627                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56364444                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  27797872                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  37663953                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3571560                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16706164                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8999941                       # Number of branches executed
+system.cpu.iew.exec_stores                    6665793                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.463109                       # Inst execution rate
+system.cpu.iew.wb_sent                       56430087                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56318236                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  27772479                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37631426                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.459850                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.738050                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.459621                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.738013                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       56288834                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         56288834                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts         8251602                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          668059                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            621198                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     87522770                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.643134                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.558246                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       56285915                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         56285915                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         8189376                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          667988                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            616441                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     87476933                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.643437                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.558745                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     66254825     75.70%     75.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8962066     10.24%     85.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4828588      5.52%     91.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2603942      2.98%     94.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1449491      1.66%     96.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       603705      0.69%     96.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       515511      0.59%     97.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       488925      0.56%     97.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1815717      2.07%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     66214375     75.69%     75.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8956758     10.24%     85.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4831410      5.52%     91.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2600718      2.97%     94.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1447358      1.65%     96.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       605400      0.69%     96.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       515608      0.59%     97.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       488345      0.56%     97.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1816961      2.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     87522770                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56288834                       # Number of instructions committed
-system.cpu.commit.committedOps               56288834                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     87476933                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56285915                       # Number of instructions committed
+system.cpu.commit.committedOps               56285915                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15506688                       # Number of memory references committed
-system.cpu.commit.loads                       9113837                       # Number of loads committed
-system.cpu.commit.membars                      227975                       # Number of memory barriers committed
-system.cpu.commit.branches                    8463674                       # Number of branches committed
+system.cpu.commit.refs                       15505813                       # Number of memory references committed
+system.cpu.commit.loads                       9113276                       # Number of loads committed
+system.cpu.commit.membars                      227944                       # Number of memory barriers committed
+system.cpu.commit.branches                    8463135                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52126817                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               744625                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1815717                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  52124087                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               744545                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1816961                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    149996318                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130455868                       # The number of ROB writes
-system.cpu.timesIdled                         1387986                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        33674364                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3608226532                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    53094243                       # Number of Instructions Simulated
-system.cpu.committedOps                      53094243                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              53094243                       # Number of Instructions Simulated
-system.cpu.cpi                               2.308560                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.308560                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.433170                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.433170                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74446052                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40661007                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166346                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   166939                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1998850                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 950370                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    149884134                       # The number of ROB reads
+system.cpu.rob.rob_writes                   130314855                       # The number of ROB writes
+system.cpu.timesIdled                         1389359                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        33691454                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3606309626                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    53091408                       # Number of Instructions Simulated
+system.cpu.committedOps                      53091408                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              53091408                       # Number of Instructions Simulated
+system.cpu.cpi                               2.307941                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.307941                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.433287                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.433287                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74386687                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40627933                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166209                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   166935                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1998011                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 950291                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -658,247 +670,245 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                1025209                       # number of replacements
-system.cpu.icache.tagsinuse                509.960172                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7772148                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1025718                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.577276                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                1024388                       # number of replacements
+system.cpu.icache.tagsinuse                509.959478                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7759501                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1024896                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.571013                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            23722278000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     509.960172                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996016                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996016                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      7772149                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7772149                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7772149                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7772149                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7772149                       # number of overall hits
-system.cpu.icache.overall_hits::total         7772149                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1087170                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1087170                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1087170                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1087170                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1087170                       # number of overall misses
-system.cpu.icache.overall_misses::total       1087170                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  17528418489                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  17528418489                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  17528418489                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  17528418489                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  17528418489                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  17528418489                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8859319                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8859319                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8859319                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8859319                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8859319                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8859319                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122715                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.122715                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.122715                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.122715                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.122715                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.122715                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16122.978457                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16122.978457                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      1581994                       # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst     509.959478                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996015                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996015                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      7759502                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7759502                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7759502                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7759502                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7759502                       # number of overall hits
+system.cpu.icache.overall_hits::total         7759502                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1085755                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1085755                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1085755                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1085755                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1085755                       # number of overall misses
+system.cpu.icache.overall_misses::total       1085755                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  17501015990                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  17501015990                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  17501015990                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  17501015990                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  17501015990                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  17501015990                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8845257                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8845257                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8845257                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8845257                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8845257                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8845257                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122750                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.122750                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.122750                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.122750                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.122750                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.122750                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16118.752380                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16118.752380                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16118.752380                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16118.752380                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16118.752380                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16118.752380                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      1777494                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               196                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               208                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  8071.397959                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8545.644231                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          238                       # number of writebacks
-system.cpu.icache.writebacks::total               238                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        61204                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        61204                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        61204                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        61204                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        61204                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        61204                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1025966                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1025966                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1025966                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1025966                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1025966                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1025966                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13510508994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13510508994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13510508994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13510508994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13510508994                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13510508994                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115806                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.115806                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.115806                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60612                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        60612                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        60612                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        60612                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        60612                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        60612                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1025143                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1025143                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1025143                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1025143                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1025143                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1025143                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13492714994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13492714994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13492714994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13492714994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13492714994                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13492714994                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115897                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115897                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115897                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13161.788154                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13161.788154                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13161.788154                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1403926                       # number of replacements
-system.cpu.dcache.tagsinuse                511.995922                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 11884045                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1404438                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   8.461780                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1403592                       # number of replacements
+system.cpu.dcache.tagsinuse                511.995920                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 11877954                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1404104                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   8.459455                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               19693000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.995922                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.995920                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999992                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7283526                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7283526                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4189382                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4189382                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       190687                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       190687                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       220149                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       220149                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11472908                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11472908                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11472908                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11472908                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1829585                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1829585                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1968134                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1968134                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23417                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23417                       # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_hits::cpu.data      7277634                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7277634                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4189219                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4189219                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       190679                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       190679                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       220144                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       220144                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11466853                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11466853                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11466853                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11466853                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1830581                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1830581                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1967996                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1967996                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23423                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23423                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3797719                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3797719                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3797719                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3797719                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  48849966500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  48849966500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  74989002011                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  74989002011                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    432032000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    432032000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        56500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        56500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123838968511                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123838968511                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123838968511                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123838968511                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9113111                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9113111                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157516                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157516                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       214104                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       214104                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       220153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       220153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15270627                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15270627                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15270627                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15270627                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200764                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.200764                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319631                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.319631                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109372                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      3798577                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3798577                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3798577                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3798577                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  48883672000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  48883672000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  74930562797                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  74930562797                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    428682000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    428682000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        98000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        98000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123814234797                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123814234797                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123814234797                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123814234797                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9108215                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9108215                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157215                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157215                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       214102                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       214102                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       220148                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       220148                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15265430                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15265430                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15265430                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15265430                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200981                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.200981                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319624                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.319624                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109401                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109401                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000018                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000018                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.248694                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.248694                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.248694                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.248694                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        14125                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        14125                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32608.776087                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32608.776087                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    732928021                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.248835                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.248835                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.248835                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.248835                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26703.910944                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26703.910944                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38074.550353                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38074.550353                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18301.754686                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18301.754686                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        24500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        24500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32594.899300                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32594.899300                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32594.899300                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32594.899300                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    731758024                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             72145                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             72544                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842954                       # number of writebacks
-system.cpu.dcache.writebacks::total            842954                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       743747                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       743747                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667534                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1667534                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5230                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5230                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2411281                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2411281                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2411281                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2411281                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1085838                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1085838                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300600                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300600                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18187                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        18187                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       842689                       # number of writebacks
+system.cpu.dcache.writebacks::total            842689                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       745053                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       745053                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667452                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1667452                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5206                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5206                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2412505                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2412505                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2412505                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2412505                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1085528                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1085528                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300544                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300544                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18217                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18217                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1386438                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1386438                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1386438                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1386438                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28239740000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  28239740000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9650792448                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9650792448                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    273508500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    273508500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        44000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        44000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37890532448                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37890532448                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37890532448                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37890532448                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    905949500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    905949500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1225663998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1225663998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2131613498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   2131613498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119151                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119151                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048818                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048818                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084945                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084945                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1386072                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1386072                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1386072                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1386072                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28234901500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28234901500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9648960448                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9648960448                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    269943500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    269943500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        85500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        85500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37883861948                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37883861948                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37883861948                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37883861948                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    904971500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    904971500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1224983998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1224983998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2129955498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   2129955498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119181                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119181                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048812                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048812                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085086                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085086                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000018                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000018                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090791                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090791                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090791                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090798                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090798                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090798                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090798                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        21375                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        21375                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -907,28 +917,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6433                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211694                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74899     40.95%     40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     247      0.14%     41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1887      1.03%     42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105884     57.89%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182917                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73532     49.28%     49.28% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      247      0.17%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1887      1.26%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73537     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149203                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1825754390000     97.87%     97.87% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                99081000      0.01%     97.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               381309500      0.02%     97.90% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             39166410000      2.10%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1865401190500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6430                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211669                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74897     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     243      0.13%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1886      1.03%     42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105867     57.88%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182893                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73530     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      243      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1886      1.26%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73533     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149192                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1824783514500     97.87%     97.87% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                98568000      0.01%     97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               384878500      0.02%     97.90% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             39156084500      2.10%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1864423045500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694505                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815687                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694579                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815734                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -967,29 +977,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175564     91.19%     93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6792      3.53%     96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175546     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6791      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.92% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5223      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5220      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192535                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5955                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192513                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5956                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2110                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2106                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1906                      
 system.cpu.kern.mode_good::user                  1736                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.320067                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320013                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080569                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.388940                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29632954500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2782152500      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1832986075500     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080722                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.389059                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29626491000      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2782272500      0.15%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832014274000     98.26%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 7eac6f043..35fda0d55 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -168,7 +168,7 @@ type=O3Checker
 children=dtb itb tracer
 checker=Null
 clock=1
-cpu_id=-1
+cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
@@ -640,7 +640,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 3620c0fb4..8990e0cd7 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -4,31 +4,8 @@ warn: Sockets disabled, not accepting gdb connections
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr dccimvac' unimplemented
-warn: 	instruction 'mcr dccmvau' unimplemented
-warn: 	instruction 'mcr icimvau' unimplemented
-warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
-warn: LCD dual screen mode not supported
-warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: 	instruction 'mcr icialluis' unimplemented
-warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
-hack: be nice to actually delete the event here
+panic: Not supported on checker!
+ @ cycle 197694500
+[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130]
+Memory Usage: 355632 KBytes
+Program aborted at cycle 197694500
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index f106f905a..8772dfecb 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -1,12 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 17:05:39
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 02:25:32
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2502549875500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 4976e4992..e69de29bb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,978 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.502550                       # Number of seconds simulated
-sim_ticks                                2502549875500                       # Number of ticks simulated
-final_tick                               2502549875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75474                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97450                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3170228022                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386888                       # Number of bytes of host memory used
-host_seconds                                   789.39                       # Real time elapsed on the host
-sim_insts                                    59578267                       # Number of instructions simulated
-sim_ops                                      76925839                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    118994504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            800128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094928                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            128893400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       800128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          800128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3786176                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6802248                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14874313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12502                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142142                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15029017                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59159                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813177                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47549304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3634264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51504828                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319725                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319725                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1512927                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1205200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2718127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1512927                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47549304                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4839464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54222954                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64431                       # number of replacements
-system.l2c.tagsinuse                     51237.782352                       # Cycle average of tags in use
-system.l2c.total_refs                         2028510                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.624716                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2492014554000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36760.884600                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       47.476285                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8187.042847                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6242.378435                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.560927                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000724                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124924                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095251                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781827                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        121963                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11826                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              977935                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              383708                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1495432                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          675442                       # number of Writeback hits
-system.l2c.Writeback_hits::total               675442                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               42                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  42                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112737                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112737                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         121963                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11826                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               977935                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               496445                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1608169                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        121963                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11826                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              977935                       # number of overall hits
-system.l2c.overall_hits::cpu.data              496445                       # number of overall hits
-system.l2c.overall_hits::total                1608169                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12384                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23135                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133229                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133229                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12384                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143920                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156364                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           59                       # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12384                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143920                       # number of overall misses
-system.l2c.overall_misses::total               156364                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3091500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    659591498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    562236498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1224979496                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       944500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       944500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   7069904999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7069904999                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      3091500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    659591498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7632141497                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8294884495                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      3091500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    659591498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7632141497                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8294884495                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       122022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11827                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          990319                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          394399                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1518567                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       675442                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           675442                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2951                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2951                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        245966                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           245966                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       122022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11827                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           990319                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           640365                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1764533                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       122022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11827                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          990319                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          640365                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1764533                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000085                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012505                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.027107                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015235                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.985768                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.985768                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541656                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541656                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000085                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012505                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.224747                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088615                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000085                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012505                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.224747                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088615                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52949.189367                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   324.682021                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   324.682021                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53065.811490                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53048.556541                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53048.556541                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59159                       # number of writebacks
-system.l2c.writebacks::total                    59159                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12375                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10629                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23064                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133229                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133229                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12375                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143858                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156293                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12375                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143858                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156293                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    508160500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    430170499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    940750999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116825000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    116825000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5436034999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5436034999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    508160500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5866205498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6376785998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    508160500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5866205498                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6376785998                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31373446015                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31373446015                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162795884015                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026950                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015188                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985768                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.985768                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541656                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541656                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088575                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088575                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
-system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             15048164                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7309                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11293826                       # DTB write hits
-system.cpu.checker.dtb.write_misses              2190                       # DTB write misses
-system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
-system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
-system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults            177                       # Number of TLB faults due to prefetch
-system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         15055473                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11296016                       # DTB write accesses
-system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26341990                       # DTB hits
-system.cpu.checker.dtb.misses                    9499                       # DTB misses
-system.cpu.checker.dtb.accesses              26351489                       # DTB accesses
-system.cpu.checker.itb.inst_hits             60744881                       # ITB inst hits
-system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
-system.cpu.checker.itb.read_hits                    0                       # DTB read hits
-system.cpu.checker.itb.read_misses                  0                       # DTB read misses
-system.cpu.checker.itb.write_hits                   0                       # DTB write hits
-system.cpu.checker.itb.write_misses                 0                       # DTB write misses
-system.cpu.checker.itb.flush_tlb                    4                       # Number of times complete TLB was flushed
-system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
-system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
-system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
-system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         60749352                       # ITB inst accesses
-system.cpu.checker.itb.hits                  60744881                       # DTB hits
-system.cpu.checker.itb.misses                    4471                       # DTB misses
-system.cpu.checker.itb.accesses              60749352                       # DTB accesses
-system.cpu.checker.numCycles                 77204260                       # number of cpu cycles simulated
-system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
-system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51771660                       # DTB read hits
-system.cpu.dtb.read_misses                      81258                       # DTB read misses
-system.cpu.dtb.write_hits                    11880398                       # DTB write hits
-system.cpu.dtb.write_misses                     17961                       # DTB write misses
-system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     8043                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      3044                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    609                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1282                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51852918                       # DTB read accesses
-system.cpu.dtb.write_accesses                11898359                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63652058                       # DTB hits
-system.cpu.dtb.misses                           99219                       # DTB misses
-system.cpu.dtb.accesses                      63751277                       # DTB accesses
-system.cpu.itb.inst_hits                     13142261                       # ITB inst hits
-system.cpu.itb.inst_misses                      12247                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            4                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     5262                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13154508                       # ITB inst accesses
-system.cpu.itb.hits                          13142261                       # DTB hits
-system.cpu.itb.misses                           12247                       # DTB misses
-system.cpu.itb.accesses                      13154508                       # DTB accesses
-system.cpu.numCycles                        413642740                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14974990                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11915620                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             753400                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10068197                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7820088                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1448775                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80927                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           33422471                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       99542070                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14974990                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9268863                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21759182                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6002262                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     163536                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               93319816                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2533                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        133610                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208459                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          397                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13138017                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1024097                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6504                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          153128307                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.804842                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.182667                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                131386008     85.80%     85.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1369017      0.89%     86.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1759019      1.15%     87.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2640315      1.72%     89.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1819667      1.19%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1142419      0.75%     91.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2920911      1.91%     93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   807762      0.53%     93.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9283189      6.06%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            153128307                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.036203                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.240647                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 35537493                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              93048586                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19509299                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1086349                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3946580                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2100058                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174557                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              116122172                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                568338                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3946580                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37621271                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39594801                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       46881047                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18412397                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6672211                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              108597287                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  4175                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1156489                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4484156                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            30967                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           113073752                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             499820515                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        499727174                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             93341                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              77686691                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 35387060                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             898607                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         797702                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13307124                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             21058263                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13875749                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1965166                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2564814                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   99781831                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1555350                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 124613166                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            199798                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23638127                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65777806                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         268083                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     153128307                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.813783                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.516400                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           107849903     70.43%     70.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14560254      9.51%     79.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7302452      4.77%     84.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5913038      3.86%     88.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12593494      8.22%     96.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2809204      1.83%     98.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1536315      1.00%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              438168      0.29%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              125479      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       153128307                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   53462      0.61%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8367005     94.75%     95.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                409700      4.64%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            106530      0.09%      0.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58482659     46.93%     47.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95330      0.08%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  11      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53414157     42.86%     89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12512351     10.04%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              124613166                       # Type of FU issued
-system.cpu.iq.rate                           0.301258                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8830169                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.070861                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          411460543                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         124996425                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85630389                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               22925                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12868                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10343                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              133324707                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12098                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           646336                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5343093                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11106                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        35068                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2077574                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107202                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1049886                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3946580                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                29463666                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                540836                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           101593235                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              21058263                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13875749                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             964547                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 125689                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 40656                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          35068                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         381127                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       332167                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               713294                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             121438397                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52461807                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3174769                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        256054                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64853171                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11412736                       # Number of branches executed
-system.cpu.iew.exec_stores                   12391364                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.293583                       # Inst execution rate
-system.cpu.iew.wb_sent                      120063166                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85640732                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  46459932                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  84649521                       # num instructions consuming a value
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.207040                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.548851                       # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       59728648                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         77076220                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24329020                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1287267                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            625309                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    149264139                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.516375                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.492760                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    121340444     81.29%     81.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13976446      9.36%     90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3929866      2.63%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2230737      1.49%     94.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1774137      1.19%     95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1064202      0.71%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1398926      0.94%     97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       658331      0.44%     98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2891050      1.94%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    149264139                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             59728648                       # Number of instructions committed
-system.cpu.commit.committedOps               77076220                       # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513345                       # Number of memory references committed
-system.cpu.commit.loads                      15715170                       # Number of loads committed
-system.cpu.commit.membars                      413057                       # Number of memory barriers committed
-system.cpu.commit.branches                    9904308                       # Number of branches committed
-system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  68616986                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995953                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2891050                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    246021016                       # The number of ROB reads
-system.cpu.rob.rob_writes                   206855771                       # The number of ROB writes
-system.cpu.timesIdled                         1910853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       260514433                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4591368963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    59578267                       # Number of Instructions Simulated
-system.cpu.committedOps                      76925839                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              59578267                       # Number of Instructions Simulated
-system.cpu.cpi                               6.942846                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.942846                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.144033                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.144033                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                551124725                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87730819                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8186                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2858                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               131789755                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912697                       # number of misc regfile writes
-system.cpu.icache.replacements                 991190                       # number of replacements
-system.cpu.icache.tagsinuse                511.611770                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12061455                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 991702                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.162378                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6426198000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.611770                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999242                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999242                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12061455                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12061455                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12061455                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12061455                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12061455                       # number of overall hits
-system.cpu.icache.overall_hits::total        12061455                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1076423                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1076423                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1076423                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1076423                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1076423                       # number of overall misses
-system.cpu.icache.overall_misses::total       1076423                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16851120991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16851120991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16851120991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16851120991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16851120991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16851120991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13137878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13137878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13137878                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13137878                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13137878                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13137878                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081933                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.081933                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.081933                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.081933                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.081933                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.081933                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15654.738881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15654.738881                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2871493                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               461                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  6228.835141                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        67899                       # number of writebacks
-system.cpu.icache.writebacks::total             67899                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84680                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84680                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84680                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84680                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84680                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84680                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991743                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       991743                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       991743                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       991743                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       991743                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       991743                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12825867499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12825867499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12825867499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12825867499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12825867499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12825867499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.075487                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.075487                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 643139                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991335                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21733833                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 643651                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.766487                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991335                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13904166                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13904166                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7257095                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7257095                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       283844                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       283844                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285639                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285639                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21161261                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21161261                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21161261                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21161261                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       765252                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        765252                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2993311                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2993311                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13765                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13765                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3758563                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3758563                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3758563                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3758563                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14844603000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14844603000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 129412035593                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223977000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    223977000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       405000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       405000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 144256638593                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 144256638593                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 144256638593                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 144256638593                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14669418                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14669418                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       297609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285658                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285658                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24919824                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24919824                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24919824                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24919824                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052166                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052166                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292019                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.292019                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046252                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046252                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000067                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000067                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150826                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150826                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150826                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150826                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38380.795691                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38380.795691                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32633902                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7260500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7285                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             283                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4479.602196                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607543                       # number of writebacks
-system.cpu.dcache.writebacks::total            607543                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379767                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       379767                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744505                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2744505                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3124272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3124272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3124272                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3124272                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385485                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385485                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248806                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248806                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12312                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12312                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634291                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634291                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634291                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634291                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6242554097                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6242554097                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9246380950                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9246380950                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    164108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    164108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       341500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       341500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15488935047                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15488935047                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15488935047                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15488935047                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41215087708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41215087708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024273                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024273                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041370                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041370                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000067                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000067                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025453                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025453                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.iocache.replacements                         0                       # number of replacements
-system.iocache.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1298563544001                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88049                       # number of quiesce instructions executed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 8ee00f929..7a79f323f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -1023,7 +1023,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index 6f1b9eba3..523f8a126 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -10,10 +10,10 @@ warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: LCD dual screen mode not supported
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index fe27005da..904402304 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 17:16:08
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 02:25:35
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2581527583500 because m5_exit instruction encountered
+Exiting @ tick 2582310281500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index ba015b214..977ccc85a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,16 +1,71 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.581528                       # Number of seconds simulated
-sim_ticks                                2581527583500                       # Number of ticks simulated
-final_tick                               2581527583500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.582310                       # Number of seconds simulated
+sim_ticks                                2582310281500                       # Number of ticks simulated
+final_tick                               2582310281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  89313                       # Simulator instruction rate (inst/s)
-host_op_rate                                   115365                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3717496726                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390980                       # Number of bytes of host memory used
-host_seconds                                   694.43                       # Real time elapsed on the host
-sim_insts                                    62021206                       # Number of instructions simulated
-sim_ops                                      80112751                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  62666                       # Simulator instruction rate (inst/s)
+host_op_rate                                    80652                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2566586582                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 395816                       # Number of bytes of host memory used
+host_seconds                                  1006.13                       # Real time elapsed on the host
+sim_insts                                    63050246                       # Number of instructions simulated
+sim_ops                                      81146063                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           396544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4372212                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           425600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5220016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129953444                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       396544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       425600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          822144                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4241024                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7270160                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6196                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             68388                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6650                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             81589                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15105053                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66266                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               823550                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46290976                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           223                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              153562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1693140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              164814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2021452                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50324488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         153562                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         164814                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             318375                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1642337                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            1166450                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2815370                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1642337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46290976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          223                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             153562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1699723                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             164814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3187902                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53139859                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          320                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           384                       # Number of bytes read from this memory
@@ -29,292 +84,237 @@ system.realview.nvmem.bw_inst_read::total          149                       # I
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          124                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             149                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           395008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4372084                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         1344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           425536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5226480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129958756                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       395008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       425536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          820544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4244480                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7273616                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6172                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             68386                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           21                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6649                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             81690                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15105136                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66320                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823604                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46305011                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           223                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              153013                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1693603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              164839                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2024569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50341804                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         153013                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         164839                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317852                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1644174                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6585                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1166804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2817563                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1644174                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46305011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          223                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             153013                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1700189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             164839                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3191372                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53159367                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         72536                       # number of replacements
-system.l2c.tagsinuse                     53024.626088                       # Cycle average of tags in use
-system.l2c.total_refs                         2019266                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        137732                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         14.660834                       # Average number of references to valid blocks.
+system.l2c.replacements                         72453                       # number of replacements
+system.l2c.tagsinuse                     52989.750711                       # Cycle average of tags in use
+system.l2c.total_refs                         1967154                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        137652                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         14.290777                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        37701.415204                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker       3.259804                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.000179                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          4215.968317                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          2959.624437                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker      13.637835                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          4028.150256                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          4102.570055                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.575278                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker      0.000050                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        37689.434458                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       3.667894                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.004429                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4220.453796                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2953.326384                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       6.708393                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          4009.126872                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          4107.028485                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.575095                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000056                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.064331                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.045160                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker      0.000208                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.061465                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.062600                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.809092                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker        53338                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6106                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             398719                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             164464                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        78886                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6452                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             615129                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             199702                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1522796                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          645710                       # number of Writeback hits
-system.l2c.Writeback_hits::total               645710                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1043                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             806                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1849                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           213                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           143                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               356                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            48030                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            59189                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107219                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         53338                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6106                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              398719                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              212494                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         78886                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6452                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              615129                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              258891                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1630015                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        53338                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6106                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             398719                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             212494                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        78886                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6452                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             615129                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             258891                       # number of overall hits
-system.l2c.overall_hits::total                1630015                       # number of overall hits
+system.l2c.occ_percent::cpu0.inst            0.064399                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.045064                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000102                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.061174                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.062668                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.808559                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        54491                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6158                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             400629                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             165440                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        78380                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6682                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             615050                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             201442                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1528272                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          583270                       # number of Writeback hits
+system.l2c.Writeback_hits::total               583270                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1037                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             784                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1821                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           208                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           159                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               367                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            48010                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            59262                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               107272                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         54491                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6158                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              400629                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              213450                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         78380                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          6682                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              615050                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              260704                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1635544                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        54491                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6158                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             400629                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             213450                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        78380                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         6682                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             615050                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             260704                       # number of overall hits
+system.l2c.overall_hits::total                1635544                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            9                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6044                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6302                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           21                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6609                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             6068                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6301                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           11                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6610                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data             6328                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                25314                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5683                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4287                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9970                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          777                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          589                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1366                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63451                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          76572                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140023                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::total                25329                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          5681                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4309                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              9990                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          780                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          578                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1358                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63459                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          76486                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139945                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            9                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6044                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             69753                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           21                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6609                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             82900                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                165337                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              6068                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             69760                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           11                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6610                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             82814                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                165274                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            9                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6044                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            69753                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           21                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6609                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            82900                       # number of overall misses
-system.l2c.overall_misses::total               165337                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       471000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker        60000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    322261499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    330895497                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1101000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    351559997                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    332583499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1338932492                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     20202500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     27410499                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     47612999                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1721500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7138500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      8860000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3379920986                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4071556980                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7451477966                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       471000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker        60000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    322261499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3710816483                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      1101000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    351559997                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4404140479                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8790410458                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       471000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker        60000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    322261499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3710816483                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      1101000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    351559997                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4404140479                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8790410458                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        53347                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6107                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         404763                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         170766                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        78907                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6452                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         621738                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         206030                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1548110                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       645710                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           645710                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6726                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             6068                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            69760                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           11                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6610                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            82814                       # number of overall misses
+system.l2c.overall_misses::total               165274                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       470500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       112500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    323600498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    331027497                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       573500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    351706500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    332606499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1340097494                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     20411497                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27614499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     48025996                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1617000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6615500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      8232500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3380389982                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4066537489                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7446927471                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker       470500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       112500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    323600498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3711417479                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       573500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    351706500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4399143988                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8787024965                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker       470500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       112500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    323600498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3711417479                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       573500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    351706500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4399143988                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8787024965                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        54500                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         6160                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         406697                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         171741                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        78391                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         6682                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         621660                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         207770                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1553601                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       583270                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           583270                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6718                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         5093                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           11819                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          990                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          732                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1722                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       111481                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       135761                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247242                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        53347                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6107                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          404763                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          282247                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        78907                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6452                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          621738                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          341791                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1795352                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        53347                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6107                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         404763                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         282247                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        78907                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6452                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         621738                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         341791                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1795352                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014932                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036904                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010630                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030714                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016352                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844930                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.841744                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.843557                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784848                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.804645                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.793264                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.569164                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.564021                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.566340                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014932                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.247135                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010630                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.242546                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.092092                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014932                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.247135                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010630                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.242546                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.092092                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        60000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52892.964052                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3554.900581                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6393.864941                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4775.626780                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2215.572716                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6486.090776                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53216.099969                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        60000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53166.626091                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        60000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53166.626091                       # average overall miss latency
+system.l2c.UpgradeReq_accesses::total           11811                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          988                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          737                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1725                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111469                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       135748                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247217                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        54500                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6160                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          406697                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          283210                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        78391                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6682                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          621660                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          343518                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1800818                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        54500                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6160                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         406697                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         283210                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        78391                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6682                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         621660                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         343518                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1800818                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014920                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036689                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010633                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.030457                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016303                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.845639                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.846063                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.845822                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.789474                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.784261                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.787246                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.569297                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.563441                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.566082                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014920                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.246319                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010633                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.241076                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.091777                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014920                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.246319                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010633                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.241076                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.091777                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        56250                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53329.020765                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52535.708142                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53208.245083                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52561.077592                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52907.635280                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3592.940855                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6408.563240                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4807.407007                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2073.076923                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11445.501730                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6062.223859                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.881987                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53167.082721                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53213.244282                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        56250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53329.020765                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 53202.658816                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53208.245083                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 53120.776535                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53166.408298                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        56250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53329.020765                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 53202.658816                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53208.245083                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 53120.776535                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53166.408298                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -323,170 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               66320                       # number of writebacks
-system.l2c.writebacks::total                    66320                       # number of writebacks
+system.l2c.writebacks::writebacks               66266                       # number of writebacks
+system.l2c.writebacks::total                    66266                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.data            23                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                72                       # number of ReadReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0.data            1                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total               1                       # number of ReadExReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data             23                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 73                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data            23                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                73                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            9                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         6039                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         6063                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.data         6263                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           21                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6604                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           11                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6605                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data         6305                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           25242                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         5683                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4287                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         9970                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          777                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          589                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1366                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        63450                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        76572                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140022                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25258                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         5681                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4309                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         9990                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          780                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          578                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1358                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        63459                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        76486                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139945                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         6039                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        69713                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           21                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6604                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        82877                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           165264                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         6063                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        69722                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           11                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6605                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        82791                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           165203                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            9                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         6039                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        69713                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           21                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6604                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        82877                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          165264                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         6063                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        69722                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           11                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6605                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        82791                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          165203                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        48000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    248302999                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253032000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    270719997                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    254713500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1028022496                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    227576000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    171718000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    399294000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31112500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23586500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     54699000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2608560498                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3134816489                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5743376987                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        88000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    249380499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253173000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    270856500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    254736000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1029033999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    227403000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    172571500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    399974500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31217000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23131000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     54348000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2608915998                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3130662995                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5739578993                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    248302999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   2861592498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    270719997                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3389529989                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6771399483                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        88000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    249380499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2862088998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    270856500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3385398995                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6768612992                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        48000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    248302999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2861592498                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    270719997                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3389529989                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6771399483                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        88000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    249380499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2862088998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    270856500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3385398995                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6768612992                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9186859000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9186576500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    704572999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30781654107                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31486227106                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122396919500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131591208500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    704511999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30785024883                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31489536882                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9891431999                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9891088499                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163078505106                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036676                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030602                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016305                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.844930                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.841744                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.843557                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784848                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.804645                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.793264                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569155                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564021                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.566336                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.246993                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.242479                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.092051                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.246993                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.242479                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.092051                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153181944383                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163080745382                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036468                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030346                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016258                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.845639                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.846063                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.845822                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.789474                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784261                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.787246                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569297                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.563441                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.566082                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.246185                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.241009                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.091738                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.246185                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.241009                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.091738                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40973.227581                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40971.489573                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40973.227581                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40971.489573                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -509,27 +507,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9084255                       # DTB read hits
-system.cpu0.dtb.read_misses                     36769                       # DTB read misses
-system.cpu0.dtb.write_hits                    5284576                       # DTB write hits
-system.cpu0.dtb.write_misses                     6773                       # DTB write misses
+system.cpu0.dtb.read_hits                     9083896                       # DTB read hits
+system.cpu0.dtb.read_misses                     37543                       # DTB read misses
+system.cpu0.dtb.write_hits                    5286239                       # DTB write hits
+system.cpu0.dtb.write_misses                     6882                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2261                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1412                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   383                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    2244                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1393                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   382                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      588                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9121024                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5291349                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      574                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 9121439                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5293121                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14368831                       # DTB hits
-system.cpu0.dtb.misses                          43542                       # DTB misses
-system.cpu0.dtb.accesses                     14412373                       # DTB accesses
-system.cpu0.itb.inst_hits                     4421795                       # ITB inst hits
-system.cpu0.itb.inst_misses                      5958                       # ITB inst misses
+system.cpu0.dtb.hits                         14370135                       # DTB hits
+system.cpu0.dtb.misses                          44425                       # DTB misses
+system.cpu0.dtb.accesses                     14414560                       # DTB accesses
+system.cpu0.itb.inst_hits                     4418601                       # ITB inst hits
+system.cpu0.itb.inst_misses                      6114                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -538,542 +536,544 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1415                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1409                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1713                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1633                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4427753                       # ITB inst accesses
-system.cpu0.itb.hits                          4421795                       # DTB hits
-system.cpu0.itb.misses                           5958                       # DTB misses
-system.cpu0.itb.accesses                      4427753                       # DTB accesses
-system.cpu0.numCycles                        66112093                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 4424715                       # ITB inst accesses
+system.cpu0.itb.hits                          4418601                       # DTB hits
+system.cpu0.itb.misses                           6114                       # DTB misses
+system.cpu0.itb.accesses                      4424715                       # DTB accesses
+system.cpu0.numCycles                        66354055                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                 6172143                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           4680207                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            316413                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              3902841                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 2861272                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                 6346252                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           4857071                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            316053                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              4075974                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 3037671                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  700420                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              30889                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          12972431                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      32579396                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    6172143                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3561692                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      7636967                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1568394                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     92289                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              21876805                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                5742                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        73340                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles        91549                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          175                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4419869                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               175391                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2999                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          43870869                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.963501                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.353712                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  700378                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              30829                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          12963003                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      33274045                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    6346252                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           3738049                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                      7812188                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1602844                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     89446                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              22023764                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                5932                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        73578                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles        90886                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          179                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  4416774                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               175280                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3223                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          44209960                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.971808                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.352806                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                36242473     82.61%     82.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  623814      1.42%     84.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  820212      1.87%     85.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  686089      1.56%     87.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                  622737      1.42%     88.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  578948      1.32%     90.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  720296      1.64%     91.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  370745      0.85%     92.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3205555      7.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                36406101     82.35%     82.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  622907      1.41%     83.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  820090      1.85%     85.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  691511      1.56%     87.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                  794774      1.80%     88.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  578673      1.31%     90.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  721468      1.63%     91.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  370773      0.84%     92.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3203663      7.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            43870869                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.093359                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.492790                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                13461534                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             21912526                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  6836712                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               603785                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1056312                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              995110                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                66550                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              40827533                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               217718                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1056312                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                14066817                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6153021                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      13456769                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  6788701                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              2349249                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              39593607                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 1040                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                472233                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1335984                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             103                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           39791095                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            179675714                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       179640853                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            34861                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             31537071                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8254023                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            463697                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        419128                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  5673165                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7928571                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5881726                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1132931                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1238845                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  37538443                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded             794373                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 37739879                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            92690                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6264606                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     14354053                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        137507                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     43870869                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.860249                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.478315                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            44209960                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.095642                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.501462                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                13460475                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             22052761                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  7004876                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               606078                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1085770                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              992839                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                66349                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              41502146                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               217622                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1085770                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                14072541                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6178049                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      13569314                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6948288                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              2355998                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              40249124                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 2572                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                473537                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1335703                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             188                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           40597200                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            181819083                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       181783808                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            35275                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             31678350                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 8918849                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            463403                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        418800                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  5692374                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7927385                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5883720                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1132627                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1230816                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  38008933                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded             947103                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 38247071                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            93468                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6756686                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     14324325                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        258267                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     44209960                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.865123                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.479533                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           28164784     64.20%     64.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            6326126     14.42%     78.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3234526      7.37%     85.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2361316      5.38%     91.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2098246      4.78%     96.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5             936106      2.13%     98.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             514694      1.17%     99.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             181493      0.41%     99.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              53578      0.12%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           28324155     64.07%     64.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            6346765     14.36%     78.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3236431      7.32%     85.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2507997      5.67%     91.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2107881      4.77%     96.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5             937016      2.12%     98.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             515116      1.17%     99.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             180639      0.41%     99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              53960      0.12%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       43870869                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       44209960                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  27565      2.58%      2.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   466      0.04%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                837939     78.44%     81.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               202337     18.94%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  27715      2.59%      2.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   460      0.04%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                839091     78.45%     81.09% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               202283     18.91%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            20407      0.05%      0.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             22494595     59.60%     59.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               50051      0.13%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  8      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              5      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           684      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     59.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9563453     25.34%     85.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5610668     14.87%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            52344      0.14%      0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             22968400     60.05%     60.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               50115      0.13%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 14      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc             11      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           684      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9563149     25.00%     85.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5612341     14.67%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              37739879                       # Type of FU issued
-system.cpu0.iq.rate                          0.570847                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1068307                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.028307                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         120546534                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         44606042                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     34820056                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads               8333                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              4740                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         3893                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              38783456                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   4323                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          326383                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              38247071                       # Type of FU issued
+system.cpu0.iq.rate                          0.576409                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1069549                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.027964                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         121902835                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         45721169                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     35306324                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads               8427                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              4840                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         3930                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              39259896                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   4380                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          325721                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1507630                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4080                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13930                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       608245                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1504145                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3982                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13879                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       608088                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2149509                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5404                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2149487                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked         5263                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1056312                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                4064319                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               129740                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           38471177                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            88757                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7928571                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5881726                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            461616                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 49674                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                17745                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13930                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        159357                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       144737                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              304094                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             37337331                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9402148                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           402548                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1085770                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                4069341                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               129560                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           39094255                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            87678                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7927385                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5883720                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            614122                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 49261                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                17662                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13879                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        160370                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       144551                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              304921                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             37828601                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9401576                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           418470                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       138361                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14958639                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 4921687                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5556491                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.564758                       # Inst execution rate
-system.cpu0.iew.wb_sent                      37117116                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     34823949                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 18360594                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 34980725                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       138219                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14960222                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5069889                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5558646                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.570102                       # Inst execution rate
+system.cpu0.iew.wb_sent                      37608832                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     35310254                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 18670977                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 35573590                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.526741                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.524877                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.532149                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.524855                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      24134633                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        31866160                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        6466683                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         656866                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           267750                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     42850944                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.743651                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.697776                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      24262280                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        31997725                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        6679991                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         688836                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           267429                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     43160582                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.741365                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.695624                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     30739496     71.74%     71.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      6075340     14.18%     85.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1944692      4.54%     90.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1041937      2.43%     92.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       773699      1.81%     94.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       503770      1.18%     95.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       405337      0.95%     96.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       203427      0.47%     97.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1163246      2.71%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     31020137     71.87%     71.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6071618     14.07%     85.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1950463      4.52%     90.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1036843      2.40%     92.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       799662      1.85%     94.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       507487      1.18%     95.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       407135      0.94%     96.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       202137      0.47%     97.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1165100      2.70%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     42850944                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            24134633                       # Number of instructions committed
-system.cpu0.commit.committedOps              31866160                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     43160582                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            24262280                       # Number of instructions committed
+system.cpu0.commit.committedOps              31997725                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      11694422                       # Number of memory references committed
-system.cpu0.commit.loads                      6420941                       # Number of loads committed
-system.cpu0.commit.membars                     234529                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4382702                       # Number of branches committed
+system.cpu0.commit.refs                      11698872                       # Number of memory references committed
+system.cpu0.commit.loads                      6423240                       # Number of loads committed
+system.cpu0.commit.membars                     234547                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4415502                       # Number of branches committed
 system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 28193395                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              499856                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1163246                       # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts                 28265931                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              499946                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1165100                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                    79207972                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   77724528                       # The number of ROB writes
-system.cpu0.timesIdled                         427936                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       22241224                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5096899290                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   24053891                       # Number of Instructions Simulated
-system.cpu0.committedOps                     31785418                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             24053891                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.748499                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.748499                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.363835                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.363835                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               174526329                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               34331240                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     3280                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     898                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               46875879                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                527497                       # number of misc regfile writes
-system.cpu0.icache.replacements                406974                       # number of replacements
-system.cpu0.icache.tagsinuse               511.614338                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 3978434                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                407486                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  9.763364                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle            6469268000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   511.614338                       # Average occupied blocks per requestor
+system.cpu0.rob.rob_reads                    79788976                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   78443760                       # The number of ROB writes
+system.cpu0.timesIdled                         426851                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       22144095                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5098222727                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   24181538                       # Number of Instructions Simulated
+system.cpu0.committedOps                     31916983                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             24181538                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.743996                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.743996                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.364432                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.364432                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               176533858                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               35079827                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     3404                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     942                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads               47584444                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                527516                       # number of misc regfile writes
+system.cpu0.icache.replacements                406873                       # number of replacements
+system.cpu0.icache.tagsinuse               511.614484                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 3975135                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                407385                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  9.757686                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            6470209000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   511.614484                       # Average occupied blocks per requestor
 system.cpu0.icache.occ_percent::cpu0.inst     0.999247                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_percent::total        0.999247                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      3978434                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        3978434                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      3978434                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         3978434                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      3978434                       # number of overall hits
-system.cpu0.icache.overall_hits::total        3978434                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       441298                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       441298                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       441298                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        441298                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       441298                       # number of overall misses
-system.cpu0.icache.overall_misses::total       441298                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7186656997                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7186656997                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7186656997                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7186656997                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7186656997                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7186656997                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4419732                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4419732                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4419732                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4419732                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4419732                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4419732                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.099847                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.099847                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.099847                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.099847                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.099847                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.099847                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 16285.269811                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 16285.269811                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1454497                       # number of cycles access was blocked
+system.cpu0.icache.ReadReq_hits::cpu0.inst      3975135                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        3975135                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      3975135                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         3975135                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      3975135                       # number of overall hits
+system.cpu0.icache.overall_hits::total        3975135                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       441500                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       441500                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       441500                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        441500                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       441500                       # number of overall misses
+system.cpu0.icache.overall_misses::total       441500                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7129067996                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7129067996                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7129067996                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7129067996                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7129067996                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7129067996                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      4416635                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      4416635                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      4416635                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      4416635                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      4416635                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      4416635                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.099963                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.099963                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.099963                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.099963                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.099963                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.099963                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16147.379379                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16147.379379                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1348496                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              171                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs  8505.830409                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  8074.826347                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks        29234                       # number of writebacks
-system.cpu0.icache.writebacks::total            29234                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        33802                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        33802                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        33802                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        33802                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        33802                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        33802                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       407496                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       407496                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       407496                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       407496                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       407496                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       407496                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5527499503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5527499503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5527499503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5527499503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5527499503                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5527499503                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        34106                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        34106                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        34106                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        34106                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        34106                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        34106                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       407394                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       407394                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       407394                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       407394                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       407394                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       407394                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5468654996                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5468654996                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5468654996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5468654996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5468654996                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5468654996                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8379000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total      8379000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.092199                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.092199                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.092199                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.092241                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.092241                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.092241                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                275761                       # number of replacements
-system.cpu0.dcache.tagsinuse               476.305820                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 9551525                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                276273                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 34.572778                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                275592                       # number of replacements
+system.cpu0.dcache.tagsinuse               476.837382                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 9554493                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                276104                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 34.604689                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              51448000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   476.305820                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.930285                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.930285                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5934693                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5934693                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3224707                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3224707                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174478                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       174478                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171499                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       171499                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9159400                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9159400                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9159400                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9159400                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       401255                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       401255                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1594245                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1594245                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9007                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9007                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7794                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7794                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1995500                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1995500                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1995500                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1995500                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7289566500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   7289566500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71816395371                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  71816395371                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    114642500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    114642500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     93715000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     93715000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  79105961871                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  79105961871                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  79105961871                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  79105961871                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6335948                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6335948                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4818952                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4818952                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183485                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       183485                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179293                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       179293                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11154900                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11154900                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11154900                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11154900                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063330                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.063330                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330828                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.330828                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.049088                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.049088                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043471                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043471                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178890                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.178890                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178890                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.178890                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      7140493                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      1629000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs             1441                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             89                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  4955.234559                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787                       # average number of cycles each access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data   476.837382                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.931323                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.931323                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5935954                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5935954                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3226635                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3226635                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174405                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       174405                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171548                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       171548                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9162589                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9162589                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9162589                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9162589                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       400527                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       400527                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1594104                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1594104                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8985                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         8985                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7776                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7776                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1994631                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1994631                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1994631                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1994631                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7261400500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   7261400500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71837415855                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  71837415855                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    113971500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    113971500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     93410500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     93410500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  79098816355                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  79098816355                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  79098816355                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  79098816355                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6336481                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6336481                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4820739                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4820739                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183390                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       183390                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179324                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       179324                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11157220                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11157220                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11157220                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11157220                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063210                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.063210                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330676                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.330676                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048994                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048994                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043363                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043363                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178775                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.178775                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178775                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.178775                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      7527492                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      1548500                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             1462                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             87                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  5148.763338                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       255942                       # number of writebacks
-system.cpu0.dcache.writebacks::total           255942                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       211815                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       211815                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1463184                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1463184                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          509                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          509                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1674999                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1674999                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1674999                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1674999                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189440                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       189440                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131061                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       131061                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8498                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8498                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7791                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7791                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       320501                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       320501                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       320501                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       320501                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2806583905                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2806583905                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4685193022                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4685193022                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     80265007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     80265007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     69214057                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     69214057                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7491776927                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7491776927                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7491776927                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7491776927                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10315161000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10315161000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    849550399                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    849550399                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11164711399                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11164711399                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029899                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029899                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027197                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027197                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046314                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046314                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043454                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043454                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028732                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028732                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028732                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028732                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9445.164392                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9445.164392                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8883.847645                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8883.847645                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       255542                       # number of writebacks
+system.cpu0.dcache.writebacks::total           255542                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       211236                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       211236                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1463026                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1463026                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          516                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          516                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1674262                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1674262                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1674262                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1674262                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189291                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       189291                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131078                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       131078                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8469                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8469                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7773                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7773                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       320369                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       320369                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       320369                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       320369                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2800937917                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2800937917                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4685815512                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4685815512                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     79569505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     79569505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     68924555                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     68924555                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7486753429                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7486753429                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7486753429                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7486753429                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10315126500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10315126500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    849486399                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    849486399                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11164612899                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11164612899                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029873                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029873                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027190                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027190                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046180                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046180                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043346                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043346                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028714                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028714                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028714                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028714                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9395.383753                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9395.383753                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8867.175479                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8867.175479                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    43446349                       # DTB read hits
-system.cpu1.dtb.read_misses                     46684                       # DTB read misses
-system.cpu1.dtb.write_hits                    7088138                       # DTB write hits
-system.cpu1.dtb.write_misses                    12274                       # DTB write misses
+system.cpu1.dtb.read_hits                    43445270                       # DTB read hits
+system.cpu1.dtb.read_misses                     46285                       # DTB read misses
+system.cpu1.dtb.write_hits                    7088572                       # DTB write hits
+system.cpu1.dtb.write_misses                    12217                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2545                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     3731                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   361                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2504                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     3688                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   371                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      673                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                43493033                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7100412                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      674                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                43491555                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7100789                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         50534487                       # DTB hits
-system.cpu1.dtb.misses                          58958                       # DTB misses
-system.cpu1.dtb.accesses                     50593445                       # DTB accesses
-system.cpu1.itb.inst_hits                     9221438                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6034                       # ITB inst misses
+system.cpu1.dtb.hits                         50533842                       # DTB hits
+system.cpu1.dtb.misses                          58502                       # DTB misses
+system.cpu1.dtb.accesses                     50592344                       # DTB accesses
+system.cpu1.itb.inst_hits                     9223213                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6180                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1112,121 +1112,121 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1610                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1615                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1730                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1780                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 9227472                       # ITB inst accesses
-system.cpu1.itb.hits                          9221438                       # DTB hits
-system.cpu1.itb.misses                           6034                       # DTB misses
-system.cpu1.itb.accesses                      9227472                       # DTB accesses
-system.cpu1.numCycles                       353824423                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 9229393                       # ITB inst accesses
+system.cpu1.itb.hits                          9223213                       # DTB hits
+system.cpu1.itb.misses                           6180                       # DTB misses
+system.cpu1.itb.accesses                      9229393                       # DTB accesses
+system.cpu1.numCycles                       355232424                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 9470897                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           7703385                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            447489                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              6420671                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 5281203                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 9848764                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           8083275                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            447123                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              6868345                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 5662939                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  834152                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              50449                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles          22167103                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      70445168                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    9470897                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           6115355                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     14956565                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                4597208                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     88094                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              73687570                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                6011                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        61739                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       141755                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  9219303                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               857673                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3541                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         114241434                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.747913                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.114106                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  832004                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              49676                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles          22148379                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      71952458                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    9848764                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           6494943                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     15333431                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                4632908                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     88364                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              74838070                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                5775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        63991                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       141562                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          138                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  9221022                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               859641                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3677                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         115781579                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.750934                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.109459                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                99293168     86.92%     86.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  828706      0.73%     87.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1015866      0.89%     88.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 2054648      1.80%     90.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1280264      1.12%     91.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  613123      0.54%     91.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 2273093      1.99%     93.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  467514      0.41%     94.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 6415052      5.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               100456410     86.76%     86.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  829573      0.72%     87.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1015846      0.88%     88.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 2061622      1.78%     90.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1645380      1.42%     91.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  616095      0.53%     92.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 2274849      1.96%     94.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  467300      0.40%     94.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 6414504      5.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           114241434                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.026767                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.199096                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                23740446                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             73499308                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 13432186                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               537783                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               3031711                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1242419                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               102480                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              79700896                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               342426                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               3031711                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                25267828                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               33699109                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      35312301                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 12394168                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              4536317                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              73261010                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3244                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                714923                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              3281779                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents           33706                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           77426546                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            339504965                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       339445449                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            59516                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             49265102                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                28161444                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            486276                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        420659                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  8155263                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            14019935                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            8605996                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          1069297                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1521896                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  66318588                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             855610                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 90596015                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           108958                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       18341957                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     53651445                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        163223                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    114241434                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.793022                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.525613                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           115781579                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.027725                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.202550                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                23776389                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             74601447                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 13781615                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               561009                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               3061119                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1241407                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               102665                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              81190791                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               341149                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               3061119                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                25333003                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               33967991                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      36116187                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 12703540                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              4599739                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              74711209                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                20422                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                719883                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              3284162                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents           33659                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           79078972                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            344223554                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       344164086                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            59468                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             50180386                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                28898586                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            486916                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        421354                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  8389500                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            14026564                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            8607423                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          1068694                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1518812                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  67421543                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1209489                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 91958955                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           109721                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       18898752                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     53543776                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        290002                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    115781579                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.794245                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.521941                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           83094748     72.74%     72.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            8828314      7.73%     80.46% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4518450      3.96%     84.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3737052      3.27%     87.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           10664138      9.33%     97.02% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1972512      1.73%     98.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1063413      0.93%     99.68% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             282401      0.25%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              80406      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           83973534     72.53%     72.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            9124499      7.88%     80.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4576997      3.95%     84.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            4009566      3.46%     87.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           10699106      9.24%     97.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1974757      1.71%     98.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1060771      0.92%     99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             281863      0.24%     99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              80486      0.07%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      114241434                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      115781579                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  29108      0.37%      0.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  29310      0.37%      0.37% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntMult                   993      0.01%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.38% # attempts to use FU when none available
@@ -1255,403 +1255,397 @@ system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.38% # at
 system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               7574349     95.84%     96.22% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               298565      3.78%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               7573445     95.84%     96.23% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               298199      3.77%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            86745      0.10%      0.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             38337785     42.32%     42.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               61539      0.07%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 4      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              6      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1698      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            44639306     49.27%     91.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7468915      8.24%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass           313737      0.34%      0.34% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             39470238     42.92%     43.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               61477      0.07%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 2      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1690      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            44643108     48.55%     91.88% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            7468676      8.12%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              90596015                       # Type of FU issued
-system.cpu1.iq.rate                          0.256048                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7903015                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.087234                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         303489486                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         85529327                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     54443530                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              14763                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              8091                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6830                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              98404572                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7713                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          368848                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              91958955                       # Type of FU issued
+system.cpu1.iq.rate                          0.258870                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    7901947                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.085929                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         307754751                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         87542996                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     55769663                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14772                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8137                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6817                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              99539441                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7724                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          371642                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      4030694                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         6909                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        21919                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1587988                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      4037130                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         6814                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        21954                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1589436                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     31965710                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      1045299                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     31965709                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      1043610                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               3031711                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               25598263                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               405605                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           67299344                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           135063                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             14019935                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             8605996                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            545729                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 81019                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 7196                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         21919                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        232087                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       197105                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              429192                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             87765278                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             43831578                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          2830737                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               3061119                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               25601852                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               406330                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           68756671                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           131432                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             14026564                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             8607423                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            899609                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 81519                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 7124                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         21954                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        226065                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       196785                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              422850                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             89098857                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             43830249                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          2860098                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       125146                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    51224987                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 7024509                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7393409                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.248048                       # Inst execution rate
-system.cpu1.iew.wb_sent                      86598496                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     54450360                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 30044182                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 53342809                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       125639                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    51224079                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 7396455                       # Number of branches executed
+system.cpu1.iew.exec_stores                   7393830                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.250818                       # Inst execution rate
+system.cpu1.iew.wb_sent                      87931251                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     55776480                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 30792122                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 54566321                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.153891                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.563228                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.157014                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.564306                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      38036954                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps        48396972                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts       18817114                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         692387                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           376510                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    111258144                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.434997                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.402953                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      38938347                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        49298719                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts       19014978                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         919487                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           376070                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    112768879                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.437166                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.403258                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     94210177     84.68%     84.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      8524716      7.66%     92.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2208233      1.98%     94.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1307974      1.18%     95.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1064973      0.96%     96.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       589982      0.53%     96.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1003368      0.90%     97.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       487910      0.44%     98.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1860811      1.67%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     95484340     84.67%     84.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      8537208      7.57%     92.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2210726      1.96%     94.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1312266      1.16%     95.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1283048      1.14%     96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       588048      0.52%     97.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1003635      0.89%     97.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       487845      0.43%     98.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1861763      1.65%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    111258144                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            38036954                       # Number of instructions committed
-system.cpu1.commit.committedOps              48396972                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    112768879                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            38938347                       # Number of instructions committed
+system.cpu1.commit.committedOps              49298719                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      17007249                       # Number of memory references committed
-system.cpu1.commit.loads                      9989241                       # Number of loads committed
-system.cpu1.commit.membars                     202226                       # Number of memory barriers committed
-system.cpu1.commit.branches                   5993368                       # Number of branches committed
+system.cpu1.commit.refs                      17007421                       # Number of memory references committed
+system.cpu1.commit.loads                      9989434                       # Number of loads committed
+system.cpu1.commit.membars                     202281                       # Number of memory barriers committed
+system.cpu1.commit.branches                   6220621                       # Number of branches committed
 system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 43235909                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              556157                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1860811                       # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts                 43690243                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              556165                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1861763                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   175585773                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  137553768                       # The number of ROB writes
-system.cpu1.timesIdled                        1520299                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      239582989                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  4808538839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   37967315                       # Number of Instructions Simulated
-system.cpu1.committedOps                     48327333                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             37967315                       # Number of Instructions Simulated
-system.cpu1.cpi                              9.319185                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        9.319185                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.107306                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.107306                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               393921761                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               56840694                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     4925                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    2334                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               90313719                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                429414                       # number of misc regfile writes
-system.cpu1.icache.replacements                622931                       # number of replacements
-system.cpu1.icache.tagsinuse               498.760560                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 8545880                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                623443                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 13.707556                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           74633827000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   498.760560                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.974142                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.974142                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      8545880                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        8545880                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      8545880                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         8545880                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      8545880                       # number of overall hits
-system.cpu1.icache.overall_hits::total        8545880                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       673372                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       673372                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       673372                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        673372                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       673372                       # number of overall misses
-system.cpu1.icache.overall_misses::total       673372                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10716931993                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  10716931993                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  10716931993                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  10716931993                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  10716931993                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  10716931993                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      9219252                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      9219252                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      9219252                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      9219252                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      9219252                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      9219252                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073040                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.073040                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073040                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.073040                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073040                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.073040                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15915.321684                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15915.321684                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      1332494                       # number of cycles access was blocked
+system.cpu1.rob.rob_reads                   178106600                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  139781050                       # The number of ROB writes
+system.cpu1.timesIdled                        1519184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      239450845                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  4808685831                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   38868708                       # Number of Instructions Simulated
+system.cpu1.committedOps                     49229080                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             38868708                       # Number of Instructions Simulated
+system.cpu1.cpi                              9.139291                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        9.139291                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.109418                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.109418                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               398713179                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               58485097                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     4918                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    2338                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads               91819776                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                429481                       # number of misc regfile writes
+system.cpu1.icache.replacements                621812                       # number of replacements
+system.cpu1.icache.tagsinuse               498.762593                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 8548797                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                622324                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 13.736891                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           74633258000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   498.762593                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.974146                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.974146                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      8548797                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        8548797                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      8548797                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         8548797                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      8548797                       # number of overall hits
+system.cpu1.icache.overall_hits::total        8548797                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       672174                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       672174                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       672174                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        672174                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       672174                       # number of overall misses
+system.cpu1.icache.overall_misses::total       672174                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10613540997                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  10613540997                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  10613540997                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  10613540997                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  10613540997                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  10613540997                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      9220971                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      9220971                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      9220971                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      9220971                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      9220971                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      9220971                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.072896                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.072896                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.072896                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.072896                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.072896                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.072896                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15789.871368                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15789.871368                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      1180997                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              205                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs              198                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  6499.970732                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5964.631313                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks        33068                       # number of writebacks
-system.cpu1.icache.writebacks::total            33068                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49906                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        49906                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        49906                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        49906                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        49906                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        49906                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       623466                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       623466                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       623466                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       623466                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       623466                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       623466                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8227032008                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8227032008                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8227032008                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8227032008                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8227032008                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8227032008                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49820                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        49820                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        49820                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        49820                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        49820                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        49820                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       622354                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       622354                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       622354                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       622354                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       622354                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       622354                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8128418498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8128418498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8128418498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8128418498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8128418498                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8128418498                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3154000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      3154000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067627                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.067627                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.067627                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067493                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.067493                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.067493                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                362729                       # number of replacements
-system.cpu1.dcache.tagsinuse               487.126779                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                13112337                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                363073                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 36.114878                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           70483759000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   487.126779                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.951419                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.951419                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8613908                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8613908                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4252702                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4252702                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       105106                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total       105106                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100709                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total       100709                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     12866610                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        12866610                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     12866610                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       12866610                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       410185                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       410185                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1595357                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1595357                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14278                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        14278                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10900                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10900                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      2005542                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       2005542                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      2005542                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      2005542                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8114216000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   8114216000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  66620735237                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  66620735237                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    166584000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    166584000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     94819000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     94819000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  74734951237                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  74734951237                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  74734951237                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  74734951237                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9024093                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9024093                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5848059                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5848059                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       119384                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       119384                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       111609                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14872152                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14872152                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14872152                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14872152                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045454                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.045454                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272801                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.272801                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119597                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119597                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097662                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097662                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134852                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.134852                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134852                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.134852                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8698.990826                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8698.990826                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     29196505                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      5606000                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6645                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets            174                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4393.755455                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805                       # average number of cycles each access was blocked
+system.cpu1.dcache.replacements                362958                       # number of replacements
+system.cpu1.dcache.tagsinuse               487.094495                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                13107479                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                363304                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 36.078543                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           70482639000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   487.094495                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.951356                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.951356                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8608268                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8608268                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4252418                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4252418                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       106100                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total       106100                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100714                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total       100714                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     12860686                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        12860686                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     12860686                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       12860686                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       410615                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       410615                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1595619                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1595619                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14222                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        14222                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10905                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10905                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      2006234                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       2006234                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      2006234                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      2006234                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8133768000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   8133768000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  66485489237                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  66485489237                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    165213500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    165213500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     94467000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     94467000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  74619257237                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  74619257237                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  74619257237                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  74619257237                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9018883                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9018883                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5848037                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5848037                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       120322                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       120322                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111619                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       111619                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14866920                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14866920                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14866920                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14866920                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045528                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.045528                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272847                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.272847                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118199                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118199                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097698                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097698                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134946                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.134946                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134946                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.134946                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41667.521656                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11616.755731                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11616.755731                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8662.723521                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8662.723521                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37193.695868                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 37193.695868                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37193.695868                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 37193.695868                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     29476015                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      5620000                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6671                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets            172                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4418.530205                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       327467                       # number of writebacks
-system.cpu1.dcache.writebacks::total           327467                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       179191                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       179191                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1432552                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1432552                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1457                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1457                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1611743                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1611743                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1611743                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1611743                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       230994                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       230994                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162805                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       162805                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12821                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12821                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10892                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10892                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       393799                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       393799                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       393799                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       393799                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3545762451                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3545762451                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5565749199                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5565749199                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    104395505                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    104395505                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     60832506                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     60832506                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9111511650                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   9111511650                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9111511650                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   9111511650                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40571899654                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40571899654                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025597                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027839                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027839                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.107393                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.107393                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097591                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097591                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026479                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026479                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026479                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026479                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8142.539973                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8142.539973                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5585.062982                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5585.062982                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       327729                       # number of writebacks
+system.cpu1.dcache.writebacks::total           327729                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       179332                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       179332                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1432824                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1432824                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1447                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1447                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1612156                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1612156                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1612156                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1612156                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231283                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       231283                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162795                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       162795                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12775                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12775                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10900                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10900                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       394078                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       394078                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       394078                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       394078                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3556387454                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3556387454                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5557887685                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5557887685                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    103446504                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    103446504                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     60421505                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     60421505                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9114275139                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   9114275139                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9114275139                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   9114275139                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40580989302                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40580989302                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025644                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025644                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027838                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027838                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.106173                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.106173                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097654                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097654                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026507                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026507                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026507                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026507                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8097.573699                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8097.573699                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5543.257339                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5543.257339                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1673,18 +1667,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1305278151135                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1305599683923                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   43785                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   43782                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   53912                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   53899                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 71f536288..9e6ff3218 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -581,7 +581,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 34717b2ec..c9f3d2864 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 17:04:56
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 02:23:14
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2502549875500 because m5_exit instruction encountered
+Exiting @ tick 2503329223500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 6df4de0df..b903804f3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,54 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.502550                       # Number of seconds simulated
-sim_ticks                                2502549875500                       # Number of ticks simulated
-final_tick                               2502549875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.503329                       # Number of seconds simulated
+sim_ticks                                2503329223500                       # Number of ticks simulated
+final_tick                               2503329223500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90191                       # Simulator instruction rate (inst/s)
-host_op_rate                                   116452                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3788406278                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386884                       # Number of bytes of host memory used
-host_seconds                                   660.58                       # Real time elapsed on the host
-sim_insts                                    59578267                       # Number of instructions simulated
-sim_ops                                      76925839                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    118994504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
+host_inst_rate                                  62297                       # Simulator instruction rate (inst/s)
+host_op_rate                                    80132                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2573650165                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 394796                       # Number of bytes of host memory used
+host_seconds                                   972.68                       # Real time elapsed on the host
+sim_insts                                    60594713                       # Number of instructions simulated
+sim_ops                                      77942287                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            800128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094928                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            128893400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       800128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          800128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3786176                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            799552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9094032                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129435024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       799552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          799552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785216                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6802248                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14874313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           6801288                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12502                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142142                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15029017                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59159                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12493                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096888                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59144                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813177                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47549304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813162                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47751475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1483                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3634264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51504828                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319725                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319725                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1512927                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1205200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2718127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1512927                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47549304                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               319395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3632775                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51705154                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          319395                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             319395                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1512073                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1204824                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2716897                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1512073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47751475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1483                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4839464                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54222954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              319395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4837599                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54422052                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst           26
 system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64431                       # number of replacements
-system.l2c.tagsinuse                     51237.782352                       # Cycle average of tags in use
-system.l2c.total_refs                         2028510                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.624716                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2492014554000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36760.884600                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       47.476285                       # Average occupied blocks per requestor
+system.l2c.replacements                         64407                       # number of replacements
+system.l2c.tagsinuse                     51237.721374                       # Cycle average of tags in use
+system.l2c.total_refs                         1963815                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129804                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         15.129079                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2492699118000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36773.515896                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       46.128401                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8187.042847                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6242.378435                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.560927                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000724                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu.inst           8177.854263                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6240.222629                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.561119                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000704                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124924                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095251                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781827                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        121963                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11826                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              977935                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              383708                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1495432                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          675442                       # number of Writeback hits
-system.l2c.Writeback_hits::total               675442                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               42                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  42                       # number of UpgradeReq hits
+system.l2c.occ_percent::cpu.inst             0.124784                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.095218                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.781826                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        123734                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         11927                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              976636                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              387128                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1499425                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          607519                       # number of Writeback hits
+system.l2c.Writeback_hits::total               607519                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               41                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  41                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112737                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112737                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         121963                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11826                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               977935                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               496445                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1608169                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        121963                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11826                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              977935                       # number of overall hits
-system.l2c.overall_hits::cpu.data              496445                       # number of overall hits
-system.l2c.overall_hits::total                1608169                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            112732                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112732                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         123734                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          11927                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               976636                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               499860                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1612157                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        123734                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         11927                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              976636                       # number of overall hits
+system.l2c.overall_hits::cpu.data              499860                       # number of overall hits
+system.l2c.overall_hits::total                1612157                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12384                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             12374                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23135                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                23124                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133229                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133229                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
+system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133219                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133219                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12384                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143920                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156364                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           59                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              12374                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143910                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156343                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           58                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12384                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143920                       # number of overall misses
-system.l2c.overall_misses::total               156364                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3091500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.inst             12374                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143910                       # number of overall misses
+system.l2c.overall_misses::total               156343                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3035000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    659591498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    562236498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1224979496                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       944500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       944500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   7069904999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7069904999                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      3091500                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    659327498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    562370998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1224793496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       994500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       994500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7086596499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7086596499                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      3035000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    659591498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7632141497                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8294884495                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      3091500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu.inst    659327498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7648967497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8311389995                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      3035000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    659591498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7632141497                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8294884495                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       122022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11827                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          990319                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          394399                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1518567                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       675442                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           675442                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2951                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2951                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        245966                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           245966                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       122022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11827                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           990319                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           640365                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1764533                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       122022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11827                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          990319                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          640365                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1764533                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000085                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012505                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.027107                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015235                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.985768                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.985768                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541656                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541656                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000085                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012505                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.224747                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088615                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000085                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012505                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.224747                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088615                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu.inst    659327498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7648967497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8311389995                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       123792                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        11928                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          989010                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          397819                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1522549                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       607519                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           607519                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2950                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2950                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           18                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            18                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        245951                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           245951                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       123792                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        11928                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           989010                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           643770                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1768500                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       123792                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        11928                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          989010                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          643770                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1768500                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000084                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012512                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026874                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015188                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.986102                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.986102                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.111111                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.111111                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.541649                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541649                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000084                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012512                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.223543                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.088404                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000084                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012512                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.223543                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.088404                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52949.189367                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   324.682021                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   324.682021                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53065.811490                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53283.295458                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52602.282106                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52966.333506                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   341.870058                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   341.870058                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53195.088531                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53195.088531                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53048.556541                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53161.254389                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53048.556541                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53161.254389                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -212,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59159                       # number of writebacks
-system.l2c.writebacks::total                    59159                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              9                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               59144                       # number of writebacks
+system.l2c.writebacks::total                    59144                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             61                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                69                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              61                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 69                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             61                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                69                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12375                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10629                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23064                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12366                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10630                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23055                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133229                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133229                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133219                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133219                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12375                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143858                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156293                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12366                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143849                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156274                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12375                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143858                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156293                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu.inst        12366                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143849                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156274                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    508160500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    430170499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    940750999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116825000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    116825000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5436034999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5436034999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    507997999                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    430294500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    940666499                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    117136000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    117136000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5457467999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5457467999                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    508160500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5866205498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6376785998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    507997999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5887762499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6398134498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    508160500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5866205498                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6376785998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    507997999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5887762499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6398134498                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31373446015                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31373446015                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131412946500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131418269500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31416947511                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31416947511                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162795884015                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026950                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015188                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985768                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.985768                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541656                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541656                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088575                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088575                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 162835217011                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026721                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015142                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986102                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.986102                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.111111                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541649                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541649                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.088365                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.088365                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -332,27 +332,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51771660                       # DTB read hits
-system.cpu.dtb.read_misses                      81258                       # DTB read misses
-system.cpu.dtb.write_hits                    11880398                       # DTB write hits
-system.cpu.dtb.write_misses                     17961                       # DTB write misses
+system.cpu.dtb.read_hits                     51771178                       # DTB read hits
+system.cpu.dtb.read_misses                      82022                       # DTB read misses
+system.cpu.dtb.write_hits                    11879780                       # DTB write hits
+system.cpu.dtb.write_misses                     18404                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4471                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      3044                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    609                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4476                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2874                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    631                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1282                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51852918                       # DTB read accesses
-system.cpu.dtb.write_accesses                11898359                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1260                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51853200                       # DTB read accesses
+system.cpu.dtb.write_accesses                11898184                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63652058                       # DTB hits
-system.cpu.dtb.misses                           99219                       # DTB misses
-system.cpu.dtb.accesses                      63751277                       # DTB accesses
-system.cpu.itb.inst_hits                     13142261                       # ITB inst hits
-system.cpu.itb.inst_misses                      12247                       # ITB inst misses
+system.cpu.dtb.hits                          63650958                       # DTB hits
+system.cpu.dtb.misses                          100426                       # DTB misses
+system.cpu.dtb.accesses                      63751384                       # DTB accesses
+system.cpu.itb.inst_hits                     13147400                       # ITB inst hits
+system.cpu.itb.inst_misses                      12275                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2634                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2641                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      3416                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13154508                       # ITB inst accesses
-system.cpu.itb.hits                          13142261                       # DTB hits
-system.cpu.itb.misses                           12247                       # DTB misses
-system.cpu.itb.accesses                      13154508                       # DTB accesses
-system.cpu.numCycles                        413642740                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 13159675                       # ITB inst accesses
+system.cpu.itb.hits                          13147400                       # DTB hits
+system.cpu.itb.misses                           12275                       # DTB misses
+system.cpu.itb.accesses                      13159675                       # DTB accesses
+system.cpu.numCycles                        415310668                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14974990                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11915620                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             753400                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10068197                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7820088                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 15527738                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12466555                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             753811                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10646284                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8367014                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1448775                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80927                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           33422471                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       99542070                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14974990                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9268863                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21759182                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6002262                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     163536                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               93319816                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2533                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        133610                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208459                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          397                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13138017                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1024097                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6504                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          153128307                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.804842                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.182667                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1449693                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               80905                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33357472                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      101736318                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15527738                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9816707                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22310929                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6078281                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     161634                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               94635812                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2484                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        132549                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       208778                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          375                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13143214                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1025665                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6564                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154991090                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.809239                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.178893                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                131386008     85.80%     85.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1369017      0.89%     86.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1759019      1.15%     87.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2640315      1.72%     89.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1819667      1.19%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1142419      0.75%     91.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2920911      1.91%     93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   807762      0.53%     93.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9283189      6.06%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                132697054     85.62%     85.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1371702      0.89%     86.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1758298      1.13%     87.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2653739      1.71%     89.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2357523      1.52%     90.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1143564      0.74%     91.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2918516      1.88%     93.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   809258      0.52%     94.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9281436      5.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            153128307                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.036203                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.240647                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 35537493                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              93048586                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19509299                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1086349                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3946580                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2100058                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174557                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              116122172                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                568338                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3946580                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37621271                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39594801                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       46881047                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18412397                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6672211                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              108597287                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  4175                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1156489                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4484156                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            30967                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           113073752                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             499820515                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        499727174                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             93341                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              77686691                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 35387060                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             898607                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         797702                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13307124                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             21058263                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13875749                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1965166                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2564814                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   99781831                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1555350                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 124613166                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            199798                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23638127                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65777806                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         268083                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     153128307                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.813783                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.516400                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154991090                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.037388                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.244964                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35540110                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              94304374                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20024957                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1112327                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4009322                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2100739                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                174603                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              118268322                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                570412                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4009322                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37657945                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                39869078                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       47822984                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18880557                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6751204                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110681454                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 22988                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1160036                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4497834                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            31020                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           115504222                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             506609726                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        506516210                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             93516                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78727449                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 36776772                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             900485                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         799637                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13564830                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21065339                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13879000                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1961867                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2663971                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  101316574                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2057711                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 126458108                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            199553                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        24657438                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65563204                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         513311                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154991090                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.815906                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.514046                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           107849903     70.43%     70.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14560254      9.51%     79.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7302452      4.77%     84.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5913038      3.86%     88.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12593494      8.22%     96.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2809204      1.83%     98.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1536315      1.00%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              438168      0.29%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              125479      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           108868078     70.24%     70.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14887887      9.61%     79.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7383585      4.76%     84.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6313472      4.07%     88.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12622401      8.14%     96.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2812506      1.81%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1537255      0.99%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              440277      0.28%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125629      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       153128307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154991090                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   53462      0.61%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   54148      0.61%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.61% # attempts to use FU when none available
@@ -504,399 +504,397 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8367005     94.75%     95.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                409700      4.64%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8364176     94.75%     95.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                409089      4.63%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            106530      0.09%      0.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58482659     46.93%     47.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95330      0.08%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  11      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53414157     42.86%     89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12512351     10.04%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60068751     47.50%     47.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95236      0.08%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               7      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53417106     42.24%     90.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12511205      9.89%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              124613166                       # Type of FU issued
-system.cpu.iq.rate                           0.301258                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8830169                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.070861                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          411460543                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         124996425                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85630389                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               22925                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12868                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10343                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              133324707                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12098                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           646336                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              126458108                       # Type of FU issued
+system.cpu.iq.rate                           0.304490                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8827417                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.069805                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          417011386                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128052835                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87416470                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               22950                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12920                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10331                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              134909754                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12105                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           645788                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5343093                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11106                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        35068                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2077574                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5350138                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11136                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        35101                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2080838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107202                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1049886                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107263                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1048290                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3946580                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                29463666                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                540836                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           101593235                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              21058263                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13875749                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             964547                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 125689                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 40656                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          35068                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         381127                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       332167                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               713294                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             121438397                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52461807                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3174769                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4009322                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                29478613                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                536036                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           103628902                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            217385                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21065339                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13879000                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1466402                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 126510                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 31155                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          35101                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         376939                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       332400                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               709339                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             123236608                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52461044                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3221500                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        256054                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64853171                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11412736                       # Number of branches executed
-system.cpu.iew.exec_stores                   12391364                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.293583                       # Inst execution rate
-system.cpu.iew.wb_sent                      120063166                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85640732                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  46459932                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  84649521                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        254617                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64851969                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11926568                       # Number of branches executed
+system.cpu.iew.exec_stores                   12390925                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.296734                       # Inst execution rate
+system.cpu.iew.wb_sent                      121860265                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87426801                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47494075                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  86379183                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.207040                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.548851                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.210509                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.549832                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       59728648                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         77076220                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24329020                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1287267                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            625309                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    149264139                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.516375                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.492760                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       60745094                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         78092668                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        24728606                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1544400                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            625654                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151064180                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.516950                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.491641                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    121340444     81.29%     81.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13976446      9.36%     90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3929866      2.63%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2230737      1.49%     94.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1774137      1.19%     95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1064202      0.71%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1398926      0.94%     97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       658331      0.44%     98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2891050      1.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122872114     81.34%     81.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13991345      9.26%     90.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3943128      2.61%     93.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2231050      1.48%     94.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2009345      1.33%     96.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1063949      0.70%     96.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1402638      0.93%     97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       655924      0.43%     98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2894687      1.92%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    149264139                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             59728648                       # Number of instructions committed
-system.cpu.commit.committedOps               77076220                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151064180                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60745094                       # Number of instructions committed
+system.cpu.commit.committedOps               78092668                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513345                       # Number of memory references committed
-system.cpu.commit.loads                      15715170                       # Number of loads committed
-system.cpu.commit.membars                      413057                       # Number of memory barriers committed
-system.cpu.commit.branches                    9904308                       # Number of branches committed
+system.cpu.commit.refs                       27513363                       # Number of memory references committed
+system.cpu.commit.loads                      15715201                       # Number of loads committed
+system.cpu.commit.membars                      413054                       # Number of memory barriers committed
+system.cpu.commit.branches                   10161447                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  68616986                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995953                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2891050                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69131310                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               995952                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2894687                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    246021016                       # The number of ROB reads
-system.cpu.rob.rob_writes                   206855771                       # The number of ROB writes
-system.cpu.timesIdled                         1910853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       260514433                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4591368963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    59578267                       # Number of Instructions Simulated
-system.cpu.committedOps                      76925839                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              59578267                       # Number of Instructions Simulated
-system.cpu.cpi                               6.942846                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.942846                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.144033                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.144033                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                551124722                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87730818                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8186                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2858                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               131789755                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912697                       # number of misc regfile writes
-system.cpu.icache.replacements                 991190                       # number of replacements
-system.cpu.icache.tagsinuse                511.611770                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12061455                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 991702                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.162378                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6426198000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.611770                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999242                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999242                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12061455                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12061455                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12061455                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12061455                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12061455                       # number of overall hits
-system.cpu.icache.overall_hits::total        12061455                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1076423                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1076423                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1076423                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1076423                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1076423                       # number of overall misses
-system.cpu.icache.overall_misses::total       1076423                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16851120991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16851120991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16851120991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16851120991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16851120991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16851120991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13137878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13137878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13137878                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13137878                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13137878                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13137878                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081933                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.081933                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.081933                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.081933                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.081933                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.081933                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15654.738881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15654.738881                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2871493                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                    249075594                       # The number of ROB reads
+system.cpu.rob.rob_writes                   209750294                       # The number of ROB writes
+system.cpu.timesIdled                         1905944                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       260319578                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4591259733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60594713                       # Number of Instructions Simulated
+system.cpu.committedOps                      77942287                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60594713                       # Number of Instructions Simulated
+system.cpu.cpi                               6.853909                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.853909                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145902                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.145902                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                557815348                       # number of integer regfile reads
+system.cpu.int_regfile_writes                90098492                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8218                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2870                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               134021846                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 912706                       # number of misc regfile writes
+system.cpu.icache.replacements                 989908                       # number of replacements
+system.cpu.icache.tagsinuse                511.610984                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12068184                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 990420                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.184915                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6426400000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.610984                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999240                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999240                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12068184                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12068184                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12068184                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12068184                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12068184                       # number of overall hits
+system.cpu.icache.overall_hits::total        12068184                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1074896                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1074896                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1074896                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1074896                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1074896                       # number of overall misses
+system.cpu.icache.overall_misses::total       1074896                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16638687991                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16638687991                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16638687991                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16638687991                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16638687991                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16638687991                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13143080                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13143080                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13143080                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13143080                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13143080                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13143080                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081784                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081784                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081784                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081784                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081784                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081784                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15479.346831                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15479.346831                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2960492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               461                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               448                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  6228.835141                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6608.241071                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        67899                       # number of writebacks
-system.cpu.icache.writebacks::total             67899                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84680                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84680                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84680                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84680                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84680                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84680                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991743                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       991743                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       991743                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       991743                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       991743                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       991743                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12825867499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12825867499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12825867499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12825867499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12825867499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12825867499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84437                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        84437                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        84437                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        84437                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        84437                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        84437                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       990459                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       990459                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       990459                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       990459                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       990459                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       990459                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12623481992                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12623481992                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12623481992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12623481992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12623481992                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12623481992                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075487                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.075487                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.075487                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075360                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.075360                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.075360                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 643139                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991335                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21733833                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 643651                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.766487                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 643258                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991338                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 21734239                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 643770                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  33.760876                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991335                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.991338                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13904166                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13904166                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7257095                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7257095                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       283844                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       283844                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285639                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285639                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21161261                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21161261                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21161261                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21161261                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       765252                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        765252                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2993311                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2993311                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13765                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13765                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3758563                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3758563                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3758563                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3758563                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14844603000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14844603000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 129412035593                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223977000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    223977000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       405000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       405000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 144256638593                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 144256638593                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 144256638593                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 144256638593                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14669418                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14669418                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       297609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285658                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285658                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24919824                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24919824                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24919824                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24919824                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052166                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052166                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292019                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.292019                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046252                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046252                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000067                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000067                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150826                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150826                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150826                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150826                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38380.795691                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38380.795691                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32633902                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7260500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7285                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             283                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4479.602196                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032                       # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data     13902749                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13902749                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7257426                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7257426                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       285261                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       285261                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285646                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285646                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21160175                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21160175                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21160175                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21160175                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       765054                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        765054                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2992955                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2992955                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13791                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13791                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           18                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           18                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3758009                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3758009                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3758009                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3758009                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14856915000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14856915000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 130200810067                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 130200810067                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223590500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    223590500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       349500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       349500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145057725067                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145057725067                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145057725067                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145057725067                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14667803                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14667803                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10250381                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10250381                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299052                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       299052                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285664                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285664                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24918184                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24918184                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24918184                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24918184                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052159                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052159                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.291985                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.291985                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046116                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046116                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000063                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.150814                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.150814                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.150814                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.150814                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19419.433138                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19419.433138                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43502.428225                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43502.428225                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16212.783700                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16212.783700                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19416.666667                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19416.666667                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38599.621520                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38599.621520                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     34077900                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7429000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7467                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             284                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4563.800723                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26158.450704                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607543                       # number of writebacks
-system.cpu.dcache.writebacks::total            607543                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379767                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       379767                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744505                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2744505                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3124272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3124272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3124272                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3124272                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385485                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385485                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248806                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248806                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12312                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12312                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634291                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634291                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634291                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634291                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6242554097                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6242554097                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9246380950                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9246380950                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    164108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    164108000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       341500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       341500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15488935047                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15488935047                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15488935047                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15488935047                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41215087708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41215087708                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024273                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024273                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041370                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041370                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000067                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000067                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025453                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025453                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607519                       # number of writebacks
+system.cpu.dcache.writebacks::total            607519                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379422                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       379422                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744177                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2744177                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1481                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1481                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3123599                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3123599                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3123599                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3123599                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385632                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385632                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248778                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248778                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12310                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12310                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           18                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           18                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634410                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634410                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634410                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634410                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6262166095                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6262166095                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9286622435                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9286622435                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    163471000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    163471000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       289000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       289000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15548788530                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15548788530                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15548788530                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15548788530                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41268229410                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41268229410                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026291                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026291                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024270                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024270                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041163                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041163                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000063                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025460                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025460                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -918,16 +916,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1298563544001                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1305424568773                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88049                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    88047                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 1fa068d9c..2ecc483cf 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -1261,7 +1261,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1281,7 +1281,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index e7dca044c..22a267134 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 22 2012 08:05:39
-gem5 started Jul 22 2012 08:05:57
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jul 26 2012 21:30:36
+gem5 started Jul 27 2012 00:44:18
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5172902281500 because m5_exit instruction encountered
+Exiting @ tick 5172910256500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 4fa4cc520..d3e4451ad 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,186 +1,186 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.172902                       # Number of seconds simulated
-sim_ticks                                5172902281500                       # Number of ticks simulated
-final_tick                               5172902281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.172910                       # Number of seconds simulated
+sim_ticks                                5172910256500                       # Number of ticks simulated
+final_tick                               5172910256500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 117061                       # Simulator instruction rate (inst/s)
-host_op_rate                                   230687                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1419746087                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420308                       # Number of bytes of host memory used
-host_seconds                                  3643.54                       # Real time elapsed on the host
-sim_insts                                   426515724                       # Number of instructions simulated
-sim_ops                                     840516219                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2496512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1067840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10426304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13994560                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1067840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1067840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9194240                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9194240                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        39008                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           55                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16685                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             162911                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                218665                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143660                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143660                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       482613                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            680                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             74                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               206430                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2015562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2705359                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          206430                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             206430                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1777385                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1777385                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1777385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       482613                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           680                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            74                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              206430                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2015562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4482745                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        107419                       # number of replacements
-system.l2c.tagsinuse                     64844.084797                       # Cycle average of tags in use
-system.l2c.total_refs                         3992672                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        171622                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         23.264337                       # Average number of references to valid blocks.
+host_inst_rate                                 136129                       # Simulator instruction rate (inst/s)
+host_op_rate                                   268264                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1651021148                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 373420                       # Number of bytes of host memory used
+host_seconds                                  3133.16                       # Real time elapsed on the host
+sim_insts                                   426513995                       # Number of instructions simulated
+sim_ops                                     840512563                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2464064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         2944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1067584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10442240                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13977280                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1067584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1067584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9176384                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9176384                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38501                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           46                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16681                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             163160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                218395                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143381                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143381                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       476340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               206380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2018639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2702015                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          206380                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             206380                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1773931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1773931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1773931                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       476340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              206380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2018639                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4475945                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        106892                       # number of replacements
+system.l2c.tagsinuse                     64846.239814                       # Cycle average of tags in use
+system.l2c.total_refs                         3994467                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        171328                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         23.314735                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50135.967843                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       12.897301                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.156788                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           3372.666022                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data          11322.396844                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.765014                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000197                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.051463                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.172766                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.989442                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        110667                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          8396                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst             1054432                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1345104                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2518599                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1613189                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1613189                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              337                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 337                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            163997                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               163997                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         110667                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           8396                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst              1054432                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1509101                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2682596                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        110667                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          8396                       # number of overall hits
-system.l2c.overall_hits::cpu.inst             1054432                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1509101                       # number of overall hits
-system.l2c.overall_hits::total                2682596                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           55                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             16686                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             35012                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                51759                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           1516                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1516                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          128839                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             128839                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           55                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              16686                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             163851                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                180598                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           55                       # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker            6                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             16686                       # number of overall misses
-system.l2c.overall_misses::cpu.data            163851                       # number of overall misses
-system.l2c.overall_misses::total               180598                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2907000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker       312000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    885914499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   1865182494                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2754315993                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     39171500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     39171500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6715513999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6715513999                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      2907000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker       312000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    885914499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   8580696493                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      9469829992                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      2907000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker       312000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    885914499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   8580696493                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     9469829992                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       110722                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         8402                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst         1071118                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1380116                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2570358                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1613189                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1613189                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         1853                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1853                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        292836                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292836                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       110722                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         8402                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst          1071118                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1672952                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2863194                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       110722                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         8402                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1071118                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1672952                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2863194                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000714                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.015578                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.025369                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020137                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.818133                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.818133                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.439970                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.439970                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000714                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.015578                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.097941                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.063076                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000714                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.015578                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.097941                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.063076                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average ReadReq miss latency
+system.l2c.occ_blocks::writebacks        50145.406461                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       11.508776                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.169764                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3382.865025                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data          11306.289787                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.765158                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000176                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000003                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.051618                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.172520                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.989475                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        113294                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          9300                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1056563                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1345318                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2524475                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1607595                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1607595                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              334                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 334                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            163366                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               163366                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         113294                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           9300                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1056563                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1508684                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2687841                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        113294                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          9300                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1056563                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1508684                       # number of overall hits
+system.l2c.overall_hits::total                2687841                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           46                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             16683                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             35188                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                51924                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2935                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2935                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          128896                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             128896                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           46                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              16683                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             164084                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                180820                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           46                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker            7                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             16683                       # number of overall misses
+system.l2c.overall_misses::cpu.data            164084                       # number of overall misses
+system.l2c.overall_misses::total               180820                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2412500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       364000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    885747500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1875717995                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2764241995                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     38348000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     38348000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6718316497                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6718316497                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      2412500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       364000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    885747500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8594034492                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9482558492                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      2412500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       364000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    885747500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8594034492                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9482558492                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       113340                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         9307                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1073246                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1380506                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2576399                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1607595                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1607595                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         3269                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3269                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        292262                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292262                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       113340                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         9307                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1073246                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1672768                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2868661                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       113340                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         9307                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1073246                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1672768                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2868661                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000752                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.015544                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.025489                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020154                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.897828                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.897828                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.441029                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.441029                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000752                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.015544                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.098091                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.063033                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000752                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.015544                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.098091                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.063033                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 53214.242798                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52123.301167                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53092.819037                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 53305.615409                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53236.306814                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13065.758092                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 13065.758092                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52121.993677                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52121.993677                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52368.899140                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52435.962702                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53092.819037                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52375.822701                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52441.978166                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52368.899140                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52435.962702                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53092.819037                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52375.822701                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52441.978166                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96993                       # number of writebacks
-system.l2c.writebacks::total                    96993                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               96714                       # number of writebacks
+system.l2c.writebacks::total                    96714                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 3                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           55                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        16685                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        35011                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           51757                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         1516                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1516                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       128839                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        128839                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           55                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         16685                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        163850                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           180596                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           55                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        16685                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       163850                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          180596                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       240000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    682427500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1437356500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2122265000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     61068000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     61068000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5163609501                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5163609501                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker       240000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    682427500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   6600966001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   7285874501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2241000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker       240000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    682427500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   6600966001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   7285874501                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59192209064                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59192209064                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1211526000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1211526000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  60403735064                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60403735064                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025368                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020136                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.818133                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.818133                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.439970                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.439970                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.097941                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.063075                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000714                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.015577                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.097941                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.063075                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           46                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        16681                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        35187                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           51921                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2935                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2935                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       128896                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        128896                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           46                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         16681                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        164083                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           180817                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           46                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        16681                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       164083                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          180817                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       280000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    682272500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1445683499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2130086999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    117833500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    117833500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5165552500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5165552500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       280000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    682272500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6611235999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7295639499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       280000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    682272500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6611235999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7295639499                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59192780564                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59192780564                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1212414000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1212414000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  60405194564                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60405194564                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025488                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020153                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.897828                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.897828                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.441029                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.441029                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.098091                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063032                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.098091                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063032                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40343.498754                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40348.194578                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40343.498754                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40348.194578                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47565                       # number of replacements
-system.iocache.tagsinuse                     0.200108                       # Cycle average of tags in use
+system.iocache.replacements                     47569                       # number of replacements
+system.iocache.tagsinuse                     0.199376                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47581                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47585                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              5000599162000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.200108                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.012507                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.012507                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          900                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              900                       # number of ReadReq misses
+system.iocache.warmup_cycle              5000598404000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.199376                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.012461                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.012461                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47620                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47620                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47620                       # number of overall misses
-system.iocache.overall_misses::total            47620                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135466932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    135466932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6926961160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6926961160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   7062428092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7062428092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   7062428092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7062428092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          900                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            900                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
+system.iocache.overall_misses::total            47624                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135906932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    135906932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6908833160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6908833160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   7044740092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7044740092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   7044740092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7044740092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47620                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47620                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47620                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47620                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 150518.813333                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 148265.435788                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 148308.023772                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 148308.023772                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 150339.526549                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 147877.422089                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 147924.157820                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 147924.157820                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs        269004                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   25                       # number of cycles access was blocked
@@ -348,22 +348,22 @@ system.iocache.fast_writes                          0                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          900                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          900                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47620                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47620                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47620                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47620                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88635000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     88635000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4497207944                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4497207944                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4585842944                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4585842944                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4585842944                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4585842944                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47624                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47624                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47624                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88867000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     88867000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4479079912                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4479079912                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4567946912                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4567946912                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4567946912                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4567946912                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 96300.775808                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 96300.775808                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 95916.909793                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 95916.909793                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -393,107 +393,107 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        472946175                       # number of cpu cycles simulated
+system.cpu.numCycles                        473223088                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 90027772                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           90027772                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1176455                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              84282590                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 81704922                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 90016360                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           90016360                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1178248                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              84343978                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 81707122                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           31264026                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      446943348                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    90027772                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           81704922                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     169792009                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5327046                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     167003                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles              104616235                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                37821                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         45804                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          481                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9365381                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                539972                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5058                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          310035010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.836765                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.376817                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           31356562                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      446929489                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    90016360                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           81707122                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     169790434                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5330018                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     171751                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles              104797996                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                37968                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         45006                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          453                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9363044                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                536807                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5287                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          310312997                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.834177                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.376352                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                140677603     45.37%     45.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1773611      0.57%     45.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72784877     23.48%     69.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   988899      0.32%     69.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1639325      0.53%     70.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3670845      1.18%     71.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1138945      0.37%     71.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1446155      0.47%     72.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85914750     27.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                140957479     45.42%     45.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1776597      0.57%     46.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72781994     23.45%     69.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   982988      0.32%     69.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1642902      0.53%     70.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3674853      1.18%     71.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1139478      0.37%     71.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1444103      0.47%     72.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 85912603     27.69%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            310035010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.190355                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.945019                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36438516                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100672732                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 164105371                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4706760                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4111631                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              876235114                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1005                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4111631                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 40855551                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                44279722                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       10981847                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 163785428                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46020831                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              872430616                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 10252                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               35253394                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3952381                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents         31994944                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1394146617                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2488353855                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2488353319                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               536                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1347546781                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 46599829                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             470336                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         478135                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  48126988                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             18909339                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10455877                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1294020                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1017517                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  865756561                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1721302                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 864328719                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            124616                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        26046990                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     53600910                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         205527                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     310035010                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.787842                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.396151                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            310312997                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.190220                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.944437                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36508708                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100881020                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 164105770                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4704672                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4112827                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              876214899                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   957                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4112827                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 40925858                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                44314017                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       11153757                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 163784094                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46022444                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              872421528                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 10519                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               35242822                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3962452                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         32001317                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1394162179                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2488413918                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2488413062                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               856                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1347546247                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 46615925                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             471039                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         478955                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  48145791                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             18923985                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10455746                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1291287                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1021115                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  865765672                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1722965                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 864313181                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            123185                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26037339                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     53671952                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         207307                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     310312997                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.785295                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.396376                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           102334281     33.01%     33.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23751530      7.66%     40.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            19011662      6.13%     46.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7830278      2.53%     49.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            80611792     26.00%     75.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3104970      1.00%     76.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72755101     23.47%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              522761      0.17%     99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              112635      0.04%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           102585339     33.06%     33.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23772488      7.66%     40.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            19036495      6.13%     46.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7825788      2.52%     49.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            80603332     25.97%     75.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3104423      1.00%     76.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72752969     23.45%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              520222      0.17%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              111941      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       310035010                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       310312997                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  164564      7.88%      7.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  164594      7.88%      7.88% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      7.88% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.88% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.88% # attempts to use FU when none available
@@ -522,12 +522,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.88% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.88% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.88% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1763434     84.48%     92.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                159280      7.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1764434     84.50%     92.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159044      7.62%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            297202      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             829439322     95.96%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            296261      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             829427794     95.96%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.00% # Type of FU issued
@@ -556,250 +556,248 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.00% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.00% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25154463      2.91%     98.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9437732      1.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25158656      2.91%     98.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9430470      1.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              864328719                       # Type of FU issued
-system.cpu.iq.rate                           1.827541                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2087278                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002415                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2041042185                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         893535851                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    853927067                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 224                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                246                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           54                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              866118699                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      96                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1579181                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              864313181                       # Type of FU issued
+system.cpu.iq.rate                           1.826439                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2088072                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002416                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2041288204                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         893536846                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    853917717                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 372                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                410                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           96                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              866104816                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     176                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1579729                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3618734                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        20083                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        12084                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2054359                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3631905                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        20141                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12168                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2053612                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7821519                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4487                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      7821470                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4399                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4111631                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                27910035                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1927143                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           867477863                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            297836                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              18909339                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10455877                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             883178                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 975186                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 15536                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          12084                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         697834                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       626380                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1324214                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             862437508                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24726867                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1891210                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4112827                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                27932530                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1927286                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           867488637                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            301587                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              18923985                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10455746                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             885039                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 975379                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15665                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12168                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         701708                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       624080                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1325788                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             862427395                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24732275                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1885785                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     33920253                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86495383                       # Number of branches executed
-system.cpu.iew.exec_stores                    9193386                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.823543                       # Inst execution rate
-system.cpu.iew.wb_sent                      861952908                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     853927121                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 669642895                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1918737755                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     33921373                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 86494176                       # Number of branches executed
+system.cpu.iew.exec_stores                    9189098                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.822454                       # Inst execution rate
+system.cpu.iew.wb_sent                      861944484                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     853917813                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 669630870                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918703675                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.805548                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.804472                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.349002                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      426515724                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        840516219                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        26857823                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1515773                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1181578                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    305938932                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.747333                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.861326                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      426513995                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        840512563                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        26872606                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1515656                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1183314                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    306215725                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.744838                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.861126                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    125006118     40.86%     40.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14720749      4.81%     45.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4254060      1.39%     47.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76641454     25.05%     72.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3896789      1.27%     73.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1794252      0.59%     73.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1101361      0.36%     74.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71996786     23.53%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6527363      2.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    125266635     40.91%     40.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14734551      4.81%     45.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4258737      1.39%     47.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     76646765     25.03%     72.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3892941      1.27%     73.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1792387      0.59%     74.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1104205      0.36%     74.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71994718     23.51%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6524786      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    305938932                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            426515724                       # Number of instructions committed
-system.cpu.commit.committedOps              840516219                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    306215725                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            426513995                       # Number of instructions committed
+system.cpu.commit.committedOps              840512563                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23692120                       # Number of memory references committed
-system.cpu.commit.loads                      15290602                       # Number of loads committed
-system.cpu.commit.membars                      781565                       # Number of memory barriers committed
-system.cpu.commit.branches                   85505775                       # Number of branches committed
+system.cpu.commit.refs                       23694211                       # Number of memory references committed
+system.cpu.commit.loads                      15292077                       # Number of loads committed
+system.cpu.commit.membars                      781571                       # Number of memory barriers committed
+system.cpu.commit.branches                   85505598                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768334838                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 768332766                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6527363                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6524786                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1166706140                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1738874776                       # The number of ROB writes
-system.cpu.timesIdled                         2996123                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       162911165                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9872855838                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   426515724                       # Number of Instructions Simulated
-system.cpu.committedOps                     840516219                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             426515724                       # Number of Instructions Simulated
-system.cpu.cpi                               1.108860                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.108860                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.901827                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.901827                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2163141042                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1362663536                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        54                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               281062978                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 403820                       # number of misc regfile writes
-system.cpu.icache.replacements                1070658                       # number of replacements
-system.cpu.icache.tagsinuse                510.425099                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8224431                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1071170                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.677989                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            56932899000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.425099                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996924                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996924                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      8224431                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8224431                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8224431                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8224431                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8224431                       # number of overall hits
-system.cpu.icache.overall_hits::total         8224431                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1140947                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1140947                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1140947                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1140947                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1140947                       # number of overall misses
-system.cpu.icache.overall_misses::total       1140947                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  18841256486                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  18841256486                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  18841256486                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  18841256486                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  18841256486                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  18841256486                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9365378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9365378                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9365378                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9365378                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9365378                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9365378                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121826                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.121826                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.121826                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.121826                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.121826                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.121826                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16513.700011                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16513.700011                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      3271992                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                   1166996622                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1738897212                       # The number of ROB writes
+system.cpu.timesIdled                         2997983                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       162910091                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9872594876                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   426513995                       # Number of Instructions Simulated
+system.cpu.committedOps                     840512563                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             426513995                       # Number of Instructions Simulated
+system.cpu.cpi                               1.109514                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.109514                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.901296                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.901296                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2163164515                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1362660599                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        96                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               281055752                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 403699                       # number of misc regfile writes
+system.cpu.icache.replacements                1072786                       # number of replacements
+system.cpu.icache.tagsinuse                510.225454                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8218240                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1073298                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.656997                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            56932893000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.225454                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996534                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996534                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      8218240                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8218240                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8218240                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8218240                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8218240                       # number of overall hits
+system.cpu.icache.overall_hits::total         8218240                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1144801                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1144801                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1144801                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1144801                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1144801                       # number of overall misses
+system.cpu.icache.overall_misses::total       1144801                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  18871083485                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  18871083485                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  18871083485                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  18871083485                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  18871083485                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  18871083485                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9363041                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9363041                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9363041                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9363041                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9363041                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9363041                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122268                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.122268                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.122268                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.122268                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.122268                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.122268                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16484.160553                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16484.160553                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      3261491                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               399                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               378                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  8200.481203                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8628.283069                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         1605                       # number of writebacks
-system.cpu.icache.writebacks::total              1605                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69655                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        69655                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        69655                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        69655                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        69655                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        69655                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1071292                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1071292                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1071292                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1071292                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1071292                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1071292                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14719464992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14719464992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14719464992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14719464992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14719464992                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14719464992                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114389                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114389                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114389                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114389                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69972                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        69972                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        69972                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        69972                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        69972                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        69972                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1074829                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1074829                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1074829                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1074829                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1074829                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1074829                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14733142991                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14733142991                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14733142991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14733142991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14733142991                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14733142991                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114795                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.114795                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.114795                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements        10504                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.031363                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          31807                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs        10516                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         3.024629                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5135227037000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.031363                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.376960                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.376960                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        31848                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        31848                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements        11223                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.037503                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          31260                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs        11237                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.781881                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5131387386000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.037503                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.377344                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.377344                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        31468                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        31468                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        31851                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        31851                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        31851                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        31851                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        11386                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        11386                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        11386                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        11386                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        11386                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        11386                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    182254500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    182254500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    182254500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    182254500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    182254500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    182254500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43234                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        43234                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        31471                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        31471                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        31471                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        31471                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        12107                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        12107                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        12107                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        12107                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        12107                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        12107                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    196957000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    196957000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    196957000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    196957000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    196957000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    196957000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43575                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        43575                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43237                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        43237                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43237                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        43237                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.263358                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.263358                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.263339                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.263339                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.263339                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.263339                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43578                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        43578                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43578                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        43578                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.277843                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.277843                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.277824                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.277824                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.277824                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.277824                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -808,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1641                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1641                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        11386                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        11386                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        11386                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        11386                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        11386                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        11386                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    147453030                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    147453030                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    147453030                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    147453030                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    147453030                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    147453030                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.263358                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.263358                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.263339                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.263339                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.263339                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.263339                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1700                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1700                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        12107                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        12107                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        12107                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        12107                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        12107                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        12107                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    159950045                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    159950045                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    159950045                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    159950045                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    159950045                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    159950045                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.277843                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.277843                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.277824                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.277824                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.277824                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.277824                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       117278                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       13.523999                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         136775                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       117293                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.166097                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5112876101000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.523999                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.845250                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.845250                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       136779                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       136779                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       136779                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       136779                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       136779                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       136779                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       118304                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       118304                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       118304                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       118304                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       118304                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       118304                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2123660000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2123660000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2123660000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   2123660000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2123660000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   2123660000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       255083                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       255083                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       255083                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       255083                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       255083                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       255083                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.463786                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.463786                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.463786                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.463786                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements       118986                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       13.873264                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         132191                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       119002                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.110830                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5112880781000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.873264                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.867079                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.867079                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       132191                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       132191                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       132191                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       132191                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       132191                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       132191                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       120057                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       120057                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       120057                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       120057                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       120057                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       120057                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2156991000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2156991000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2156991000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   2156991000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2156991000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   2156991000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       252248                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       252248                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       252248                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       252248                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       252248                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       252248                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.475948                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.475948                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.475948                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -888,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        37674                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        37674                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       118304                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       118304                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       118304                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total       118304                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       118304                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total       118304                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1766049009                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1766049009                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1766049009                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1766049009                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.463786                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.463786                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.463786                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.463786                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        34205                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        34205                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       120057                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       120057                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       120057                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       120057                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       120057                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       120057                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1794187508                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1794187508                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1794187508                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.475948                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.475948                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.475948                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1673136                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997556                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 19006106                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1673648                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.356095                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1672900                       # number of replacements
+system.cpu.dcache.tagsinuse                511.996980                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19011613                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1673412                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.360988                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               36854000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997556                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     10928708                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10928708                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8074811                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8074811                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19003519                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19003519                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19003519                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19003519                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2430538                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2430538                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       317333                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       317333                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2747871                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2747871                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2747871                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2747871                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  45186101000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  45186101000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10603069990                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10603069990                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55789170990                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55789170990                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55789170990                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55789170990                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13359246                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13359246                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8392144                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8392144                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21751390                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21751390                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21751390                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21751390                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181937                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.181937                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037813                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037813                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.126331                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.126331                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.126331                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.126331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20302.689242                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20302.689242                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     27875990                       # number of cycles access was blocked
+system.cpu.dcache.occ_blocks::cpu.data     511.996980                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     10933058                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10933058                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8074504                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8074504                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19007562                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19007562                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19007562                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19007562                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2431156                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2431156                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       318255                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       318255                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2749411                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2749411                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2749411                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2749411                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  45213675500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  45213675500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10676522982                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10676522982                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55890198482                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55890198482                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55890198482                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55890198482                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13364214                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13364214                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8392759                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8392759                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21756973                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21756973                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21756973                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21756973                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181915                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.181915                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037920                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037920                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.126369                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.126369                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.126369                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.126369                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18597.603568                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18597.603568                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33547.070689                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33547.070689                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20328.062440                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20328.062440                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20328.062440                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     26730982                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              4957                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              4911                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5623.560621                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5443.083282                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1572269                       # number of writebacks
-system.cpu.dcache.writebacks::total           1572269                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1049151                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1049151                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22726                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        22726                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1071877                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1071877                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1071877                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1071877                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381387                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1381387                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294607                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       294607                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1675994                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1675994                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1675994                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1675994                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23290713035                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23290713035                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9337845997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9337845997                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32628559032                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  32628559032                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32628559032                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  32628559032                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85207723000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85207723000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1386731000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1386731000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86594454000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  86594454000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103403                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103403                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035105                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035105                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077052                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.077052                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077052                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1571690                       # number of writebacks
+system.cpu.dcache.writebacks::total           1571690                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1049439                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1049439                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22786                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        22786                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1072225                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1072225                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1072225                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1072225                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381717                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1381717                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       295469                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       295469                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1677186                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1677186                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1677186                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1677186                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23302977034                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23302977034                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9408800483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9408800483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32711777517                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  32711777517                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32711777517                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  32711777517                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208357000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208357000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1386111000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1386111000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86594468000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  86594468000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103389                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103389                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035205                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035205                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077087                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077087                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077087                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077087                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index 7b9ea05e8..c9fc9d3a5 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -642,30 +642,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=32768
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=32768
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -706,30 +696,20 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=32768
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=32768
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.sequencer]
 type=RubySequencer
@@ -766,16 +746,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=4194304
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.pc]
 type=Pc
@@ -1020,7 +995,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1040,7 +1015,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1215,9 +1190,9 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=8
+width=64
 default=system.pc.pciconfig.pio
-master=system.physmem.port system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
+master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
 slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master
 
 [system.ruby]
@@ -1244,104 +1219,74 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl1
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.ext_links3]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links3.int_node
+int_node=system.ruby.network.topology.routers3
 latency=1
 link_id=3
 weight=1
 
-[system.ruby.network.topology.ext_links3.int_node]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.ext_links4]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dma_cntrl0
-int_node=system.ruby.network.topology.ext_links4.int_node
+int_node=system.ruby.network.topology.routers4
 latency=1
 link_id=4
 weight=1
 
-[system.ruby.network.topology.ext_links4.int_node]
-type=BasicRouter
-router_id=4
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers5
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=5
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=6
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers5
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -1349,8 +1294,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=7
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers5
 weight=1
 
 [system.ruby.network.topology.int_links3]
@@ -1358,8 +1303,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=8
-node_a=system.ruby.network.topology.ext_links3.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers3
+node_b=system.ruby.network.topology.routers5
 weight=1
 
 [system.ruby.network.topology.int_links4]
@@ -1367,10 +1312,34 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=9
-node_a=system.ruby.network.topology.ext_links4.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers4
+node_b=system.ruby.network.topology.routers5
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers4]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers5]
+type=BasicRouter
+router_id=5
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
index a4244c4ca..62578ab56 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
@@ -3,10 +3,8 @@ warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
 warn: Don't know what interrupt to clear for console.
 warn: instruction 'fxsave' unimplemented
-warn: x86 cpuid: unknown family 0x8086
 warn: instruction 'wbinvd' unimplemented
 warn: instruction 'wbinvd' unimplemented
-warn: x86 cpuid: unknown family 0x8086
 hack: Assuming logical destinations are 1 << id.
 warn: Tried to clear PCI interrupt 14
 warn: Unknown mouse command 0xe1.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index 00f64894a..d6cb455f2 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 22 2012 08:55:10
-gem5 started Jul 22 2012 08:55:16
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jun  4 2012 13:44:12
+gem5 started Jun  4 2012 17:11:29
+gem5 executing on zizzer
 command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5305568377500 because m5_exit instruction encountered
+Exiting @ tick 5304689685500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index 90df3051e..b7d143468 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,107 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.305568                       # Number of seconds simulated
-sim_ticks                                5305568377500                       # Number of ticks simulated
-final_tick                               5305568377500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.304690                       # Number of seconds simulated
+sim_ticks                                5304689685500                       # Number of ticks simulated
+final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 148548                       # Simulator instruction rate (inst/s)
-host_op_rate                                   304739                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5673062484                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 518516                       # Number of bytes of host memory used
-host_seconds                                   935.22                       # Real time elapsed on the host
-sim_insts                                   138925597                       # Number of instructions simulated
-sim_ops                                     284998538                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide        35160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       131880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        65368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        843619360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         40106316                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        91872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        42696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst        468873856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         53484588                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1406451096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    843619360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst    468873856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1312493216                       # Number of instructions bytes read from this memory
+host_inst_rate                                 163049                       # Simulator instruction rate (inst/s)
+host_op_rate                                   333085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6301127704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 481488                       # Number of bytes of host memory used
+host_seconds                                   841.86                       # Real time elapsed on the host
+sim_insts                                   137264752                       # Number of instructions simulated
+sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide        35144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       126800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        64416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        827772912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         39626426                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       100784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        45696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        470347440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         53905938                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1392025556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    827772912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    470347440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1298120352                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      32433610                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      35512400                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70937130                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide          811                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker        16485                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         8171                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst         105452420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           6721793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker        11484                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         5337                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst          58609232                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data           8980167                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             179805900                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data      32173132                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      35738580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70902832                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          809                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        15850                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         8052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         103471614                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6642662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        12598                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         5712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          58793430                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           9050935                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             178001662                       # Number of read requests responded to by this memory
 system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          4872539                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data          4951932                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              9871209                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         6627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker         24857                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         12321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           159006406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             7559287                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker         17316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8047                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            88373916                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            10080840                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               265089618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      159006406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       88373916                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          247380322                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       563767                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data          4837067                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          4982709                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9866514                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6625                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         23903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker         12143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           156045492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7470074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         18999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          8614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            88666344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10161940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               262414135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      156045492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       88666344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          244711836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563860                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            6113126                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            6693420                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               13370317                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       570394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker        24857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        12324                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          159006406                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13672414                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker        17316                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           88373916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           16774261                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              278459935                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+system.physmem.bw_write::cpu0.data            6065036                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            6737167                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13366066                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        23903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker        12146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          156045492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13535110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        18999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         8614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           88666344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           16899107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              275780201                       # Total bandwidth to/from this memory (bytes/s)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@@ -114,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu0.numCycles                     10611136755                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10608177450                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   90467113                       # Number of instructions committed
-system.cpu0.committedOps                    191744891                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            172320091                       # Number of integer alu accesses
+system.cpu0.committedInsts                   88690468                       # Number of instructions committed
+system.cpu0.committedOps                    187060545                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            168469813                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     18433408                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   172320091                       # number of integer instructions
+system.cpu0.num_conditional_control_insts     17923925                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   168469813                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          529438037                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         286410601                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          517963630                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         280483339                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     19683230                       # number of memory refs
-system.cpu0.num_load_insts                   14799913                       # Number of load instructions
-system.cpu0.num_store_insts                   4883317                       # Number of store instructions
-system.cpu0.num_idle_cycles              10087385086.886099                       # Number of idle cycles
-system.cpu0.num_busy_cycles              523751668.113901                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049359                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950641                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     19132508                       # number of memory refs
+system.cpu0.num_load_insts                   14284566                       # Number of load instructions
+system.cpu0.num_store_insts                   4847942                       # Number of store instructions
+system.cpu0.num_idle_cycles              10086452980.871330                       # Number of idle cycles
+system.cpu0.num_busy_cycles              521724469.128670                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049181                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950819                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.numCycles                     10608184676                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10609379371                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48458484                       # Number of instructions committed
-system.cpu1.committedOps                     93253647                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             88897203                       # Number of integer alu accesses
+system.cpu1.committedInsts                   48574284                       # Number of instructions committed
+system.cpu1.committedOps                     93351709                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             89110416                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8156142                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    88897203                       # number of integer instructions
+system.cpu1.num_conditional_control_insts      8197841                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    89110416                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          272264147                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         138280138                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          273178604                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         138760228                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14383325                       # number of memory refs
-system.cpu1.num_load_insts                    9129593                       # Number of load instructions
-system.cpu1.num_store_insts                   5253732                       # Number of store instructions
-system.cpu1.num_idle_cycles              10274264583.773684                       # Number of idle cycles
-system.cpu1.num_busy_cycles              333920092.226317                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031478                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968522                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14426742                       # number of memory refs
+system.cpu1.num_load_insts                    9181010                       # Number of load instructions
+system.cpu1.num_store_insts                   5245732                       # Number of store instructions
+system.cpu1.num_idle_cycles              10273661233.326063                       # Number of idle cycles
+system.cpu1.num_busy_cycles              335718137.673937                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031644                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968356                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 79d4aa555..d7217517d 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -507,7 +507,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
+cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -530,7 +530,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 19d21974e..2e50d7c5a 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 15:42:24
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 01:18:01
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 213265939500 because target called exit()
+Exiting @ tick 213305827500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index e448a6379..65ecf33d6 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.213266                       # Number of seconds simulated
-sim_ticks                                213265939500                       # Number of ticks simulated
-final_tick                               213265939500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.213306                       # Number of seconds simulated
+sim_ticks                                213305827500                       # Number of ticks simulated
+final_tick                               213305827500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 150954                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170051                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63253971                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238980                       # Number of bytes of host memory used
-host_seconds                                  3371.58                       # Real time elapsed on the host
+host_inst_rate                                 122434                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137922                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51312604                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243816                       # Number of bytes of host memory used
+host_seconds                                  4156.99                       # Real time elapsed on the host
 sim_insts                                   508955143                       # Number of instructions simulated
 sim_ops                                     573341703                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            218944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10016576                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10235520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       218944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          218944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6679616                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6679616                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3421                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             156509                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                159930                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          104369                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               104369                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1026624                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             46967537                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47994162                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1026624                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1026624                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          31320594                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               31320594                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          31320594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1026624                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            46967537                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               79314756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            218880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10018112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10236992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       218880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          218880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6680832                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6680832                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3420                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             156533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                159953                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          104388                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               104388                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1026132                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             46965955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                47992088                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1026132                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1026132                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          31320438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               31320438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          31320438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1026132                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            46965955                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               79312526                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,143 +77,143 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        426531880                       # number of cpu cycles simulated
+system.cpu.numCycles                        426611656                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                180717428                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          143299693                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            7745708                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              94822680                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 87599174                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                180727823                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          143302439                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            7746795                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              94842136                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 87606401                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 12446842                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              117258                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          120998369                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      797263404                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   180717428                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          100046016                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     177300353                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                41685655                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               95764916                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   19                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           750                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 114346660                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2503858                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          424958022                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.156047                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.022518                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 12449624                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              117248                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          121010673                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      797304667                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   180727823                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          100056025                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     177314401                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                41698826                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               95806477                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   17                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           633                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 114358410                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2503764                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          425037502                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.155810                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.022430                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                247670464     58.28%     58.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 14397332      3.39%     61.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 20689751      4.87%     66.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22947722      5.40%     71.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 21025298      4.95%     76.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13188609      3.10%     79.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13288793      3.13%     83.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 12167829      2.86%     85.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 59582224     14.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                247735901     58.29%     58.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 14398989      3.39%     61.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 20690991      4.87%     66.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22948184      5.40%     71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 21028166      4.95%     76.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13190111      3.10%     79.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 13289231      3.13%     83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 12171348      2.86%     85.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 59584581     14.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            424958022                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.423690                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.869177                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                133827033                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              89884158                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 165222726                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5205901                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               30818204                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             26548087                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 78411                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              873467434                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                311843                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               30818204                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                144286364                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8884116                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       66224882                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 159795223                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14949233                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              818684887                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1541                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2838925                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               8204276                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              192                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           966602186                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3574693177                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3574688542                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4635                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            425037502                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.423635                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.868924                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                133844968                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              89919956                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 165224759                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5218013                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               30829806                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             26552808                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 78494                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              873544954                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                311862                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               30829806                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                144308291                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8889002                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       66226963                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 159805436                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14978004                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              818752285                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1493                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2838539                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8233022                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              166                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           966651195                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3575004515                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3574999805                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              4710                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             672200163                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                294402023                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            5323897                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        5323528                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  70458787                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            172688867                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            75177672                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          27536611                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         15452316                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  763600148                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             6775253                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 672568642                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1541380                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       194741611                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    494202077                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        3054137                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     424958022                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.582671                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.715070                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                294451032                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            5324262                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        5323899                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  70506892                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172716678                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            75192368                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          27652992                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         15476560                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  763674623                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             6775753                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 672581286                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1543643                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       194823037                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    494499430                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        3054637                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     425037502                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.582405                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.714766                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           161198015     37.93%     37.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            79163376     18.63%     56.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            71154341     16.74%     73.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            52720722     12.41%     85.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            30628875      7.21%     92.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16032619      3.77%     96.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9417662      2.22%     98.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3389445      0.80%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1252967      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           161217436     37.93%     37.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            79193919     18.63%     56.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            71219740     16.76%     73.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            52703176     12.40%     85.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            30630317      7.21%     92.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16016984      3.77%     96.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9411904      2.21%     98.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3391461      0.80%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1252565      0.29%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       424958022                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       425037502                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  469414      4.82%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6674941     68.55%     73.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2592845     26.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  468985      4.81%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6682386     68.55%     73.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2596899     26.64%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             451773589     67.17%     67.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               385931      0.06%     67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             451788730     67.17%     67.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               385834      0.06%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 236      0.00%     67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 242      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.23% # Type of FU issued
@@ -239,86 +239,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.23% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            155280491     23.09%     90.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            65128392      9.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            155276883     23.09%     90.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            65129594      9.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              672568642                       # Type of FU issued
-system.cpu.iq.rate                           1.576831                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     9737200                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014478                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1781373379                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         965920498                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    652179695                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 507                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                988                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              672581286                       # Type of FU issued
+system.cpu.iq.rate                           1.576566                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9748270                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014494                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1781491468                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         966076983                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    652193699                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 519                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                994                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              682305587                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     255                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          8455481                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              682329295                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     261                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          8459367                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     45915828                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        43410                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       808399                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     17573711                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     45943639                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        43480                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       808541                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     17588407                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19491                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        19485                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked          1190                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               30818204                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 4164130                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                269264                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           776544403                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1215899                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             172688867                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             75177672                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            5286544                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 138154                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  7994                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         808399                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4709852                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      6436476                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11146328                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             662608710                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             151741633                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9959932                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               30829806                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4164559                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                269371                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           776620659                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1214502                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             172716678                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             75192368                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            5287034                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 138183                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  8014                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         808541                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4710218                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6437306                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11147524                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             662618807                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             151738432                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9962479                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       6169002                       # number of nop insts executed
-system.cpu.iew.exec_refs                    215464084                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                137322673                       # Number of branches executed
-system.cpu.iew.exec_stores                   63722451                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.553480                       # Inst execution rate
-system.cpu.iew.wb_sent                      657371500                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     652179711                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 375708324                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 644520569                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       6170283                       # number of nop insts executed
+system.cpu.iew.exec_refs                    215459970                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                137327241                       # Number of branches executed
+system.cpu.iew.exec_stores                   63721538                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.553213                       # Inst execution rate
+system.cpu.iew.wb_sent                      657384625                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     652193715                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 375712620                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 644546393                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.529029                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.582927                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.528776                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.582910                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      510299027                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        574685587                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       201878689                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       201955385                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         3721116                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9919991                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    394139819                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.458075                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.151494                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9921280                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    394207697                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.457824                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.150931                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    179649221     45.58%     45.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    103014328     26.14%     71.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     36282541      9.21%     80.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     18903013      4.80%     85.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     16466891      4.18%     89.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8169845      2.07%     91.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      6904317      1.75%     93.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3742857      0.95%     94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     21006806      5.33%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    179674322     45.58%     45.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    103038794     26.14%     71.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     36295508      9.21%     80.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     18900800      4.79%     85.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     16480626      4.18%     89.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8181222      2.08%     91.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6907237      1.75%     93.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3752163      0.95%     94.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     20977025      5.32%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    394139819                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    394207697                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            510299027                       # Number of instructions committed
 system.cpu.commit.committedOps              574685587                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -329,69 +329,69 @@ system.cpu.commit.branches                  120192224                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 473701629                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              21006806                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              20977025                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1149690151                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1584089992                       # The number of ROB writes
-system.cpu.timesIdled                           76999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1573858                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   1149864506                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1584255068                       # The number of ROB writes
+system.cpu.timesIdled                           77013                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1574154                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   508955143                       # Number of Instructions Simulated
 system.cpu.committedOps                     573341703                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             508955143                       # Number of Instructions Simulated
-system.cpu.cpi                               0.838054                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.838054                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.193241                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.193241                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3092178369                       # number of integer regfile reads
-system.cpu.int_regfile_writes               760489659                       # number of integer regfile writes
+system.cpu.cpi                               0.838211                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.838211                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.193017                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.193017                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3092210365                       # number of integer regfile reads
+system.cpu.int_regfile_writes               760501959                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1025175182                       # number of misc regfile reads
+system.cpu.misc_regfile_reads              1025217817                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                4464052                       # number of misc regfile writes
-system.cpu.icache.replacements                  15943                       # number of replacements
-system.cpu.icache.tagsinuse               1097.454054                       # Cycle average of tags in use
-system.cpu.icache.total_refs                114326971                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  17802                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                6422.141950                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                  15942                       # number of replacements
+system.cpu.icache.tagsinuse               1098.022149                       # Cycle average of tags in use
+system.cpu.icache.total_refs                114338741                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  17803                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                6422.442341                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1097.454054                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.535866                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.535866                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    114326971                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       114326971                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     114326971                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        114326971                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    114326971                       # number of overall hits
-system.cpu.icache.overall_hits::total       114326971                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19689                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19689                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19689                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19689                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19689                       # number of overall misses
-system.cpu.icache.overall_misses::total         19689                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    281738500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    281738500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    281738500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    281738500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    281738500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    281738500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    114346660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    114346660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    114346660                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    114346660                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    114346660                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    114346660                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1098.022149                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.536144                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.536144                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    114338741                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       114338741                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     114338741                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        114338741                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    114338741                       # number of overall hits
+system.cpu.icache.overall_hits::total       114338741                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19669                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19669                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19669                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19669                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19669                       # number of overall misses
+system.cpu.icache.overall_misses::total         19669                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    281943000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    281943000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    281943000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    281943000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    281943000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    281943000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    114358410                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    114358410                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    114358410                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    114358410                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    114358410                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    114358410                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000172                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000172                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000172                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000172                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000172                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000172                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.436741                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14309.436741                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.436741                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14309.436741                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.436741                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14309.436741                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14334.384056                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14334.384056                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14334.384056                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14334.384056                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14334.384056                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14334.384056                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,112 +400,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
-system.cpu.icache.writebacks::total                 1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1829                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1829                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1829                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1829                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1829                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1829                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17860                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        17860                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        17860                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        17860                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        17860                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        17860                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    184743000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    184743000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    184743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    184743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    184743000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    184743000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1810                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1810                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1810                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1810                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1810                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1810                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17859                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        17859                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        17859                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        17859                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        17859                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        17859                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    184851000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    184851000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    184851000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    184851000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    184851000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    184851000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000156                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000156                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10343.952968                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 10343.952968                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 10343.952968                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10350.579540                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10350.579540                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10350.579540                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10350.579540                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10350.579540                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10350.579540                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1188340                       # number of replacements
-system.cpu.dcache.tagsinuse               4054.521086                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                194732293                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1192436                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 163.306285                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1188372                       # number of replacements
+system.cpu.dcache.tagsinuse               4054.528843                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                194724251                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1192468                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.295158                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             4858281000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4054.521086                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.989873                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.989873                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    137583731                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       137583731                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     52683552                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       52683552                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      2232862                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      2232862                       # number of LoadLockedReq hits
+system.cpu.dcache.occ_blocks::cpu.data    4054.528843                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.989875                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.989875                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    137575577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       137575577                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     52683646                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       52683646                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      2232872                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      2232872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      2232025                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      2232025                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     190267283                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        190267283                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    190267283                       # number of overall hits
-system.cpu.dcache.overall_hits::total       190267283                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1266916                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1266916                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1555754                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1555754                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     190259223                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        190259223                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    190259223                       # number of overall hits
+system.cpu.dcache.overall_hits::total       190259223                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1266823                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1266823                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1555660                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1555660                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2822670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2822670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2822670                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2822670                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  15542571000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  15542571000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  33103572500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  33103572500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      2822483                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2822483                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2822483                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2822483                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  15537538000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  15537538000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33101884500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33101884500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       516500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       516500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  48646143500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  48646143500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  48646143500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  48646143500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    138850647                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    138850647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  48639422500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  48639422500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  48639422500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  48639422500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    138842400                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    138842400                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2232903                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      2232903                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2232913                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      2232913                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232025                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      2232025                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    193089953                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    193089953                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    193089953                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    193089953                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    193081706                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    193081706                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    193081706                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    193081706                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009124                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.009124                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028683                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.028683                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028681                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.028681                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000018                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000018                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.014618                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.014618                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.014618                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.014618                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12268.035923                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12268.035923                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.153551                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.153551                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12264.963614                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12264.963614                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.354203                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.354203                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17234.088115                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17234.088115                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17234.088115                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17234.088115                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17232.848701                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17232.848701                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17232.848701                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17232.848701                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      3299000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -514,142 +512,142 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets  5901.610018                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1102764                       # number of writebacks
-system.cpu.dcache.writebacks::total           1102764                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       422570                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       422570                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1207611                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1207611                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      1102743                       # number of writebacks
+system.cpu.dcache.writebacks::total           1102743                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       422432                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       422432                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1207529                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1207529                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           41                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           41                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1630181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1630181                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1630181                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1630181                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       844346                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       844346                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348143                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       348143                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1192489                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1192489                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1192489                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1192489                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4793812500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4793812500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4284005501                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4284005501                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9077818001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9077818001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9077818001                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   9077818001                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006081                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006081                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006419                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006419                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data      1629961                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1629961                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1629961                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1629961                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       844391                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       844391                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348131                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       348131                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1192522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1192522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1192522                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1192522                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4793957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4793957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4284082001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4284082001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9078039001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9078039001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9078039001                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9078039001                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006082                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006082                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006418                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006418                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006176                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006176                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  5677.545106                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  5677.545106                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.304145                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.304145                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7612.496217                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7612.496217                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7612.496217                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7612.496217                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  5677.413663                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  5677.413663                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.948051                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.948051                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7612.470882                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  7612.470882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7612.470882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  7612.470882                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                128738                       # number of replacements
-system.cpu.l2cache.tagsinuse             26549.866286                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1724393                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                159968                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 10.779612                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                128760                       # number of replacements
+system.cpu.l2cache.tagsinuse             26550.688656                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1724027                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                159983                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 10.776314                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          109550112000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 22721.325025                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    308.211644                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   3520.329617                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.693400                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.009406                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.107432                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.810238                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        14375                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       787281                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         801656                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1102765                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1102765                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           44                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           44                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       248622                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       248622                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        14375                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1035903                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1050278                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        14375                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1035903                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1050278                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3428                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        53041                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        56469                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 22719.838493                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    309.354854                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   3521.495310                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.693354                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.009441                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.107468                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.810263                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        14376                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       787309                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         801685                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1102743                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1102743                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           48                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           48                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       248604                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       248604                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        14376                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1035913                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1050289                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        14376                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1035913                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1050289                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3427                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        53062                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        56489                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       103489                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       103489                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3428                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       156530                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        159958                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3428                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       156530                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       159958                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121134500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1832266000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1953400500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3547601500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3547601500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    121134500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   5379867500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   5501002000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    121134500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   5379867500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   5501002000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data       103493                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       103493                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3427                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       156555                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        159982                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3427                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       156555                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       159982                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121113500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1832817500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1953931000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3547748000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3547748000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    121113500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   5380565500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   5501679000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    121113500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   5380565500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   5501679000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        17803                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       840322                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       858125                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1102765                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1102765                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           50                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           50                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       352111                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       352111                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       840371                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       858174                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1102743                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1102743                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           54                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           54                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       352097                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       352097                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        17803                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1192433                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1210236                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1192468                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1210271                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        17803                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1192433                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1210236                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.063120                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.065805                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.120000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.120000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.293910                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.293910                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.131269                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.132171                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.131269                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.132171                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35336.785298                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34544.333629                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34592.440100                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34279.986279                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34279.986279                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35336.785298                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.561745                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34390.289951                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35336.785298                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.561745                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34390.289951                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data      1192468                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1210271                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192496                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.063141                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.065825                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.111111                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.111111                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.293933                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.293933                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192496                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.131287                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.132187                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192496                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.131287                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.132187                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35340.968777                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34541.055746                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34589.583813                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34280.076913                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34280.076913                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35340.968777                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34368.531826                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34389.362553                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35340.968777                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34368.531826                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34389.362553                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -658,69 +656,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       104369                       # number of writebacks
-system.cpu.l2cache.writebacks::total           104369                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       104388                       # number of writebacks
+system.cpu.l2cache.writebacks::total           104388                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            7                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           20                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           28                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            7                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           28                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            7                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3421                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        53021                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        56442                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           28                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3420                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        53041                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        56461                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103489                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       103489                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3421                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       156510                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       159931                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3421                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       156510                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       159931                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110230000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1664605500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1774835500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103493                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       103493                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       156534                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       159954                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3420                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       156534                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       159954                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110207000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1665041000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1775248000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       186000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       186000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3213112500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3213112500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110230000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4877718000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   4987948000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110230000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4877718000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   4987948000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.063096                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.065774                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.120000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.120000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.293910                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.293910                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.131253                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.132149                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.131253                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.132149                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31395.211331                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31445.297828                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3213249000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3213249000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110207000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4878290000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4988497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110207000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4878290000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   4988497000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.192102                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.063116                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.065792                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.111111                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.293933                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.293933                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.192102                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.131269                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.132164                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.192102                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.131269                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.132164                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32224.269006                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31391.583869                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31442.021927                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.864990                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.864990                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.535749                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31188.124879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.535749                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31188.124879                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.983922                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.983922                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32224.269006                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31164.411566                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31187.072533                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32224.269006                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31164.411566                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31187.072533                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 9aac7b043..e88ab98aa 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -510,7 +510,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -533,7 +533,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 96a3d5c32..ea9092f76 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 13:33:28
+gem5 compiled Jul 26 2012 21:30:36
+gem5 started Jul 26 2012 23:13:36
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -80,4 +80,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 460577560500 because target called exit()
+Exiting @ tick 460506550000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 96eed0126..ba1f3f77b 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,172 +1,172 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.460578                       # Number of seconds simulated
-sim_ticks                                460577560500                       # Number of ticks simulated
-final_tick                               460577560500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.460507                       # Number of seconds simulated
+sim_ticks                                460506550000                       # Number of ticks simulated
+final_tick                               460506550000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104932                       # Simulator instruction rate (inst/s)
-host_op_rate                                   194032                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               58448222                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266596                       # Number of bytes of host memory used
-host_seconds                                  7880.10                       # Real time elapsed on the host
+host_inst_rate                                  78127                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144467                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43510964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271484                       # Number of bytes of host memory used
+host_seconds                                 10583.69                       # Real time elapsed on the host
 sim_insts                                   826877144                       # Number of instructions simulated
 sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            222400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          27604032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27826432                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       222400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          222400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     20791104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          20791104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3475                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             431313                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                434788                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          324861                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               324861                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               482872                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             59933515                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                60416387                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          482872                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             482872                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45141374                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45141374                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45141374                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              482872                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            59933515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              105557761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            221568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          27602688                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27824256                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       221568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          221568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     20791168                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          20791168                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             431292                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                434754                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          324862                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               324862                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               481140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             59939838                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                60420978                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          481140                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             481140                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45148474                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45148474                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45148474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              481140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            59939838                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              105569452                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        921155122                       # number of cpu cycles simulated
+system.cpu.numCycles                        921013101                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                225826893                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          225826893                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           14312665                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             160782597                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                155982448                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                225814140                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          225814140                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           14312639                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             160732187                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                155963049                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          191746261                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1263371603                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225826893                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          155982448                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     392161652                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                98608350                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              239363044                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                24915                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        235054                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 183579479                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3670479                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          907575951                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.580457                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.385202                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          191714211                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1263294933                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225814140                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155963049                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     392136096                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                98589209                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              239295269                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                25132                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        236819                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 183551766                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3669107                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          907433762                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.580701                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.385285                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                519878601     57.28%     57.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25999906      2.86%     60.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 29091750      3.21%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 30316480      3.34%     66.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 19610375      2.16%     68.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 25620095      2.82%     71.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 32648944      3.60%     75.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30886362      3.40%     78.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                193523438     21.32%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                519759842     57.28%     57.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 26004641      2.87%     60.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 29087197      3.21%     63.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 30312943      3.34%     66.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 19607781      2.16%     68.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 25619101      2.82%     71.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32643698      3.60%     75.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 30879699      3.40%     78.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                193518860     21.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            907575951                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.245156                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.371508                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                253842060                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             190511569                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 329127835                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50049462                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               84045025                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2290915196                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total            907433762                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.245180                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.371636                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                253860681                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             190389456                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 329095586                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50061804                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               84026235                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2290781397                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                     2                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               84045025                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                290488035                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                45203385                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          15283                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 340026605                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             147797618                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2240907588                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2049                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24533767                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             107236940                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            12284                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2887565810                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6495003002                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       6494129328                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            873674                       # Number of floating rename lookups
+system.cpu.rename.SquashCycles               84026235                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                290493220                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                45042707                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15282                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 340016370                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             147839948                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2240790840                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1987                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24419621                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             107426362                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            12159                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2887400396                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6494628948                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6493753174                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            875774                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1993077484                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                894488326                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1298                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1285                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 351684544                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            540282589                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           217467537                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         211757951                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         61365379                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2143556526                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               68297                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1846659599                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1592599                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       612964134                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1231726867                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          67744                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     907575951                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.034716                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.801175                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                894322912                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1296                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1278                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 351952477                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            540247389                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           217453734                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         211358657                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         61297047                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2143407595                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               68408                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1846659650                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1592160                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       612815347                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1231279567                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          67855                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     907433762                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.035035                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.801518                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           248881296     27.42%     27.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           159283558     17.55%     44.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           154019271     16.97%     61.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           148934495     16.41%     78.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            98823398     10.89%     89.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            59633911      6.57%     95.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            27979654      3.08%     98.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             8970001      0.99%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1050367      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           248935467     27.43%     27.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           159182837     17.54%     44.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           153661987     16.93%     61.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149232137     16.45%     78.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            98738940     10.88%     89.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            59680898      6.58%     95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            27969436      3.08%     98.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8976918      0.99%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1055142      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       907575951                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       907433762                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2635862     18.39%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8471298     59.09%     77.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3228137     22.52%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2635361     18.49%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8379879     58.81%     77.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3234007     22.70%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2716270      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1219519641     66.04%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2716087      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1219498090     66.04%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.19% # Type of FU issued
@@ -195,86 +195,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.19% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            447028129     24.21%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           177395559      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            447052191     24.21%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           177393282      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1846659599                       # Type of FU issued
-system.cpu.iq.rate                           2.004722                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    14335297                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007763                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4616815245                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2756549096                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1806310045                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                7800                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             300622                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          277                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1858275871                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    2755                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        168023437                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1846659650                       # Type of FU issued
+system.cpu.iq.rate                           2.005031                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    14249247                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007716                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4616586705                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2756248953                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1806266388                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                7764                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             302326                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          267                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1858190079                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    2731                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        168174825                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    156180429                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       430384                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       272150                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     68307598                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    156145229                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       432412                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       271180                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     68293794                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7189                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads         7298                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               84045025                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6572333                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1289879                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2143624823                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2858157                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             540282589                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            217467783                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5279                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 972146                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 66800                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         272150                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10086391                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5256955                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             15343346                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1818812244                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             438622961                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          27847355                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               84026235                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6572859                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1284585                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2143476003                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2866964                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             540247389                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            217453979                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5268                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 966767                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 66701                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         271180                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10086388                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5256785                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             15343173                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1818783281                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             438633483                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          27876369                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    610455243                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                170879995                       # Number of branches executed
-system.cpu.iew.exec_stores                  171832282                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.974491                       # Inst execution rate
-system.cpu.iew.wb_sent                     1813575376                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1806310322                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1378798297                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2933608967                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    610463331                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                170879553                       # Number of branches executed
+system.cpu.iew.exec_stores                  171829848                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.974764                       # Inst execution rate
+system.cpu.iew.wb_sent                     1813538943                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1806266655                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1378870906                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2933493121                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.960919                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.470001                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.961174                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.470044                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       614662287                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       614512471                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14337681                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    823530926                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.856626                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.319528                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14337883                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    823407527                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.856904                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.319659                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    305238213     37.06%     37.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    205541162     24.96%     62.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     74423413      9.04%     71.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     96471007     11.71%     82.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29999240      3.64%     86.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28772955      3.49%     89.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     15805357      1.92%     91.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11742762      1.43%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     55536817      6.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    305105182     37.05%     37.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    205650111     24.98%     62.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     74228668      9.01%     71.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     96597559     11.73%     82.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29968597      3.64%     86.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28751826      3.49%     89.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15821579      1.92%     91.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11746400      1.43%     93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     55537605      6.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    823530926                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    823407527                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -285,69 +285,69 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              55536817                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              55537605                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2911645152                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4371462099                       # The number of ROB writes
-system.cpu.timesIdled                          309415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13579171                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2911371149                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4371143864                       # The number of ROB writes
+system.cpu.timesIdled                          309440                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13579339                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
-system.cpu.cpi                               1.114017                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.114017                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.897652                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.897652                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               4004251902                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2286361140                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       274                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        3                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1001934144                       # number of misc regfile reads
-system.cpu.icache.replacements                   5528                       # number of replacements
-system.cpu.icache.tagsinuse               1043.833365                       # Cycle average of tags in use
-system.cpu.icache.total_refs                183339964                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7144                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25663.488802                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.113845                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.113845                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.897791                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.897791                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4004246874                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2286313998                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       266                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1001920728                       # number of misc regfile reads
+system.cpu.icache.replacements                   5588                       # number of replacements
+system.cpu.icache.tagsinuse               1044.044381                       # Cycle average of tags in use
+system.cpu.icache.total_refs                183312403                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7204                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               25445.919350                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1043.833365                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.509684                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.509684                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    183356988                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       183356988                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     183356988                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        183356988                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    183356988                       # number of overall hits
-system.cpu.icache.overall_hits::total       183356988                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       222491                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        222491                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       222491                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         222491                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       222491                       # number of overall misses
-system.cpu.icache.overall_misses::total        222491                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1555664000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1555664000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1555664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1555664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1555664000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1555664000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    183579479                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    183579479                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    183579479                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    183579479                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    183579479                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    183579479                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1044.044381                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.509787                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.509787                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    183329342                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       183329342                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     183329342                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        183329342                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    183329342                       # number of overall hits
+system.cpu.icache.overall_hits::total       183329342                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       222424                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        222424                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       222424                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         222424                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       222424                       # number of overall misses
+system.cpu.icache.overall_misses::total        222424                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1554709500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1554709500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1554709500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1554709500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1554709500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1554709500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    183551766                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    183551766                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    183551766                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    183551766                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    183551766                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    183551766                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001212                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001212                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001212                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.001212                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001212                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001212                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6992.031138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6992.031138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6992.031138                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6992.031138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6992.031138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6992.031138                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6989.845970                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6989.845970                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6989.845970                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6989.845970                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6989.845970                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6989.845970                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -356,96 +356,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
-system.cpu.icache.writebacks::total                 8                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1714                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1714                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1714                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1714                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1714                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1714                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       220777                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       220777                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       220777                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       220777                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       220777                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       220777                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    807311500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    807311500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    807311500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    807311500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    807311500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    807311500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1671                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1671                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1671                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1671                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1671                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1671                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       220753                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       220753                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       220753                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       220753                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       220753                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       220753                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    807012500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    807012500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    807012500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    807012500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    807012500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    807012500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001203                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001203                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001203                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3656.682988                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3656.682988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3656.682988                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3655.726083                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3655.726083                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3655.726083                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2526932                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.002869                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                415155555                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2531028                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 164.026457                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                2526911                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.001481                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                415013959                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2531007                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.971873                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             2119650000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.002869                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data    4087.001481                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997803                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997803                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    266306304                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       266306304                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148172784                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148172784                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     414479088                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414479088                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414479088                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414479088                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2652001                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2652001                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       987417                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       987417                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3639418                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3639418                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3639418                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3639418                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36687997500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36687997500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18991122500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18991122500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55679120000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55679120000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55679120000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55679120000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    268958305                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    268958305                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::cpu.data    266164816                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       266164816                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148172858                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148172858                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     414337674                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        414337674                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    414337674                       # number of overall hits
+system.cpu.dcache.overall_hits::total       414337674                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2652510                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2652510                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       987343                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       987343                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3639853                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3639853                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3639853                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3639853                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36720929000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36720929000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18986429000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18986429000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55707358000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55707358000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55707358000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55707358000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    268817326                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    268817326                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418118506                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418118506                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418118506                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418118506                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009860                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.009860                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006620                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006620                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008704                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008704                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008704                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008704                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13834.081322                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13834.081322                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19233.133013                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 19233.133013                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15298.907682                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15298.907682                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15298.907682                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15298.907682                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    417977527                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    417977527                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    417977527                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    417977527                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009867                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009867                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006619                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006619                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008708                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008708                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008708                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008708                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13843.841871                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13843.841871                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19229.820842                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 19229.820842                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15304.837311                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15304.837311                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15304.837311                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15304.837311                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -454,144 +452,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2302590                       # number of writebacks
-system.cpu.dcache.writebacks::total           2302590                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       891786                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       891786                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3028                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         3028                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       894814                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       894814                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       894814                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       894814                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760215                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1760215                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       984389                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       984389                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2744604                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2744604                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2744604                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2744604                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12497957644                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12497957644                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15832587002                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  15832587002                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28330544646                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28330544646                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28330544646                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28330544646                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006545                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006545                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006600                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006600                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006564                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006564                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006564                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006564                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7100.244938                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7100.244938                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.669161                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.669161                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10322.270406                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10322.270406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10322.270406                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10322.270406                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2302631                       # number of writebacks
+system.cpu.dcache.writebacks::total           2302631                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       892307                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       892307                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3035                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3035                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       895342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       895342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       895342                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       895342                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760203                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1760203                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       984308                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       984308                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2744511                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2744511                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2744511                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2744511                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12496937149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12496937149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15830652502                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  15830652502                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28327589651                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28327589651                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28327589651                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28327589651                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006548                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006548                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006599                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006599                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006566                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006566                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7099.713584                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7099.713584                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.027367                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.027367                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10321.543492                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10321.543492                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10321.543492                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10321.543492                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                408624                       # number of replacements
-system.cpu.l2cache.tagsinuse             29310.882366                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3608909                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                440968                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  8.184061                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                408577                       # number of replacements
+system.cpu.l2cache.tagsinuse             29310.101870                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3608876                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                440919                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  8.184896                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          220647003000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21083.148834                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    149.403214                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   8078.330317                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.643407                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.004559                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.246531                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.894497                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3622                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1537243                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1540865                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2302598                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2302598                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1280                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1280                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       562350                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       562350                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3622                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2099593                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2103215                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3622                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2099593                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2103215                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3475                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       222140                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       225615                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       212287                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       212287                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       209207                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       209207                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3475                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       431347                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        434822                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3475                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       431347                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       434822                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121950500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7624838921                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   7746789421                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10608500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     10608500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7167281000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7167281000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    121950500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  14792119921                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14914070421                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    121950500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  14792119921                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14914070421                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7097                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1759383                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1766480                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2302598                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2302598                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       213567                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       213567                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771557                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771557                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7097                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2530940                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2538037                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7097                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2530940                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2538037                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.489644                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126260                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.127720                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.994007                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.994007                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271149                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.271149                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.489644                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.170430                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.171322                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.489644                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.170430                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.171322                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35093.669065                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.475200                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.322589                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    49.972443                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    49.972443                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34259.279087                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34259.279087                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35093.669065                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.854525                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34299.254456                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35093.669065                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.854525                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34299.254456                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 21083.038182                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    149.770059                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   8077.293628                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.643403                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.004571                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.246499                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.894473                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3685                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1537271                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1540956                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2302631                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2302631                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1259                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1259                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       562411                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       562411                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3685                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2099682                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2103367                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3685                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2099682                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2103367                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3462                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       222130                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       225592                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       212243                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       212243                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       209197                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       209197                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3462                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       431327                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        434789                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3462                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       431327                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       434789                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121473500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7624503923                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   7745977423                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10569500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     10569500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7166790000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7166790000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    121473500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14791293923                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  14912767423                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    121473500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14791293923                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14912767423                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7147                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1759401                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1766548                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2302631                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2302631                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       213502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       213502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771608                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771608                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7147                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2531009                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2538156                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7147                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2531009                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2538156                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.484399                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126253                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.127702                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.994103                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.994103                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.271118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.484399                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.170417                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.171301                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.484399                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.170417                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.171301                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35087.666089                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.512326                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.223904                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    49.799051                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    49.799051                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.569674                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.569674                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35087.666089                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.529619                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34298.860880                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35087.666089                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.529619                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34298.860880                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -600,60 +598,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       324861                       # number of writebacks
-system.cpu.l2cache.writebacks::total           324861                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3475                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222140                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       225615                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       212287                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       212287                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209207                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       209207                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3475                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       431347                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       434822                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3475                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       431347                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       434822                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110937500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6934880499                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7045817999                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6582250000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6582250000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6487010500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6487010500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13421890999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13532828499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110937500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13421890999                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13532828499                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126260                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127720                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.994007                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.994007                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271149                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271149                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170430                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.171322                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.171322                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.513095                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.386340                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.373447                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.373447                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.616858                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.616858                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.226609                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.685832                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.226609                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.685832                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       324862                       # number of writebacks
+system.cpu.l2cache.writebacks::total           324862                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3462                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222130                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       225592                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       212243                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       212243                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209197                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       209197                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3462                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       431327                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       434789                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3462                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       431327                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       434789                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110501000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6934646999                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7045147999                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6580894500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6580894500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6486675500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6486675500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13421322499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13531823499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110501000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13421322499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13531823499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126253                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127702                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.994103                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.994103                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271118                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271118                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170417                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.171301                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170417                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.171301                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.867325                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.600336                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.414817                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.414817                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.497717                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.497717                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.351397                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.736543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.351397                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.736543                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 08fd1ccfb..9a2e4ebac 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -287,7 +287,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -349,9 +349,9 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
@@ -406,7 +406,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 86d337feb..9d0955474 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:04
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 21:40:04
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 046013e55..98f92d27e 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4061827                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4061823                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                           120292600618                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301032                       # Number of bytes of host memory used
-host_seconds                                    15.55                       # Real time elapsed on the host
+host_inst_rate                                3051606                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3051604                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            90374561583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305448                       # Number of bytes of host memory used
+host_seconds                                    20.70                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst           761216                       # Number of bytes read from this memory
@@ -50,9 +50,9 @@ system.physmem.bw_total::cpu1.data             357514                       # To
 system.physmem.bw_total::total               42102084                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                       1000626                       # number of replacements
 system.l2c.tagsinuse                     65381.922680                       # Cycle average of tags in use
-system.l2c.total_refs                         2464692                       # Total number of references to valid blocks.
+system.l2c.total_refs                         2464737                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                       1065768                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.312597                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.312639                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                     838081000                       # Cycle when the warmup percentage was hit.
 system.l2c.occ_blocks::writebacks        56158.702580                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu0.inst          4894.236968                       # Average occupied blocks per requestor
@@ -66,31 +66,31 @@ system.l2c.occ_percent::cpu1.inst            0.002661                       # Av
 system.l2c.occ_percent::cpu1.data            0.000305                       # Average percentage of cache occupancy
 system.l2c.occ_percent::total                0.997649                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.inst             873086                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             763047                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             763077                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             101896                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              36724                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1774753                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          816766                       # number of Writeback hits
-system.l2c.Writeback_hits::total               816766                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             133                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              36                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 169                       # number of UpgradeReq hits
+system.l2c.ReadReq_hits::cpu1.data              36734                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1774793                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          816653                       # number of Writeback hits
+system.l2c.Writeback_hits::total               816653                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             135                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              37                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 172                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                23                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           166157                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            14260                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               180417                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           166234                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            14285                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               180519                       # number of ReadExReq hits
 system.l2c.demand_hits::cpu0.inst              873086                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              929204                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              929311                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst              101896                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               50984                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1955170                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               51019                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1955312                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.inst             873086                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             929204                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             929311                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst             101896                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              50984                       # number of overall hits
-system.l2c.overall_hits::total                1955170                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              51019                       # number of overall hits
+system.l2c.overall_hits::total                1955312                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.inst            11894                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data           926761                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst             1734                       # number of ReadReq misses
@@ -116,55 +116,55 @@ system.l2c.overall_misses::cpu1.inst             1734                       # nu
 system.l2c.overall_misses::cpu1.data            10570                       # number of overall misses
 system.l2c.overall_misses::total              1066665                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu0.inst         884980                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1689808                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1689838                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst         103630                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          37632                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2716050                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       816766                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           816766                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2575                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          606                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3181                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          37642                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2716090                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       816653                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           816653                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2577                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          607                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3184                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data           79                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data          109                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       281863                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        23922                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           305785                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       281940                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        23947                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           305887                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.inst          884980                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1971671                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1971778                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst          103630                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           61554                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3021835                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           61589                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3021977                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst         884980                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1971671                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1971778                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst         103630                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          61554                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3021835                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          61589                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3021977                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.inst      0.013440                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.548442                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.548432                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.016733                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024128                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.346568                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.948350                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.940594                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.946872                       # miss rate for UpgradeReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024122                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.346563                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.947614                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.939044                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.945980                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.822785                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.917431                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.877660                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.410504                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.403896                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.409987                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.410392                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.403474                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.409851                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.013440                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.528723                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.528694                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.016733                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.171719                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.352986                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.171622                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.352969                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.013440                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.528723                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.528694                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.016733                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.171719                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.352986                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.171622                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.352969                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -448,8 +448,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks           95                       # number of writebacks
-system.cpu0.icache.writebacks::total               95                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements               1978686                       # number of replacements
 system.cpu0.dcache.tagsinuse               507.129778                       # Cycle average of tags in use
@@ -687,8 +685,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks           18                       # number of writebacks
-system.cpu1.icache.writebacks::total               18                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                 62044                       # number of replacements
 system.cpu1.dcache.tagsinuse               421.562730                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 3950ce4a4..29a31b8cf 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -190,7 +190,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -252,9 +252,9 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
@@ -309,7 +309,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index d842316f6..ed03a48be 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:03
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 21:39:53
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index e2a65cb45..179af31f5 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4017982                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4017978                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                           122425314574                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297960                       # Number of bytes of host memory used
-host_seconds                                    14.94                       # Real time elapsed on the host
+host_inst_rate                                2962809                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2962806                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            90274916526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302384                       # Number of bytes of host memory used
+host_seconds                                    20.26                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
@@ -40,9 +40,9 @@ system.physmem.bw_total::tsunami.ide          1449867                       # To
 system.physmem.bw_total::total               42507908                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        992301                       # number of replacements
 system.l2c.tagsinuse                     65424.374305                       # Cycle average of tags in use
-system.l2c.total_refs                         2433195                       # Total number of references to valid blocks.
+system.l2c.total_refs                         2433239                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                       1057464                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.300972                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.301014                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
 system.l2c.occ_blocks::writebacks        56309.122439                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.inst           4867.329747                       # Average occupied blocks per requestor
@@ -52,20 +52,20 @@ system.l2c.occ_percent::cpu.inst             0.074270                       # Av
 system.l2c.occ_percent::cpu.data             0.064818                       # Average percentage of cache occupancy
 system.l2c.occ_percent::total                0.998297                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu.inst              906797                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              811183                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1717980                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          833599                       # number of Writeback hits
-system.l2c.Writeback_hits::total               833599                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data                1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   1                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            187125                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187125                       # number of ReadExReq hits
+system.l2c.ReadReq_hits::cpu.data              811229                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1718026                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          833491                       # number of Writeback hits
+system.l2c.Writeback_hits::total               833491                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data                4                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   4                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            187229                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               187229                       # number of ReadExReq hits
 system.l2c.demand_hits::cpu.inst               906797                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               998308                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1905105                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               998458                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1905255                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu.inst              906797                       # number of overall hits
-system.l2c.overall_hits::cpu.data              998308                       # number of overall hits
-system.l2c.overall_hits::total                1905105                       # number of overall hits
+system.l2c.overall_hits::cpu.data              998458                       # number of overall hits
+system.l2c.overall_hits::total                1905255                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.inst             13406                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data            927640                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               941046                       # number of ReadReq misses
@@ -80,33 +80,33 @@ system.l2c.overall_misses::cpu.inst             13406                       # nu
 system.l2c.overall_misses::cpu.data           1044757                       # number of overall misses
 system.l2c.overall_misses::total              1058163                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu.inst          920203                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1738823                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2659026                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       833599                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           833599                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        304242                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1738869                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2659072                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       833491                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           833491                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        304346                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304346                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu.inst           920203                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          2043065                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2963268                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          2043215                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2963418                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu.inst          920203                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         2043065                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2963268                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         2043215                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2963418                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.014569                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.533487                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.353906                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.923077                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.923077                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.384947                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.384947                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.533473                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.353900                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.750000                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.384815                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.384815                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.inst        0.014569                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.511367                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.357093                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.511330                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.357075                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.inst       0.014569                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.511367                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.357093                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.511330                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.357075                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -385,8 +385,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          108                       # number of writebacks
-system.cpu.icache.writebacks::total               108                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2042702                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index b6c3eb879..e9608d5ae 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -343,7 +343,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index e633d965f..3b87d756d 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:09:26
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 21:40:05
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 573593000
-Exiting @ tick 1954209106000 because m5_exit instruction encountered
+Exiting @ tick 1954209529000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index e64aeb301..19b49bfc4 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.954209                       # Number of seconds simulated
-sim_ticks                                1954209106000                       # Number of ticks simulated
-final_tick                               1954209106000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.954210                       # Number of seconds simulated
+sim_ticks                                1954209529000                       # Number of ticks simulated
+final_tick                               1954209529000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1820229                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1820228                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            59866957581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296900                       # Number of bytes of host memory used
-host_seconds                                    32.64                       # Real time elapsed on the host
-sim_insts                                    59416827                       # Number of instructions simulated
-sim_ops                                      59416827                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1320479                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1320478                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43430338961                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301360                       # Number of bytes of host memory used
+host_seconds                                    45.00                       # Real time elapsed on the host
+sim_insts                                    59416773                       # Number of instructions simulated
+sim_ops                                      59416773                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst           717056                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         23797184                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
@@ -31,90 +31,90 @@ system.physmem.num_reads::total                448972                       # Nu
 system.physmem.num_writes::writebacks          121019                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               121019                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.inst              366929                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12177399                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1355712                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12177396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1355711                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst               74637                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              729077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14703753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              729076                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14703750                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu0.inst         366929                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst          74637                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             441566                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3963351                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3963351                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3963351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3963350                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3963350                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3963350                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.inst             366929                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12177399                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1355712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12177396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1355711                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst              74637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             729077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18667104                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             729076                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18667100                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        342059                       # number of replacements
-system.l2c.tagsinuse                     65268.179703                       # Cycle average of tags in use
-system.l2c.total_refs                         2559285                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        407065                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.287165                       # Average number of references to valid blocks.
+system.l2c.tagsinuse                     65268.160318                       # Cycle average of tags in use
+system.l2c.total_refs                         2559182                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        407064                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.286928                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    7752825000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55637.656104                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          3742.496714                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4175.529809                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          1176.827938                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data           535.669138                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks        55637.634903                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3742.497316                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4175.530834                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          1176.828105                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data           535.669160                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.848963                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.inst            0.057106                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.data            0.063714                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.inst            0.017957                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.data            0.008174                       # Average percentage of cache occupancy
 system.l2c.occ_percent::total                0.995913                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             478629                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             342574                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             511941                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             491320                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1824464                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          858732                       # number of Writeback hits
-system.l2c.Writeback_hits::total               858732                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             137                       # number of UpgradeReq hits
+system.l2c.ReadReq_hits::cpu0.inst             478624                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             342590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             511938                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             491329                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1824481                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          858650                       # number of Writeback hits
+system.l2c.Writeback_hits::total               858650                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             133                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data              95                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 232                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 228                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data            22                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                46                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           101383                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            99295                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               200678                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              478629                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              443957                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              511941                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              590615                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2025142                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             478629                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             443957                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             511941                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             590615                       # number of overall hits
-system.l2c.overall_hits::total                2025142                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu0.data           101497                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            99318                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               200815                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              478624                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              444087                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              511938                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              590647                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2025296                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             478624                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             444087                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             511938                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             590647                       # number of overall hits
+system.l2c.overall_hits::total                2025296                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.inst            11204                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data           270589                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst             2290                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data             1211                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               285294                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2576                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2582                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu1.data           476                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3052                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3058                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu0.data           85                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data           88                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total             173                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         101598                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         101602                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data          21093                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122691                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122695                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.inst             11204                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            372187                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            372191                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst              2290                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data             22304                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                407985                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                407989                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.inst            11204                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           372187                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           372191                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst             2290                       # number of overall misses
 system.l2c.overall_misses::cpu1.data            22304                       # number of overall misses
-system.l2c.overall_misses::total               407985                       # number of overall misses
+system.l2c.overall_misses::total               407989                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.inst    582910000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.data  14075669000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.inst    119002000                       # number of ReadReq miss cycles
@@ -126,93 +126,93 @@ system.l2c.UpgradeReq_miss_latency::total      3068000                       # n
 system.l2c.SCUpgradeReq_miss_latency::cpu0.data       695000                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu1.data       156000                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::total       851000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5283374000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5283582000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data   1096874000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6380248000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6380456000                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.inst    582910000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  19359043000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  19359251000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.inst    119002000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data   1160294000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21221249000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21221457000                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.inst    582910000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  19359043000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  19359251000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.inst    119002000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data   1160294000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21221249000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         489833                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         613163                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         514231                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         492531                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2109758                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       858732                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           858732                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2713                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_miss_latency::total    21221457000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         489828                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         613179                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         514228                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         492540                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2109775                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       858650                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           858650                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2715                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data          571                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3284                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3286                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data          107                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data          112                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           219                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       202981                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       120388                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           323369                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          489833                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          816144                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          514231                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          612919                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2433127                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         489833                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         816144                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         514231                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         612919                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2433127                       # number of overall (read+write) accesses
+system.l2c.ReadExReq_accesses::cpu0.data       203099                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       120411                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           323510                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          489828                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          816278                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          514228                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          612951                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2433285                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         489828                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         816278                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         514228                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         612951                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2433285                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.inst      0.022873                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.441300                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.441289                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.004453                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.002459                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.135226                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.949502                       # miss rate for UpgradeReq accesses
+system.l2c.ReadReq_miss_rate::total          0.135225                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.951013                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.833625                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.929354                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.930615                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.794393                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.785714                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.789954                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.500530                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.175208                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.379415                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.500258                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.175175                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.379262                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.022873                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.456031                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.455961                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.004453                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.036390                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.167679                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.036388                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.167670                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.022873                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.456031                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.455961                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.004453                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.036390                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.167679                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.036388                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.167670                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total 52020.024957                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   444.099379                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   443.067390                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4042.016807                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1005.242464                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1003.270111                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  8176.470588                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1772.727273                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total  4919.075145                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736274                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736167                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52002.575576                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52002.575492                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52014.291203                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52014.291049                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52014.777504                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52014.777359                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52014.291203                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52014.291049                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52014.777504                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52014.777359                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -234,106 +234,106 @@ system.l2c.ReadReq_mshr_misses::cpu0.data       270589                       # n
 system.l2c.ReadReq_mshr_misses::cpu1.inst         2279                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data         1211                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total          285283                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2576                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2582                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu1.data          476                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3052                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3058                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           85                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           88                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total          173                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       101598                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       101602                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data        21093                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122691                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122695                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.inst        11204                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       372187                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       372191                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst         2279                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data        22304                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           407974                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           407978                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst        11204                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       372187                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       372191                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.inst         2279                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data        22304                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          407974                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          407978                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    448459000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10828601000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     91164000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.data     48888000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::total  11417112000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    103144000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19089000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    122233000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    103374000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19058000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    122432000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3419000                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3520000                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total      6939000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4064198000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4064358000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    843758000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4907956000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4908116000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.inst    448459000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  14892799000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  14892959000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst     91164000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data    892646000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16325068000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16325228000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.inst    448459000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  14892799000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  14892959000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst     91164000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data    892646000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16325068000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16325228000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    538312030                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    264188000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total    802500030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    914387000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    465201000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1379588000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1452699030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    729389000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2182088030                       # number of overall MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    914384000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    465175000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1379559000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1452696030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    729363000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2182059030                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.441300                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.441289                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002459                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.135221                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.949502                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.135220                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.951013                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.833625                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.929354                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.930615                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794393                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.789954                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.500530                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.175208                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.379415                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.500258                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.175175                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.379262                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.456031                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.455961                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.036390                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167675                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.036388                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.167666                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.456031                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.455961                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.036390                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167675                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.036388                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.167666                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.372671                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40102.941176                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.131062                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.405887                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40037.815126                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40036.625245                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736274                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736167                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575576                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575492                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291203                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291049                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40014.971542                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40014.971396                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291203                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291049                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40014.971542                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40014.971396                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41707                       # number of replacements
-system.iocache.tagsinuse                     1.261560                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.261563                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41723                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1747651126000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.261560                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.078847                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.078847                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::tsunami.ide       1.261563                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.078848                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.078848                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide        41728                       #
 system.iocache.overall_misses::total            41728                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21013998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21013998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7626020806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7626020806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7647034804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7647034804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7647034804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7647034804                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7626285806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7626285806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7647299804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7647299804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7647299804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7647299804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119397.715909                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183529.572728                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183259.077933                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183259.077933                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7245000                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183535.950279                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183265.428585                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183265.428585                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7316000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7076                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7050                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1023.883550                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1037.730496                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41728
 system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11861000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     11861000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5465163000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5465163000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5477024000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5477024000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5477024000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5477024000                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5465428000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5465428000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5477289000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5477289000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5477289000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5477289000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131255.368098                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131255.368098                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131261.718750                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131261.718750                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     5733478                       # DTB read hits
+system.cpu0.dtb.read_hits                     5733461                       # DTB read hits
 system.cpu0.dtb.read_misses                      7687                       # DTB read misses
 system.cpu0.dtb.read_acv                          174                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3961950                       # DTB write hits
+system.cpu0.dtb.write_hits                    3961949                       # DTB write hits
 system.cpu0.dtb.write_misses                      798                       # DTB write misses
 system.cpu0.dtb.write_acv                         115                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
-system.cpu0.dtb.data_hits                     9695428                       # DTB hits
+system.cpu0.dtb.data_hits                     9695410                       # DTB hits
 system.cpu0.dtb.data_misses                      8485                       # DTB misses
 system.cpu0.dtb.data_acv                          289                       # DTB access violations
 system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3214168                       # ITB hits
+system.cpu0.itb.fetch_hits                    3214179                       # ITB hits
 system.cpu0.itb.fetch_misses                     3841                       # ITB misses
 system.cpu0.itb.fetch_acv                         143                       # ITB acv
-system.cpu0.itb.fetch_accesses                3218009                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3218020                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -480,55 +480,55 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3908418212                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3908419058                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   36160823                       # Number of instructions committed
-system.cpu0.committedOps                     36160823                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33648358                       # Number of integer alu accesses
+system.cpu0.committedInsts                   36160769                       # Number of instructions committed
+system.cpu0.committedOps                     36160769                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33648309                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                143029                       # Number of float alu accesses
-system.cpu0.num_func_calls                     874754                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4239281                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33648358                       # number of integer instructions
+system.cpu0.num_func_calls                     874750                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4239273                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33648309                       # number of integer instructions
 system.cpu0.num_fp_insts                       143029                       # number of float instructions
-system.cpu0.num_int_register_reads           46246578                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          25142775                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           46246517                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          25142738                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads               70823                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes              71471                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      9726012                       # number of memory refs
-system.cpu0.num_load_insts                    5755191                       # Number of load instructions
-system.cpu0.num_store_insts                   3970821                       # Number of store instructions
-system.cpu0.num_idle_cycles              3741416410.998085                       # Number of idle cycles
-system.cpu0.num_busy_cycles              167001801.001915                       # Number of busy cycles
+system.cpu0.num_mem_refs                      9725994                       # number of memory refs
+system.cpu0.num_load_insts                    5755174                       # Number of load instructions
+system.cpu0.num_store_insts                   3970820                       # Number of store instructions
+system.cpu0.num_idle_cycles              3741414636.998085                       # Number of idle cycles
+system.cpu0.num_busy_cycles              167004421.001915                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.042729                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.957271                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    4839                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    129052                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    129053                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   41012     38.31%     38.31% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    131      0.12%     38.43% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1971      1.84%     40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1971      1.84%     40.27% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                     17      0.02%     40.29% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  63918     59.71%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              107049                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  63919     59.71%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              107050                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    40581     48.74%     48.74% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.16%     48.90% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1971      2.37%     51.26% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                      17      0.02%     51.28% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   40564     48.72%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total                83264                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1905787793000     97.52%     97.52% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               88207500      0.00%     97.53% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              590484500      0.03%     97.56% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1905788612000     97.52%     97.52% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               88224500      0.00%     97.53% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              590412500      0.03%     97.56% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               12827000      0.00%     97.56% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            47728938000      2.44%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1954208250000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            47728597000      2.44%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1954208673000                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.989491                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.634626                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.777812                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.634616                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.777805                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.68%      2.68% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.48%     11.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         3      1.34%     12.50% # number of syscalls executed
@@ -568,7 +568,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.08% # nu
 system.cpu0.kern.callpal::swpctx                 1959      1.72%      1.80% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      44      0.04%      1.84% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.01%      1.84% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               101151     88.59%     90.44% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               101152     88.59%     90.44% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6620      5.80%     96.24% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.24% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     4      0.00%     96.24% # number of callpals executed
@@ -577,19 +577,19 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.25% # nu
 system.cpu0.kern.callpal::rti                    3778      3.31%     99.56% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 356      0.31%     99.87% # number of callpals executed
 system.cpu0.kern.callpal::imb                     149      0.13%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                114173                       # number of callpals executed
+system.cpu0.kern.callpal::total                114174                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5323                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1230                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1231                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1229                      
-system.cpu0.kern.mode_good::user                 1230                      
+system.cpu0.kern.mode_good::kernel               1230                      
+system.cpu0.kern.mode_good::user                 1231                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.230885                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.231073                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.375248                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1950524029000     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3684214000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.375496                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1950522760000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3685906000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    1960                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
@@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                489211                       # number of replacements
-system.cpu0.icache.tagsinuse               508.795621                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                35679745                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                489723                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 72.856993                       # Average number of references to valid blocks.
+system.cpu0.icache.replacements                489206                       # number of replacements
+system.cpu0.icache.tagsinuse               508.795620                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                35679696                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                489718                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 72.857636                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           36113258000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   508.795621                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu0.inst   508.795620                       # Average occupied blocks per requestor
 system.cpu0.icache.occ_percent::cpu0.inst     0.993741                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_percent::total        0.993741                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     35679745                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       35679745                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     35679745                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        35679745                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     35679745                       # number of overall hits
-system.cpu0.icache.overall_hits::total       35679745                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       489853                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       489853                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       489853                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        489853                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       489853                       # number of overall misses
-system.cpu0.icache.overall_misses::total       489853                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7462564000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7462564000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7462564000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7462564000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7462564000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7462564000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36169598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36169598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36169598                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36169598                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36169598                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36169598                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     35679696                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       35679696                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     35679696                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        35679696                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     35679696                       # number of overall hits
+system.cpu0.icache.overall_hits::total       35679696                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       489848                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       489848                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       489848                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        489848                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       489848                       # number of overall misses
+system.cpu0.icache.overall_misses::total       489848                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7462315000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7462315000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7462315000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7462315000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7462315000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7462315000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     36169544                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     36169544                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     36169544                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     36169544                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     36169544                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     36169544                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013543                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.013543                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013543                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     0.013543                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013543                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.013543                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15234.292737                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15234.292737                       # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15233.939916                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15233.939916                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -676,114 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks           58                       # number of writebacks
-system.cpu0.icache.writebacks::total               58                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       489853                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       489853                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       489853                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       489853                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       489853                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       489853                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5992343500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5992343500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5992343500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5992343500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5992343500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5992343500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       489848                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       489848                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       489848                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       489848                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       489848                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       489848                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5992109500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5992109500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5992109500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5992109500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5992109500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5992109500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.013543                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.013543                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                817835                       # number of replacements
-system.cpu0.dcache.tagsinuse               479.881432                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 8879650                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                818347                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 10.850715                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                817819                       # number of replacements
+system.cpu0.dcache.tagsinuse               479.881496                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 8879648                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                818331                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 10.850925                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              85697000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   479.881432                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.937268                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.937268                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5008280                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5008280                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3627742                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3627742                       # number of WriteReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   479.881496                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.937269                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.937269                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5008276                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5008276                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3627744                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3627744                       # number of WriteReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117045                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       117045                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122538                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       122538                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8636022                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         8636022                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8636022                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        8636022                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       610615                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       610615                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       207039                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       207039                       # number of WriteReq misses
+system.cpu0.dcache.demand_hits::cpu0.data      8636020                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         8636020                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8636020                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        8636020                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       610602                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       610602                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       207036                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       207036                       # number of WriteReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6562                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         6562                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data          580                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total          580                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       817654                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        817654                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       817654                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       817654                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  19940488000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  19940488000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7282919000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7282919000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92852000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     92852000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      8304000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      8304000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  27223407000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  27223407000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  27223407000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  27223407000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5618895                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5618895                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3834781                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      3834781                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_misses::cpu0.data       817638                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        817638                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       817638                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       817638                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  19940652000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  19940652000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7284412000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   7284412000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92857000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     92857000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      8303000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      8303000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  27225064000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  27225064000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  27225064000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  27225064000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5618878                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5618878                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3834780                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      3834780                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123607                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       123607                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123118                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       123118                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9453676                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total      9453676                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9453676                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total      9453676                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108672                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.108672                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.053990                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.053990                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data      9453658                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total      9453658                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      9453658                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total      9453658                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108670                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.108670                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.053989                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.053989                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053088                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053088                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004711                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004711                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086491                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086491                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086491                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086491                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672                       # average overall miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086489                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086489                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086489                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086489                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -792,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       359699                       # number of writebacks
-system.cpu0.dcache.writebacks::total           359699                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       610615                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       610615                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       207039                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       207039                       # number of WriteReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       359687                       # number of writebacks
+system.cpu0.dcache.writebacks::total           359687                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       610602                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       610602                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       207036                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       207036                       # number of WriteReq MSHR misses
 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6562                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6562                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          580                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total          580                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       817654                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       817654                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       817654                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       817654                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  18108577524                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  18108577524                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6661800002                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6661800002                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73166000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     73166000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      6564000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      6564000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  24770377526                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  24770377526                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  24770377526                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  24770377526                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    601208500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    601208500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1014438500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1014438500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1615647000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1615647000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108672                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108672                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.053990                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.053990                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       817638                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       817638                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       817638                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       817638                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  18108780524                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  18108780524                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6663302002                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6663302002                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73171000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     73171000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      6563000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      6563000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  24772082526                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  24772082526                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  24772082526                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  24772082526                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    601210500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    601210500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1014423500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1014423500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1615634000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1615634000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108670                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108670                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.053989                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.053989                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.053088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004711                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004711                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086491                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.086491                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086491                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.086491                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086489                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.086489                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086489                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.086489                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -887,7 +885,7 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3908222380                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3908222400                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                   23256004                       # Number of instructions committed
@@ -905,8 +903,8 @@ system.cpu1.num_fp_register_writes              97489                       # nu
 system.cpu1.num_mem_refs                      6725970                       # number of memory refs
 system.cpu1.num_load_insts                    3973767                       # Number of load instructions
 system.cpu1.num_store_insts                   2752203                       # Number of store instructions
-system.cpu1.num_idle_cycles              3808684025.637170                       # Number of idle cycles
-system.cpu1.num_busy_cycles              99538354.362830                       # Number of busy cycles
+system.cpu1.num_idle_cycles              3808683702.691761                       # Number of idle cycles
+system.cpu1.num_busy_cycles              99538697.308239                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.025469                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.974531                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
@@ -922,11 +920,11 @@ system.cpu1.kern.ipl_good::22                    1966      2.41%     51.21% # nu
 system.cpu1.kern.ipl_good::30                      91      0.11%     51.32% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   39692     48.68%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                81532                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1901560823500     97.31%     97.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              537428500      0.03%     97.34% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1901560916500     97.31%     97.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              537337500      0.03%     97.34% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               59036000      0.00%     97.34% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            51953872000      2.66%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1954111160000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            51953880000      2.66%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1954111170000                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.976773                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -982,37 +980,37 @@ system.cpu1.kern.mode_switch_good::kernel     0.200282                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.026006                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.210800                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       72316980000      3.70%      3.70% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1607803000      0.08%      3.78% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1879348629000     96.22%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel       72317077000      3.70%      3.70% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1608073000      0.08%      3.78% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1879348652000     96.22%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2293                       # number of times the context was actually changed
-system.cpu1.icache.replacements                513695                       # number of replacements
-system.cpu1.icache.tagsinuse               501.294136                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                22744962                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                514207                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 44.233085                       # Average number of references to valid blocks.
+system.cpu1.icache.replacements                513692                       # number of replacements
+system.cpu1.icache.tagsinuse               501.294138                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                22744965                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                514204                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 44.233349                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle           96225204000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   501.294136                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_blocks::cpu1.inst   501.294138                       # Average occupied blocks per requestor
 system.cpu1.icache.occ_percent::cpu1.inst     0.979090                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_percent::total        0.979090                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     22744962                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       22744962                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     22744962                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        22744962                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     22744962                       # number of overall hits
-system.cpu1.icache.overall_hits::total       22744962                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       514232                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       514232                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       514232                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        514232                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       514232                       # number of overall misses
-system.cpu1.icache.overall_misses::total       514232                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7551962500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7551962500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7551962500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7551962500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7551962500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7551962500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_hits::cpu1.inst     22744965                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       22744965                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     22744965                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        22744965                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     22744965                       # number of overall hits
+system.cpu1.icache.overall_hits::total       22744965                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       514229                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       514229                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       514229                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        514229                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       514229                       # number of overall misses
+system.cpu1.icache.overall_misses::total       514229                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7551928500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7551928500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7551928500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7551928500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7551928500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7551928500                       # number of overall miss cycles
 system.cpu1.icache.ReadReq_accesses::cpu1.inst     23259194                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total     23259194                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.demand_accesses::cpu1.inst     23259194                       # number of demand (read+write) accesses
@@ -1025,12 +1023,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022109
 system.cpu1.icache.demand_miss_rate::total     0.022109                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022109                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     0.022109                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14685.905389                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14685.905389                       # average overall miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14685.924948                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14685.924948                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1039,78 +1037,76 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks           11                       # number of writebacks
-system.cpu1.icache.writebacks::total               11                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       514232                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       514232                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       514232                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       514232                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       514232                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       514232                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6009201500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6009201500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6009201500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6009201500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6009201500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6009201500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       514229                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       514229                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       514229                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       514229                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       514229                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       514229                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6009175500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   6009175500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6009175500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   6009175500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6009175500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   6009175500                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022109                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total     0.022109                       # mshr miss rate for demand accesses
 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total     0.022109                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                642543                       # number of replacements
-system.cpu1.dcache.tagsinuse               493.349744                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 6059288                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                642980                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                  9.423758                       # Average number of references to valid blocks.
+system.cpu1.dcache.replacements                642542                       # number of replacements
+system.cpu1.dcache.tagsinuse               493.349728                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 6059289                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                642979                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                  9.423774                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle           54205321000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   493.349744                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_blocks::cpu1.data   493.349728                       # Average occupied blocks per requestor
 system.cpu1.dcache.occ_percent::cpu1.data     0.963574                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_percent::total        0.963574                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3370942                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3370942                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2541026                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2541026                       # number of WriteReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3370941                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3370941                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2541028                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2541028                       # number of WriteReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        71125                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        71125                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80221                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        80221                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5911968                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5911968                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5911968                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5911968                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       513440                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       513440                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       122215                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       122215                       # number of WriteReq misses
+system.cpu1.dcache.demand_hits::cpu1.data      5911969                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5911969                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5911969                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5911969                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       513441                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       513441                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       122213                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       122213                       # number of WriteReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13103                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total        13103                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data          640                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total          640                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       635655                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        635655                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       635655                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       635655                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7202447500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   7202447500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2665469000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2665469000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    183740000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    183740000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.demand_misses::cpu1.data       635654                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        635654                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       635654                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       635654                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7202554500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   7202554500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2665634000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2665634000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    183727000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    183727000                       # number of LoadLockedReq miss cycles
 system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8466000                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.StoreCondReq_miss_latency::total      8466000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   9867916500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   9867916500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   9867916500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   9867916500                       # number of overall miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   9868188500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   9868188500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   9868188500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   9868188500                       # number of overall miss cycles
 system.cpu1.dcache.ReadReq_accesses::cpu1.data      3884382                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      3884382                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data      2663241                       # number of WriteReq accesses(hits+misses)
@@ -1125,8 +1121,8 @@ system.cpu1.dcache.overall_accesses::cpu1.data      6547623
 system.cpu1.dcache.overall_accesses::total      6547623                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.132181                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.132181                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.045890                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.045890                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.045889                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.045889                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155566                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155566                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007915                       # miss rate for StoreCondReq accesses
@@ -1135,18 +1131,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097082
 system.cpu1.dcache.demand_miss_rate::total     0.097082                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097082                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     0.097082                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883                       # average LoadLockedReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744                       # average LoadLockedReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.465354                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15524.465354                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.465354                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15524.465354                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1155,44 +1151,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       498964                       # number of writebacks
-system.cpu1.dcache.writebacks::total           498964                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       513440                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       513440                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       122215                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       122215                       # number of WriteReq MSHR misses
+system.cpu1.dcache.writebacks::writebacks       498963                       # number of writebacks
+system.cpu1.dcache.writebacks::total           498963                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       513441                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       513441                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       122213                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       122213                       # number of WriteReq MSHR misses
 system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        13103                       # number of LoadLockedReq MSHR misses
 system.cpu1.dcache.LoadLockedReq_mshr_misses::total        13103                       # number of LoadLockedReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          640                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::total          640                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       635655                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       635655                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       635655                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       635655                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5662112010                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5662112010                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2298824000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2298824000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    144431000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    144431000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       635654                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       635654                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       635654                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       635654                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5662217009                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5662217009                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2298995000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2298995000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    144418000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    144418000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6549000                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6549000                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         5000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         5000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7960936010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   7960936010                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7960936010                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   7960936010                       # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7961212009                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7961212009                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7961212009                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7961212009                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    295035500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    295035500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    516397500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    516397500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    811433000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    811433000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    516366500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    516366500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    811402000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    811402000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.132181                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.132181                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.045890                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.045890                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.045889                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.045889                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155566                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155566                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007915                       # mshr miss rate for StoreCondReq accesses
@@ -1201,20 +1197,20 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097082
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.097082                       # mshr miss rate for demand accesses
 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097082                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total     0.097082                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744                       # average LoadLockedReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index a60709d68..734887994 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -250,7 +250,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port[0]
+master=system.bridge.slave system.physmem.port
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index c99186441..e4a5afde7 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,11 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:09:16
+gem5 compiled Jul 26 2012 21:20:05
+gem5 started Jul 26 2012 21:40:05
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
+      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1920852274000 because m5_exit instruction encountered
+Exiting @ tick 1920853042000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 8d476d641..c7cd1312f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.920852                       # Number of seconds simulated
-sim_ticks                                1920852274000                       # Number of ticks simulated
-final_tick                               1920852274000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.920853                       # Number of seconds simulated
+sim_ticks                                1920853042000                       # Number of ticks simulated
+final_tick                               1920853042000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1904642                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1904641                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            65112526106                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294856                       # Number of bytes of host memory used
-host_seconds                                    29.50                       # Real time elapsed on the host
+host_inst_rate                                1381815                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1381815                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            47239093914                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299308                       # Number of bytes of host memory used
+host_seconds                                    40.66                       # Real time elapsed on the host
 sim_insts                                    56187824                       # Number of instructions simulated
 sim_ops                                      56187824                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
@@ -26,113 +26,113 @@ system.physmem.num_reads::total                442978                       # Nu
 system.physmem.num_writes::writebacks          115454                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               115454                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               442870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12935691                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12935686                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide           1380820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14759382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14759376                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          442870                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             442870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3846759                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3846759                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3846759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3846758                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3846758                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3846758                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              442870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12935691                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12935686                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide          1380820                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18606141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18606133                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        336066                       # number of replacements
-system.l2c.tagsinuse                     65311.816256                       # Cycle average of tags in use
-system.l2c.total_refs                         2448229                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        401229                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.101825                       # Average number of references to valid blocks.
+system.l2c.tagsinuse                     65311.806529                       # Cycle average of tags in use
+system.l2c.total_refs                         2448197                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        401228                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.101760                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    5946056000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55675.740322                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           4768.394145                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           4867.681789                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks        55675.727094                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           4768.395922                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           4867.683513                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.849544                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.inst             0.072760                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.data             0.074275                       # Average percentage of cache occupancy
 system.l2c.occ_percent::total                0.996579                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst              916210                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              814879                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1731089                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835223                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835223                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data                6                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            187457                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187457                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst               916210                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1002336                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1918546                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst              916210                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1002336                       # number of overall hits
-system.l2c.overall_hits::total                1918546                       # number of overall hits
+system.l2c.ReadReq_hits::cpu.inst              916208                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              814933                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1731141                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835149                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835149                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data                4                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   4                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            187605                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               187605                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst               916208                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1002538                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1918746                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst              916208                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1002538                       # number of overall hits
+system.l2c.overall_hits::total                1918746                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.inst             13292                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data            271915                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               285207                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data              8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 8                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          116714                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             116714                       # number of ReadExReq misses
+system.l2c.UpgradeReq_misses::cpu.data             14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                14                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          116718                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             116718                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.inst              13292                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             388629                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                401921                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             388633                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                401925                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.inst             13292                       # number of overall misses
-system.l2c.overall_misses::cpu.data            388629                       # number of overall misses
-system.l2c.overall_misses::total               401921                       # number of overall misses
+system.l2c.overall_misses::cpu.data            388633                       # number of overall misses
+system.l2c.overall_misses::total               401925                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu.inst    691773000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.data  14144855000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::total    14836628000                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu.data       320000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total       320000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6069807000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6069807000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6070015000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6070015000                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu.inst    691773000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20214662000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20906435000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20214870000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     20906643000                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu.inst    691773000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20214662000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20906435000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst          929502                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1086794                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2016296                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       835223                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835223                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           14                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              14                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        304171                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304171                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst           929502                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1390965                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2320467                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          929502                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1390965                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2320467                       # number of overall (read+write) accesses
+system.l2c.overall_miss_latency::cpu.data  20214870000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    20906643000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst          929500                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1086848                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2016348                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       835149                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835149                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           18                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              18                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        304323                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304323                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst           929500                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1391171                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2320671                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          929500                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1391171                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2320671                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.014300                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.250199                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.141451                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.571429                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.571429                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383712                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383712                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.250187                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.141447                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.777778                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.777778                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383533                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383533                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.inst        0.014300                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.279395                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173207                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.279357                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.173193                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.inst       0.014300                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.279395                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173207                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.279357                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.173193                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total 52020.560505                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data        40000                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total        40000                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52005.817640                       # average ReadExReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52005.817440                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52015.320524                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52016.279319                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52015.320367                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52016.279157                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52015.320524                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52016.279319                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52015.320367                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52016.279157                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -146,29 +146,29 @@ system.l2c.writebacks::total                    73942                       # nu
 system.l2c.ReadReq_mshr_misses::cpu.inst        13292                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.data       271915                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total          285207                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       116714                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        116714                       # number of ReadExReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data           14                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           14                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       116718                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        116718                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu.inst         13292                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        388629                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           401921                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        388633                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           401925                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu.inst        13292                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       388629                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          401921                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       388633                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          401925                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu.inst    532266000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.data  10881875000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::total  11414141000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       380000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       380000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4669239000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4669239000                       # number of ReadExReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       620000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       620000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4669399000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4669399000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.inst    532266000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15551114000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16083380000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15551274000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16083540000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.inst    532266000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15551114000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16083380000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15551274000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16083540000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    772639030                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total    772639030                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1072677000                       # number of WriteReq MSHR uncacheable cycles
@@ -176,31 +176,31 @@ system.l2c.WriteReq_mshr_uncacheable_latency::total   1072677000
 system.l2c.overall_mshr_uncacheable_latency::cpu.data   1845316030                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::total   1845316030                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250199                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.141451                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.571429                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383712                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383712                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250187                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.141447                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.777778                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.777778                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383533                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383533                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.279395                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173207                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.279357                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173193                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.279395                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173207                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.279357                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173193                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        47500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        47500                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40016.271854                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40016.271692                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40016.271854                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40016.271692                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.356962                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.356968                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1753491316000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.356962                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.084810                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.084810                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::tsunami.ide       1.356968                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.084811                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.084811                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -344,7 +344,7 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3841704548                       # number of cpu cycles simulated
+system.cpu.numCycles                       3841706084                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    56187824                       # Number of instructions committed
@@ -362,10 +362,10 @@ system.cpu.num_fp_register_writes              166520                       # nu
 system.cpu.num_mem_refs                      15475451                       # number of memory refs
 system.cpu.num_load_insts                     9102635                       # Number of load instructions
 system.cpu.num_store_insts                    6372816                       # Number of store instructions
-system.cpu.num_idle_cycles               3589583028.998131                       # Number of idle cycles
-system.cpu.num_busy_cycles               252121519.001869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065628                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934372                       # Percentage of idle cycles
+system.cpu.num_idle_cycles               3589579952.998131                       # Number of idle cycles
+system.cpu.num_busy_cycles               252126131.001869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065629                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934371                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
 system.cpu.kern.inst.hwrei                     212104                       # number of hwrei instructions executed
@@ -379,11 +379,11 @@ system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # nu
 system.cpu.kern.ipl_good::22                     1936      1.30%     50.69% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73562     49.31%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149191                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1861395067500     96.90%     96.90% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1861395652500     96.90%     96.90% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                90398000      0.00%     96.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               587303500      0.03%     96.94% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             58778672000      3.06%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1920851441000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               587366500      0.03%     96.94% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             58778792000      3.06%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1920852209000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981756                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -447,9 +447,9 @@ system.cpu.kern.mode_switch_good::kernel     0.323061                       # fr
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::total      0.391706                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46234544000      2.41%      2.41% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5257252000      0.27%      2.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1869359638000     97.32%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel        46234707000      2.41%      2.41% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5259387000      0.27%      2.68% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1869358108000     97.32%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -482,33 +482,33 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                 928851                       # number of replacements
-system.cpu.icache.tagsinuse                508.732124                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55270141                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 929362                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  59.471058                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                 928849                       # number of replacements
+system.cpu.icache.tagsinuse                508.732123                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55270143                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 929360                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  59.471188                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            35877190000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     508.732124                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     508.732123                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.993617                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.993617                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     55270141                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55270141                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55270141                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55270141                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55270141                       # number of overall hits
-system.cpu.icache.overall_hits::total        55270141                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929522                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929522                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929522                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929522                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929522                       # number of overall misses
-system.cpu.icache.overall_misses::total        929522                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13854472500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13854472500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13854472500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13854472500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13854472500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13854472500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_hits::cpu.inst     55270143                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55270143                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55270143                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55270143                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55270143                       # number of overall hits
+system.cpu.icache.overall_hits::total        55270143                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929520                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929520                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929520                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929520                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929520                       # number of overall misses
+system.cpu.icache.overall_misses::total        929520                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13854449500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13854449500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13854449500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13854449500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13854449500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13854449500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     56199663                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     56199663                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     56199663                       # number of demand (read+write) accesses
@@ -521,12 +521,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.016540
 system.cpu.icache.demand_miss_rate::total     0.016540                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.016540                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.016540                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14904.943078                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14904.943078                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14904.950405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14904.950405                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -535,74 +535,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks           85                       # number of writebacks
-system.cpu.icache.writebacks::total                85                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929522                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929522                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929522                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929522                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929522                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929522                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11065220000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11065220000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11065220000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11065220000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11065220000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11065220000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929520                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929520                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929520                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929520                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929520                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929520                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11065203000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11065203000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11065203000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11065203000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11065203000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11065203000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016540                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.016540                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.016540                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1390643                       # number of replacements
+system.cpu.dcache.replacements                1390657                       # number of replacements
 system.cpu.dcache.tagsinuse                511.983813                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14050710                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1391155                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.100032                       # Average number of references to valid blocks.
+system.cpu.dcache.total_refs                 14050696                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1391169                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.099920                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               85768000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::cpu.data     511.983813                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999968                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7815347                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815347                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5853082                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5853082                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data      7815339                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7815339                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853076                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853076                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data       182979                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       182979                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       199284                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199284                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13668429                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13668429                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13668429                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13668429                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069514                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069514                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304335                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      13668415                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13668415                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13668415                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13668415                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069522                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069522                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304341                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304341                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data        17326                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        17326                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373849                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373849                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373849                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373849                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26655510000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26655510000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9230954000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9230954000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1373863                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373863                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373863                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373863                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26656014000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26656014000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9232792000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9232792000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    248493000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total    248493000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35886464000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35886464000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35886464000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35886464000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35888806000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35888806000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35888806000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35888806000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data      8884861                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      8884861                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6157417                       # number of WriteReq accesses(hits+misses)
@@ -615,26 +613,26 @@ system.cpu.dcache.demand_accesses::cpu.data     15042278                       #
 system.cpu.dcache.demand_accesses::total     15042278                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data     15042278                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15042278                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120375                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120375                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049426                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049426                       # miss rate for WriteReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120376                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120376                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049427                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049427                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086498                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086498                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.091333                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.091333                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.091333                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.091333                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26121.112291                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26121.112291                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26122.550793                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26122.550793                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -643,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835138                       # number of writebacks
-system.cpu.dcache.writebacks::total            835138                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069514                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069514                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304335                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       835149                       # number of writebacks
+system.cpu.dcache.writebacks::total            835149                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069522                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069522                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304341                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304341                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17326                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total        17326                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373849                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373849                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373849                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373849                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23446923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23446923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8317949000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8317949000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373863                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373863                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373863                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373863                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23447403000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23447403000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8319769000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8319769000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    196515000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196515000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31764872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  31764872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31764872000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31764872000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31767172000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  31767172000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31767172000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31767172000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    862831000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    862831000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1190523500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1190523500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2053354500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total   2053354500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120375                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120375                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049426                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049426                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120376                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120376                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049427                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049427                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086498                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086498                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.091333                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.091333                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index e2b1a3bea..cab94b1b5 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -306,7 +306,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -367,9 +367,9 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
@@ -780,7 +780,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 50982556e..638b19e04 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:36:18
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 00:55:21
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 911653589000 because m5_exit instruction encountered
+Exiting @ tick 912096763500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index c0313feaf..492e0d099 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,16 +1,71 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.911654                       # Number of seconds simulated
-sim_ticks                                911653589000                       # Number of ticks simulated
-final_tick                               911653589000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.912097                       # Number of seconds simulated
+sim_ticks                                912096763500                       # Number of ticks simulated
+final_tick                               912096763500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2171864                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2807005                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32664627860                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 382740                       # Number of bytes of host memory used
-host_seconds                                    27.91                       # Real time elapsed on the host
-sim_insts                                    60615585                       # Number of instructions simulated
-sim_ops                                      78342060                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1622636                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2089140                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24015838223                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388524                       # Number of bytes of host memory used
+host_seconds                                    37.98                       # Real time elapsed on the host
+sim_insts                                    61625970                       # Number of instructions simulated
+sim_ops                                      79343340                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           502180                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6234996                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           214556                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          3364528                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49638308                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       502180                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       214556                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          716736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4195776                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7222864                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             14065                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             97494                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3434                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             52597                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               5082797                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           65559                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               822331                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43111215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            70                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              550578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             6835893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              235234                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3688784                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                54422195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         550578                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         235234                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             785811                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4600144                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              18638                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            3300185                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7918967                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4600144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43111215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           70                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             550578                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            6854532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             235234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6988969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               62341162                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -29,238 +84,171 @@ system.realview.nvmem.bw_inst_read::total           75                       # I
 system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           506468                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6290740                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           210652                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          3309616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49639524                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       506468                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       210652                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          717120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4196032                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7223120                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14132                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             98365                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3373                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             51739                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               5082816                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           65563                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               822335                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43132173                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            70                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              555549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             6900362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            70                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              231066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3630344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                54449985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         555549                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         231066                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             786615                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4602661                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              18647                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            3301789                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7923097                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4602661                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43132173                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           70                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             555549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            6919010                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           70                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             231066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6932133                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               62373082                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         70681                       # number of replacements
-system.l2c.tagsinuse                     51554.827924                       # Cycle average of tags in use
-system.l2c.total_refs                         1661073                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        135855                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         12.226808                       # Average number of references to valid blocks.
+system.l2c.replacements                         70662                       # number of replacements
+system.l2c.tagsinuse                     51560.217790                       # Cycle average of tags in use
+system.l2c.total_refs                         1623342                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        135814                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         11.952685                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        39271.893324                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks        39276.104351                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu0.dtb.walker       0.000049                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.000326                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          4360.096185                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          2483.383308                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker       2.678787                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker       0.000776                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          2126.160779                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          3310.614391                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.599242                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.itb.walker       0.001108                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4360.752038                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2483.307369                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       2.678940                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2126.451282                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          3310.922653                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.599306                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.066530                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.037893                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.066540                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.037892                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.dtb.walker      0.000041                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.032443                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.050516                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.786664                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         5302                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2202                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             487741                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             211552                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         4297                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1568                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             361833                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             130247                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1204742                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          613260                       # number of Writeback hits
-system.l2c.Writeback_hits::total               613260                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             827                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             750                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1577                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           123                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            53                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               176                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            71506                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            36206                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107712                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5302                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          2202                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              487741                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              283058                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4297                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1568                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              361833                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              166453                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1312454                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5302                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         2202                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             487741                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             283058                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4297                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1568                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             361833                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             166453                       # number of overall hits
-system.l2c.overall_hits::total                1312454                       # number of overall hits
+system.l2c.occ_percent::cpu1.inst            0.032447                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.050521                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.786746                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         3874                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1919                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             421038                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             175188                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         5331                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1734                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             430511                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             169511                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1209106                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          567807                       # number of Writeback hits
+system.l2c.Writeback_hits::total               567807                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             611                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             663                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1274                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           137                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               168                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            58151                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            50212                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               108363                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          3874                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1919                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              421038                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              233339                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5331                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1734                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              430511                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              219723                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1317469                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         3874                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1919                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             421038                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             233339                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5331                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1734                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             430511                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             219723                       # number of overall hits
+system.l2c.overall_hits::total                1317469                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7499                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6382                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7432                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6392                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3286                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             5264                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22438                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          6263                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3008                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9271                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          734                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          484                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1218                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          93870                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          47031                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140901                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst             3347                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             5276                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                22454                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          4932                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4304                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              9236                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          741                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          490                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1231                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          92461                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          48372                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140833                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7499                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            100252                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7432                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             98853                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3286                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             52295                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                163339                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              3347                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             53648                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                163287                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7499                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           100252                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7432                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            98853                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3286                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            52295                       # number of overall misses
-system.l2c.overall_misses::total               163339                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         5303                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         2204                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         495240                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         217934                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         4300                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1569                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         365119                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         135511                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1227180                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       613260                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           613260                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         7090                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3758                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10848                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          857                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          537                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1394                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       165376                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        83237                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           248613                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         5303                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         2204                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          495240                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          383310                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         4300                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1569                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          365119                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          218748                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1475793                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         5303                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         2204                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         495240                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         383310                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         4300                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1569                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         365119                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         218748                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1475793                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000189                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000907                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015142                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.029284                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.009000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.038846                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018284                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.883357                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800426                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.854628                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.856476                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.901304                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.873745                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.567616                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.565025                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.566748                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000189                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000907                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015142                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.261543                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.000637                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.009000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.239065                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.110679                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000189                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000907                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015142                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.261543                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.000637                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.009000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.239065                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.110679                       # miss rate for overall accesses
+system.l2c.overall_misses::cpu1.inst             3347                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            53648                       # number of overall misses
+system.l2c.overall_misses::total               163287                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         3875                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1922                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         428470                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         181580                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5334                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1734                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         433858                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         174787                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1231560                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       567807                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           567807                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         5543                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4967                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           10510                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          878                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          521                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1399                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       150612                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        98584                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249196                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         3875                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1922                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          428470                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          332192                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5334                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1734                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          433858                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          273371                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1480756                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         3875                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1922                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         428470                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         332192                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5334                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1734                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         433858                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         273371                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1480756                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.017345                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.035202                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.007715                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.030185                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.018232                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.889771                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.866519                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.878782                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.843964                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.940499                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.879914                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.613902                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.490668                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.565150                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.017345                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.297578                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007715                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.196246                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.110273                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000258                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001561                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.017345                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.297578                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007715                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.196246                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.110273                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -269,8 +257,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               65563                       # number of writebacks
-system.l2c.writebacks::total                    65563                       # number of writebacks
+system.l2c.writebacks::writebacks               65559                       # number of writebacks
+system.l2c.writebacks::total                    65559                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -280,27 +268,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9312139                       # DTB read hits
-system.cpu0.dtb.read_misses                      5476                       # DTB read misses
-system.cpu0.dtb.write_hits                    6895585                       # DTB write hits
-system.cpu0.dtb.write_misses                     1137                       # DTB write misses
+system.cpu0.dtb.read_hits                     7975768                       # DTB read hits
+system.cpu0.dtb.read_misses                      3611                       # DTB read misses
+system.cpu0.dtb.write_hits                    5966574                       # DTB write hits
+system.cpu0.dtb.write_misses                      672                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2449                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2004                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   187                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   135                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9317615                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6896722                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7979379                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5967246                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         16207724                       # DTB hits
-system.cpu0.dtb.misses                           6613                       # DTB misses
-system.cpu0.dtb.accesses                     16214337                       # DTB accesses
-system.cpu0.itb.inst_hits                    34683994                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3170                       # ITB inst misses
+system.cpu0.dtb.hits                         13942342                       # DTB hits
+system.cpu0.dtb.misses                           4283                       # DTB misses
+system.cpu0.dtb.accesses                     13946625                       # DTB accesses
+system.cpu0.itb.inst_hits                    30238804                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2175                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -309,74 +297,74 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1558                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1499                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                34687164                       # ITB inst accesses
-system.cpu0.itb.hits                         34683994                       # DTB hits
-system.cpu0.itb.misses                           3170                       # DTB misses
-system.cpu0.itb.accesses                     34687164                       # DTB accesses
-system.cpu0.numCycles                      1823259919                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                30240979                       # ITB inst accesses
+system.cpu0.itb.hits                         30238804                       # DTB hits
+system.cpu0.itb.misses                           2175                       # DTB misses
+system.cpu0.itb.accesses                     30240979                       # DTB accesses
+system.cpu0.numCycles                      1823633059                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   33900598                       # Number of instructions committed
-system.cpu0.committedOps                     44786074                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             39685287                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5074                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1436598                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4494112                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    39685287                       # number of integer instructions
-system.cpu0.num_fp_insts                         5074                       # number of float instructions
-system.cpu0.num_int_register_reads          201262894                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          42034263                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3706                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1372                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     16978573                       # number of memory refs
-system.cpu0.num_load_insts                    9760184                       # Number of load instructions
-system.cpu0.num_store_insts                   7218389                       # Number of store instructions
-system.cpu0.num_idle_cycles              1777623684.411826                       # Number of idle cycles
-system.cpu0.num_busy_cycles              45636234.588174                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025030                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974970                       # Percentage of idle cycles
+system.cpu0.committedInsts                   29750005                       # Number of instructions committed
+system.cpu0.committedOps                     39129633                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             34471201                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5449                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1241903                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4025450                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    34471201                       # number of integer instructions
+system.cpu0.num_fp_insts                         5449                       # number of float instructions
+system.cpu0.num_int_register_reads          175121947                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36551788                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4535                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     14626951                       # number of memory refs
+system.cpu0.num_load_insts                    8357226                       # Number of load instructions
+system.cpu0.num_store_insts                   6269725                       # Number of store instructions
+system.cpu0.num_idle_cycles              1783968822.941743                       # Number of idle cycles
+system.cpu0.num_busy_cycles              39664236.058257                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.021750                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.978250                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   58955                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                497178                       # number of replacements
-system.cpu0.icache.tagsinuse               511.019581                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                34187980                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                497690                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 68.693323                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           64536851000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   511.019581                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.998085                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.998085                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34187980                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34187980                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34187980                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34187980                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34187980                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34187980                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       497690                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       497690                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       497690                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        497690                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       497690                       # number of overall misses
-system.cpu0.icache.overall_misses::total       497690                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     34685670                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     34685670                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     34685670                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     34685670                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     34685670                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     34685670                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014349                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014349                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014349                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014349                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014349                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014349                       # miss rate for overall accesses
+system.cpu0.kern.inst.quiesce                   49966                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                428547                       # number of replacements
+system.cpu0.icache.tagsinuse               511.020000                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                29811115                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                429059                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 69.480223                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           64537139000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   511.020000                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.998086                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.998086                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29811115                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29811115                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29811115                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29811115                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29811115                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29811115                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       429059                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       429059                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       429059                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        429059                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       429059                       # number of overall misses
+system.cpu0.icache.overall_misses::total       429059                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30240174                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     30240174                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30240174                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     30240174                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30240174                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     30240174                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014188                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014188                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014188                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014188                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014188                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014188                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -385,66 +373,64 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks        31457                       # number of writebacks
-system.cpu0.icache.writebacks::total            31457                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                380425                       # number of replacements
-system.cpu0.dcache.tagsinuse               495.308430                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                14671885                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                380937                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 38.515253                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                323609                       # number of replacements
+system.cpu0.dcache.tagsinuse               494.763091                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                12467604                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                323981                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 38.482516                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              22115000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   495.308430                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.967399                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.967399                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7779192                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7779192                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      6519856                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       6519856                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       173153                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       173153                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       175464                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       175464                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     14299048                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        14299048                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     14299048                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       14299048                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       237170                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       237170                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       185374                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       185374                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9761                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9761                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7396                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7396                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       422544                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        422544                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       422544                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       422544                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8016362                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8016362                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6705230                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6705230                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       182914                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       182914                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       182860                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       182860                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14721592                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14721592                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14721592                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14721592                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029586                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.029586                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027646                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.027646                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053364                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053364                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.040446                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.040446                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028702                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028702                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028702                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.028702                       # miss rate for overall accesses
+system.cpu0.dcache.occ_blocks::cpu0.data   494.763091                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.966334                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.966334                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6512305                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6512305                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5630881                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5630881                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       151619                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       151619                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       153180                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       153180                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12143186                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12143186                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12143186                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12143186                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       197167                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       197167                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       167342                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       167342                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9062                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9062                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7469                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7469                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       364509                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        364509                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       364509                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       364509                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6709472                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6709472                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5798223                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5798223                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       160681                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       160681                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160649                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       160649                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12507695                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12507695                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12507695                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12507695                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.029386                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.028861                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.028861                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056397                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056397                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.046493                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046493                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029143                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029143                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029143                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029143                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -453,32 +439,32 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       353901                       # number of writebacks
-system.cpu0.dcache.writebacks::total           353901                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       300958                       # number of writebacks
+system.cpu0.dcache.writebacks::total           300958                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6036043                       # DTB read hits
-system.cpu1.dtb.read_misses                      1895                       # DTB read misses
-system.cpu1.dtb.write_hits                    4565126                       # DTB write hits
-system.cpu1.dtb.write_misses                     1147                       # DTB write misses
+system.cpu1.dtb.read_hits                     7364781                       # DTB read hits
+system.cpu1.dtb.read_misses                      3705                       # DTB read misses
+system.cpu1.dtb.write_hits                    5489656                       # DTB write hits
+system.cpu1.dtb.write_misses                     1595                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1364                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1788                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    95                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   145                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      185                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6037938                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4566273                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7368486                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5491251                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         10601169                       # DTB hits
-system.cpu1.dtb.misses                           3042                       # DTB misses
-system.cpu1.dtb.accesses                     10604211                       # DTB accesses
-system.cpu1.itb.inst_hits                    26944447                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1203                       # ITB inst misses
+system.cpu1.dtb.hits                         12854437                       # DTB hits
+system.cpu1.dtb.misses                           5300                       # DTB misses
+system.cpu1.dtb.accesses                     12859737                       # DTB accesses
+system.cpu1.itb.inst_hits                    32412306                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2200                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -487,74 +473,74 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1228                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1327                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                26945650                       # ITB inst accesses
-system.cpu1.itb.hits                         26944447                       # DTB hits
-system.cpu1.itb.misses                           1203                       # DTB misses
-system.cpu1.itb.accesses                     26945650                       # DTB accesses
-system.cpu1.numCycles                      1822760078                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                32414506                       # ITB inst accesses
+system.cpu1.itb.hits                         32412306                       # DTB hits
+system.cpu1.itb.misses                           2200                       # DTB misses
+system.cpu1.itb.accesses                     32414506                       # DTB accesses
+system.cpu1.numCycles                      1824154149                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   26714987                       # Number of instructions committed
-system.cpu1.committedOps                     33555986                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             30087808                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5643                       # Number of float alu accesses
-system.cpu1.num_func_calls                     761024                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3301562                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    30087808                       # number of integer instructions
-system.cpu1.num_fp_insts                         5643                       # number of float instructions
-system.cpu1.num_int_register_reads          152234781                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          32495677                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3915                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1728                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     11031013                       # number of memory refs
-system.cpu1.num_load_insts                    6247466                       # Number of load instructions
-system.cpu1.num_store_insts                   4783547                       # Number of store instructions
-system.cpu1.num_idle_cycles              1788952556.347001                       # Number of idle cycles
-system.cpu1.num_busy_cycles              33807521.652999                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.018547                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.981453                       # Percentage of idle cycles
+system.cpu1.committedInsts                   31875965                       # Number of instructions committed
+system.cpu1.committedOps                     40213707                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             35797832                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  4436                       # Number of float alu accesses
+system.cpu1.num_func_calls                     955227                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      4028429                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    35797832                       # number of integer instructions
+system.cpu1.num_fp_insts                         4436                       # number of float instructions
+system.cpu1.num_int_register_reads          181634271                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          39007898                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3022                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1416                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     13370713                       # number of memory refs
+system.cpu1.num_load_insts                    7642673                       # Number of load instructions
+system.cpu1.num_store_insts                   5728040                       # Number of store instructions
+system.cpu1.num_idle_cycles              1783362859.317266                       # Number of idle cycles
+system.cpu1.num_busy_cycles              40791289.682734                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.022362                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.977638                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   31471                       # number of quiesce instructions executed
-system.cpu1.icache.replacements                365832                       # number of replacements
-system.cpu1.icache.tagsinuse               475.430525                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                26579068                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                366344                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 72.552213                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           69967043000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   475.430525                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.928575                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.928575                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     26579068                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       26579068                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     26579068                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        26579068                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     26579068                       # number of overall hits
-system.cpu1.icache.overall_hits::total       26579068                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       366344                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       366344                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       366344                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        366344                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       366344                       # number of overall misses
-system.cpu1.icache.overall_misses::total       366344                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     26945412                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     26945412                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     26945412                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     26945412                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     26945412                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     26945412                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013596                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.013596                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013596                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.013596                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013596                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.013596                       # miss rate for overall accesses
+system.cpu1.kern.inst.quiesce                   40379                       # number of quiesce instructions executed
+system.cpu1.icache.replacements                433942                       # number of replacements
+system.cpu1.icache.tagsinuse               475.447912                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                31979125                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                434454                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 73.607620                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           69967763000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   475.447912                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.928609                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.928609                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     31979125                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       31979125                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     31979125                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        31979125                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     31979125                       # number of overall hits
+system.cpu1.icache.overall_hits::total       31979125                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       434454                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       434454                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       434454                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        434454                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       434454                       # number of overall misses
+system.cpu1.icache.overall_misses::total       434454                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     32413579                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     32413579                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     32413579                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     32413579                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     32413579                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     32413579                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013403                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.013403                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013403                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.013403                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013403                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.013403                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -563,66 +549,64 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks        15197                       # number of writebacks
-system.cpu1.icache.writebacks::total            15197                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                236700                       # number of replacements
-system.cpu1.dcache.tagsinuse               447.071707                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 9515102                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                237061                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 40.137779                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           67292773000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   447.071707                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.873187                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.873187                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      5742078                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        5742078                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3635346                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3635346                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        56591                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        56591                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        56639                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        56639                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      9377424                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         9377424                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      9377424                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        9377424                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       159026                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       159026                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       108254                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       108254                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10539                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        10539                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10435                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10435                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       267280                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        267280                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       267280                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       267280                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      5901104                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      5901104                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3743600                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3743600                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        67130                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        67130                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        67074                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        67074                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      9644704                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      9644704                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      9644704                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      9644704                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.026949                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.026949                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028917                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.028917                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156994                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.156994                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.155574                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.155574                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027713                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027713                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027713                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.027713                       # miss rate for overall accesses
+system.cpu1.dcache.replacements                294289                       # number of replacements
+system.cpu1.dcache.tagsinuse               447.573682                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                11707745                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                294801                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 39.714061                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           67293493000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   447.573682                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.874167                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.874167                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      7002209                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        7002209                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4520313                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4520313                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77954                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        77954                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79030                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        79030                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11522522                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11522522                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11522522                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11522522                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       198275                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       198275                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       125920                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       125920                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11251                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11251                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10139                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10139                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       324195                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        324195                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       324195                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       324195                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7200484                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7200484                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4646233                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4646233                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89205                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        89205                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        89169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     11846717                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     11846717                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     11846717                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     11846717                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027536                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.027536                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027102                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.027102                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126125                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126125                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113705                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113705                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027366                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027366                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027366                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.027366                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -631,8 +615,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       212705                       # number of writebacks
-system.cpu1.dcache.writebacks::total           212705                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       266849                       # number of writebacks
+system.cpu1.dcache.writebacks::total           266849                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index f14835c6b..59476048e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -191,7 +191,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -252,9 +252,9 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
@@ -665,7 +665,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 4dbfc774f..5f92f06af 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:35:36
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 00:54:29
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2332330037000 because m5_exit instruction encountered
+Exiting @ tick 2332810264000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 176436ee7..e8bc29aac 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,54 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332330                       # Number of seconds simulated
-sim_ticks                                2332330037000                       # Number of ticks simulated
-final_tick                               2332330037000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.332810                       # Number of seconds simulated
+sim_ticks                                2332810264000                       # Number of ticks simulated
+final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1988795                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2567201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            78099767101                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 382744                       # Number of bytes of host memory used
-host_seconds                                    29.86                       # Real time elapsed on the host
-sim_insts                                    59392246                       # Number of instructions simulated
-sim_ops                                      76665494                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1498673                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1927201                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57874436068                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388524                       # Number of bytes of host memory used
+host_seconds                                    40.31                       # Real time elapsed on the host
+sim_insts                                    60408639                       # Number of instructions simulated
+sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            704992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9071568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450416                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       704992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703040                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            705120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9071632                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            121450608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       705120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3703232                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6718856                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6719048                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17218                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141777                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118171                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57860                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17220                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141778                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14118174                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57863                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811814                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47880592                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               811817                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47870736                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker            137                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               302269                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3889487                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52072569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          302269                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302269                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1293049                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880748                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47880592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               302262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3888714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52061931                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          302262                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             302262                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1587455                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1292782                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2880238                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1587455                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47870736                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           137                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            82                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              302269                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5182536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54953317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              302262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5181496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54942169                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst            9
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         62240                       # number of replacements
-system.l2c.tagsinuse                     50004.786190                       # Cycle average of tags in use
-system.l2c.total_refs                         1717775                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        127625                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         13.459549                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2316513323500                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36897.037256                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker        2.960071                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.993930                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           7014.608709                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6089.186223                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.563004                       # Average percentage of cache occupancy
+system.l2c.replacements                         62243                       # number of replacements
+system.l2c.tagsinuse                     50007.272909                       # Cycle average of tags in use
+system.l2c.total_refs                         1669922                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127628                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.084292                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2316901489000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36899.582990                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        2.960148                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.993931                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           7014.720482                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6089.015357                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.563043                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.dtb.walker       0.000045                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.107034                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.092914                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.763012                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          7534                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          3151                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              838895                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              364444                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1214024                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          642748                       # number of Writeback hits
-system.l2c.Writeback_hits::total               642748                       # number of Writeback hits
+system.l2c.occ_percent::cpu.inst             0.107036                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.092911                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.763050                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          7507                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3129                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              838871                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              366771                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1216278                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          592643                       # number of Writeback hits
+system.l2c.Writeback_hits::total               592643                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            113737                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               113737                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           7534                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           3151                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               838895                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               478181                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1327761                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          7534                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          3151                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              838895                       # number of overall hits
-system.l2c.overall_hits::cpu.data              478181                       # number of overall hits
-system.l2c.overall_hits::total                1327761                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu.data            113739                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113739                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           7507                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3129                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               838871                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               480510                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1330017                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          7507                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3129                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              838871                       # number of overall hits
+system.l2c.overall_hits::cpu.data              480510                       # number of overall hits
+system.l2c.overall_hits::total                1330017                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             10602                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data              9870                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20480                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2918                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2918                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133469                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133469                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu.inst             10604                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data              9871                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20483                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2919                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2919                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133468                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133468                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              10602                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              10604                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.data             143339                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153949                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153951                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             10602                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             10604                       # number of overall misses
 system.l2c.overall_misses::cpu.data            143339                       # number of overall misses
-system.l2c.overall_misses::total               153949                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu.dtb.walker         7539                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         3154                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          849497                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          374314                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1234504                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       642748                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           642748                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2944                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2944                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        247206                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247206                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         7539                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           849497                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           621520                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1481710                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         7539                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          849497                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          621520                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1481710                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000951                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012480                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026368                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016590                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.991168                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991168                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.539910                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.539910                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000951                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012480                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.230627                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103900                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000951                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012480                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.230627                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103900                       # miss rate for overall accesses
+system.l2c.overall_misses::total               153951                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu.dtb.walker         7512                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3132                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          849475                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          376642                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1236761                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       592643                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           592643                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2945                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2945                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        247207                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247207                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         7512                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3132                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           849475                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           623849                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1483968                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         7512                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3132                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          849475                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          623849                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1483968                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000958                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012483                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026208                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016562                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.991171                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991171                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.539904                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.539904                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000958                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012483                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.229766                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103743                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000666                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000958                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012483                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.229766                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103743                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57860                       # number of writebacks
-system.l2c.writebacks::total                    57860                       # number of writebacks
+system.l2c.writebacks::writebacks               57863                       # number of writebacks
+system.l2c.writebacks::total                    57863                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -177,26 +177,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14971229                       # DTB read hits
-system.cpu.dtb.read_misses                       7293                       # DTB read misses
-system.cpu.dtb.write_hits                    11217018                       # DTB write hits
+system.cpu.dtb.read_hits                     14971214                       # DTB read hits
+system.cpu.dtb.read_misses                       7294                       # DTB read misses
+system.cpu.dtb.write_hits                    11217004                       # DTB write hits
 system.cpu.dtb.write_misses                      2181                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3492                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3496                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 14978522                       # DTB read accesses
-system.cpu.dtb.write_accesses                11219199                       # DTB write accesses
+system.cpu.dtb.read_accesses                 14978508                       # DTB read accesses
+system.cpu.dtb.write_accesses                11219185                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26188247                       # DTB hits
-system.cpu.dtb.misses                            9474                       # DTB misses
-system.cpu.dtb.accesses                      26197721                       # DTB accesses
-system.cpu.itb.inst_hits                     60403303                       # ITB inst hits
+system.cpu.dtb.hits                          26188218                       # DTB hits
+system.cpu.dtb.misses                            9475                       # DTB misses
+system.cpu.dtb.accesses                      26197693                       # DTB accesses
+system.cpu.itb.inst_hits                     61431840                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -213,67 +213,67 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 60407774                       # ITB inst accesses
-system.cpu.itb.hits                          60403303                       # DTB hits
+system.cpu.itb.inst_accesses                 61436311                       # ITB inst accesses
+system.cpu.itb.hits                          61431840                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      60407774                       # DTB accesses
-system.cpu.numCycles                       4664583062                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61436311                       # DTB accesses
+system.cpu.numCycles                       4665543516                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    59392246                       # Number of instructions committed
-system.cpu.committedOps                      76665494                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68281415                       # Number of integer alu accesses
+system.cpu.committedInsts                    60408639                       # Number of instructions committed
+system.cpu.committedOps                      77681819                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              68795605                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2136013                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7647793                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68281415                       # number of integer instructions
+system.cpu.num_func_calls                     2136008                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7904929                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     68795605                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           345981857                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           73062916                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           349324274                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           74103608                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27361692                       # number of memory refs
-system.cpu.num_load_insts                    15639569                       # Number of load instructions
-system.cpu.num_store_insts                   11722123                       # Number of store instructions
-system.cpu.num_idle_cycles               4586814358.980880                       # Number of idle cycles
-system.cpu.num_busy_cycles               77768703.019120                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016672                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983328                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      27361637                       # number of memory refs
+system.cpu.num_load_insts                    15639527                       # Number of load instructions
+system.cpu.num_store_insts                   11722110                       # Number of store instructions
+system.cpu.num_idle_cycles               4586746360.692756                       # Number of idle cycles
+system.cpu.num_busy_cycles               78797155.307244                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.016889                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.983111                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 850612                       # number of replacements
-system.cpu.icache.tagsinuse                511.678549                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59554939                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 851124                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  69.972106                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             5708999000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.678549                       # Average occupied blocks per requestor
+system.cpu.icache.replacements                 850590                       # number of replacements
+system.cpu.icache.tagsinuse                511.678593                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 60583498                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 851102                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  71.182418                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             5709383000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.678593                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59554939                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59554939                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59554939                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59554939                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59554939                       # number of overall hits
-system.cpu.icache.overall_hits::total        59554939                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       851124                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        851124                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       851124                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         851124                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       851124                       # number of overall misses
-system.cpu.icache.overall_misses::total        851124                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60406063                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60406063                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60406063                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60406063                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60406063                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60406063                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014090                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014090                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014090                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014090                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014090                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014090                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     60583498                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60583498                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60583498                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60583498                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60583498                       # number of overall hits
+system.cpu.icache.overall_hits::total        60583498                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       851102                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        851102                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       851102                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         851102                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       851102                       # number of overall misses
+system.cpu.icache.overall_misses::total        851102                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     61434600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61434600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61434600                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61434600                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61434600                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61434600                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013854                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013854                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013854                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013854                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013854                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013854                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -282,58 +282,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        50093                       # number of writebacks
-system.cpu.icache.writebacks::total             50093                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 623347                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997030                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 23628362                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 623859                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  37.874523                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 623337                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997031                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 23628343                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 623849                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.875100                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997030                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.997031                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13180074                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13180074                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9962087                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9962087                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236035                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236035                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247222                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247222                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23142161                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23142161                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23142161                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23142161                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       365465                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        365465                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250150                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11188                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11188                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       615615                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         615615                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       615615                       # number of overall misses
-system.cpu.dcache.overall_misses::total        615615                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     13545539                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13545539                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10212237                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10212237                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247223                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247223                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247222                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247222                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23757776                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23757776                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23757776                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23757776                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13180066                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13180066                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9962072                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9962072                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236039                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236039                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247221                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      23142138                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23142138                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23142138                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23142138                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       365459                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        365459                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250152                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250152                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11183                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       615611                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         615611                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       615611                       # number of overall misses
+system.cpu.dcache.overall_misses::total        615611                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     13545525                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13545525                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10212224                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10212224                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247222                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247222                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247221                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247221                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23757749                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23757749                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23757749                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23757749                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026980                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045255                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045255                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045235                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
@@ -346,8 +344,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       592655                       # number of writebacks
-system.cpu.dcache.writebacks::total            592655                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       592643                       # number of writebacks
+system.cpu.dcache.writebacks::total            592643                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 363bd4c66..f88222537 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -361,7 +361,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 70032b595..3225b7372 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 15:21:03
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 00:58:01
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1171612619000 because m5_exit instruction encountered
+Exiting @ tick 1172544977000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index bf3a52c45..2693ffabe 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,71 +1,71 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.171613                       # Number of seconds simulated
-sim_ticks                                1171612619000                       # Number of ticks simulated
-final_tick                               1171612619000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.172545                       # Number of seconds simulated
+sim_ticks                                1172544977000                       # Number of ticks simulated
+final_tick                               1172544977000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639669                       # Simulator instruction rate (inst/s)
-host_op_rate                                   818158                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12399663305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384708                       # Number of bytes of host memory used
-host_seconds                                    94.49                       # Real time elapsed on the host
-sim_insts                                    60440687                       # Number of instructions simulated
-sim_ops                                      77305655                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 706392                       # Simulator instruction rate (inst/s)
+host_op_rate                                   900233                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13469238975                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 389548                       # Number of bytes of host memory used
+host_seconds                                    87.05                       # Real time elapsed on the host
+sim_insts                                    61493926                       # Number of instructions simulated
+sim_ops                                      78368454                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           395940                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4717108                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           394788                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4717236                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           321948                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4794672                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60561764                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       395940                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       321948                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          717888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4107520                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           322588                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4794736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             60561444                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       394788                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       322588                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          717376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4107264                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7134864                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7134608                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12405                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73777                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12387                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73779                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5112                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             74943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6457700                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64180                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5122                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74944                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6457695                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64176                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821016                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        42959291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               821012                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        42925132                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker           109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              337944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             4026167                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              274790                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4092370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51690945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         337944                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         274790                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             612735                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3505869                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14510                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2569402                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6089781                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3505869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       42959291                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              336693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             4023075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           218                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              275118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4089170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51649570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         336693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         275118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             611811                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3502863                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14498                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2567359                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6084720                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3502863                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       42925132                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker          109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             337944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            4040677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             274790                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6661772                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57780726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             336693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            4037573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          218                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             275118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6656529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57734290                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -84,237 +84,237 @@ system.realview.nvmem.bw_inst_read::total           58                       # I
 system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              58                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         69306                       # number of replacements
-system.l2c.tagsinuse                     52659.016481                       # Cycle average of tags in use
-system.l2c.total_refs                         1685686                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        134505                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         12.532516                       # Average number of references to valid blocks.
+system.l2c.replacements                         69301                       # number of replacements
+system.l2c.tagsinuse                     52667.431766                       # Cycle average of tags in use
+system.l2c.total_refs                         1645571                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        134500                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         12.234729                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        39891.573384                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks        39900.139395                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu0.dtb.walker       0.000282                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.001243                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          3742.951187                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4216.912189                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker       2.733680                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          2750.765696                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          2054.078820                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.608697                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.itb.walker       0.001242                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3730.644795                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4216.663550                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       2.734150                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2763.076938                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2054.171414                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.608828                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.057113                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.064345                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.056925                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.064341                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.dtb.walker      0.000042                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.041973                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.031343                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.803513                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4104                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1844                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             401511                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             204865                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5725                       # number of ReadReq hits
+system.l2c.occ_percent::cpu1.inst            0.042161                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.031344                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.803641                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4102                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1845                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             402958                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             205810                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         5738                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.itb.walker         1962                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             448415                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             143316                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1211742                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          616867                       # number of Writeback hits
-system.l2c.Writeback_hits::total               616867                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1168                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             575                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1743                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           210                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           101                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               311                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            56775                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            52975                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109750                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4104                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1844                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              401511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              261640                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5725                       # number of demand (read+write) hits
+system.l2c.ReadReq_hits::cpu1.inst             449307                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             144268                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1215990                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          572486                       # number of Writeback hits
+system.l2c.Writeback_hits::total               572486                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1132                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             588                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1720                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           206                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           104                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               310                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            56781                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            53046                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109827                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4102                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1845                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              402958                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              262591                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5738                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.itb.walker          1962                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              448415                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              196291                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1321492                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4104                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1844                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             401511                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             261640                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5725                       # number of overall hits
+system.l2c.demand_hits::cpu1.inst              449307                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              197314                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1325817                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4102                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1845                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             402958                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             262591                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5738                       # number of overall hits
 system.l2c.overall_hits::cpu1.itb.walker         1962                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             448415                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             196291                       # number of overall hits
-system.l2c.overall_hits::total                1321492                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             449307                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             197314                       # number of overall hits
+system.l2c.overall_hits::total                1325817                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5773                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             7865                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             5755                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             7866                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             5025                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             5035                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data             3646                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22316                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4668                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3562                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              8230                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          564                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          479                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1043                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          67164                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          72393                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139557                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::total                22309                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          4696                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          3601                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8297                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          568                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          498                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1066                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          67165                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          72394                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139559                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5773                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             75029                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5755                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             75031                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5025                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             76039                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                161873                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5035                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             76040                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                161868                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5773                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            75029                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             5755                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            75031                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5025                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            76039                       # number of overall misses
-system.l2c.overall_misses::total               161873                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5035                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            76040                       # number of overall misses
+system.l2c.overall_misses::total               161868                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        52000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    300844500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    409319998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    299823500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    409333998                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       208500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    262047000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    190080500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1162656498                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     28957997                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     27214000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     56171997                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3588000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6004000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      9592000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3493801976                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   3769288495                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7263090471                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    262768000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    190087500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1162377498                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     29968997                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27317000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     57285997                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3654000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6100000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      9754000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3493697466                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   3769025494                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7262722960                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.dtb.walker        52000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    300844500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3903121974                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    299823500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3903031464                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker       208500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    262047000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   3959368995                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8425746969                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    262768000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   3959112994                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8425100458                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.dtb.walker        52000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    300844500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3903121974                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    299823500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3903031464                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker       208500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    262047000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   3959368995                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8425746969                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4105                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1846                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         407284                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         212730                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5729                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu1.inst    262768000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   3959112994                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8425100458                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4103                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1847                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         408713                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         213676                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5742                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker         1962                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         453440                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         146962                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1234058                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       616867                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           616867                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5836                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4137                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            9973                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         454342                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         147914                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1238299                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       572486                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           572486                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         5828                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4189                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           10017                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data          774                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          580                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1354                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       123939                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       125368                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249307                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4105                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1846                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          407284                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          336669                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5729                       # number of demand (read+write) accesses
+system.l2c.SCUpgradeReq_accesses::cpu1.data          602                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1376                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123946                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       125440                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249386                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4103                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1847                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          408713                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          337622                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5742                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.itb.walker         1962                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          453440                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          272330                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1483365                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4105                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1846                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         407284                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         336669                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5729                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          454342                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          273354                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1487685                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4103                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1847                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         408713                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         337622                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5742                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.itb.walker         1962                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         453440                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         272330                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1483365                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         454342                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         273354                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1487685                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014174                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036972                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014081                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036813                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.011082                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024809                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018083                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.799863                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.861010                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.825228                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.728682                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.825862                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.770310                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.541912                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.577444                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.559780                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024649                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.018016                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805765                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.859632                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.828292                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.733850                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.827243                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.774709                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.541889                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.577121                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.559610                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014174                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.222857                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014081                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.222234                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.011082                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.279216                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.109126                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.278174                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.108805                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014174                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.222857                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014081                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.222234                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.011082                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.279216                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.109126                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.278174                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.108805                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52112.333276                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52043.229243                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52097.914857                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52038.392830                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52125                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52148.656716                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52133.982447                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52099.681753                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6203.512639                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7640.089837                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6825.273026                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6361.702128                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12534.446764                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  9196.548418                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52018.968138                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52067.029892                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52043.899417                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52188.282026                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52135.902359                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52103.523152                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6381.813671                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7585.948348                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6904.422924                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6433.098592                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12248.995984                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  9150.093809                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52016.637624                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52062.677763                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52040.520210                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52112.333276                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52021.511336                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52097.914857                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52018.918367                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52148.656716                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52070.240206                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52051.589635                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52188.282026                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52066.188769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52049.203413                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52112.333276                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52021.511336                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52097.914857                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52018.918367                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52148.656716                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52070.240206                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52051.589635                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52188.282026                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52066.188769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52049.203413                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -323,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               64180                       # number of writebacks
-system.l2c.writebacks::total                    64180                       # number of writebacks
+system.l2c.writebacks::writebacks               64176                       # number of writebacks
+system.l2c.writebacks::total                    64176                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -333,149 +333,149 @@ system.l2c.overall_mshr_hits::cpu0.inst             1                       # nu
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5772                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7865                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5754                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7866                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5025                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5035                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data         3646                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22315                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         4668                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3562                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8230                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          564                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          479                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67164                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72393                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139557                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           22308                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         4696                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3601                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8297                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          568                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          498                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1066                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        67165                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        72394                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139559                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5772                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        75029                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5754                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        75031                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5025                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        76039                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           161872                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5035                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        76040                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           161867                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5772                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        75029                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5754                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        75031                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5025                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        76039                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          161872                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5035                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        76040                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          161867                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    231552000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    314935000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    230747000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    314937000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    201743000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    146326000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    894836000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    186889000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    142710000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    329599000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22593000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19208000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     41801000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2687800500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2900558000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5588358500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    202344000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    146333000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    894641000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    187986000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    144285000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    332271000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22750000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19953000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     42703000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2687673000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2900282000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5587955000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    231552000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   3002735500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    230747000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3002610000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    201743000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3046884000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6483194500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    202344000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3046615000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6482596000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    231552000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   3002735500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    230747000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3002610000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    201743000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3046884000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6483194500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    202344000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3046615000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6482596000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9312662000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9314941499                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122159781000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131741924000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    694882000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30588601000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31283483000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122157234000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131741656499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    694839000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30621237500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31316076500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10007544000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10009780499                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152748382000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163025407000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163057732999                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036972                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036813                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024809                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018083                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.799863                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.861010                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.825228                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.728682                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825862                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.770310                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.541912                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577444                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.559780                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024649                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.018015                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.805765                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.859632                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.828292                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.733850                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.827243                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.774709                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.541889                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577121                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.559610                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.222857                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222234                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.279216                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.109125                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.278174                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.108805                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.222857                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222234                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.279216                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.109125                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.278174                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.108805                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40051.364658                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40048.904347                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40051.364658                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40048.904347                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -498,9 +498,9 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7077919                       # DTB read hits
-system.cpu0.dtb.read_misses                      3740                       # DTB read misses
-system.cpu0.dtb.write_hits                    5661726                       # DTB write hits
+system.cpu0.dtb.read_hits                     7082876                       # DTB read hits
+system.cpu0.dtb.read_misses                      3736                       # DTB read misses
+system.cpu0.dtb.write_hits                    5665319                       # DTB write hits
 system.cpu0.dtb.write_misses                      804                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
@@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults                        0                       # Nu
 system.cpu0.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7081659                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5662530                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 7086612                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5666123                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12739645                       # DTB hits
-system.cpu0.dtb.misses                           4544                       # DTB misses
-system.cpu0.dtb.accesses                     12744189                       # DTB accesses
-system.cpu0.itb.inst_hits                    29451654                       # ITB inst hits
+system.cpu0.dtb.hits                         12748195                       # DTB hits
+system.cpu0.dtb.misses                           4540                       # DTB misses
+system.cpu0.dtb.accesses                     12752735                       # DTB accesses
+system.cpu0.itb.inst_hits                    29606138                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                29453859                       # ITB inst accesses
-system.cpu0.itb.hits                         29451654                       # DTB hits
+system.cpu0.itb.inst_accesses                29608343                       # ITB inst accesses
+system.cpu0.itb.hits                         29606138                       # DTB hits
 system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     29453859                       # DTB accesses
-system.cpu0.numCycles                      2343225238                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     29608343                       # DTB accesses
+system.cpu0.numCycles                      2345089954                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   28759206                       # Number of instructions committed
-system.cpu0.committedOps                     37112849                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33058293                       # Number of integer alu accesses
+system.cpu0.committedInsts                   28907917                       # Number of instructions committed
+system.cpu0.committedOps                     37265600                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33149705                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1242118                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4322812                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33058293                       # number of integer instructions
+system.cpu0.num_func_calls                    1243107                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4358822                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33149705                       # number of integer instructions
 system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          189772382                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36110779                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          190344582                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36275228                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13408219                       # number of memory refs
-system.cpu0.num_load_insts                    7415624                       # Number of load instructions
-system.cpu0.num_store_insts                   5992595                       # Number of store instructions
-system.cpu0.num_idle_cycles              2203054927.350120                       # Number of idle cycles
-system.cpu0.num_busy_cycles              140170310.649880                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.059819                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.940181                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     13418689                       # number of memory refs
+system.cpu0.num_load_insts                    7420825                       # Number of load instructions
+system.cpu0.num_store_insts                   5997864                       # Number of store instructions
+system.cpu0.num_idle_cycles              2204555139.350120                       # Number of idle cycles
+system.cpu0.num_busy_cycles              140534814.649880                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.059927                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.940073                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   46686                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                408292                       # number of replacements
-system.cpu0.icache.tagsinuse               509.494086                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                29042833                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                408804                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 71.043417                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           75128321000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   509.494086                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.995106                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.995106                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29042833                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29042833                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29042833                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29042833                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29042833                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29042833                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       408804                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       408804                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       408804                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        408804                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       408804                       # number of overall misses
-system.cpu0.icache.overall_misses::total       408804                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6099412500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6099412500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6099412500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6099412500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6099412500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6099412500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     29451637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     29451637                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     29451637                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     29451637                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     29451637                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     29451637                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013881                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013881                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013881                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013881                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013881                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013881                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14920.138991                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14920.138991                       # average overall miss latency
+system.cpu0.kern.inst.quiesce                   46687                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                408797                       # number of replacements
+system.cpu0.icache.tagsinuse               509.495989                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                29196812                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                409309                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 71.331957                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           75128897000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   509.495989                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.995109                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.995109                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29196812                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29196812                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29196812                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29196812                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29196812                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29196812                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       409309                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       409309                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       409309                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        409309                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       409309                       # number of overall misses
+system.cpu0.icache.overall_misses::total       409309                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6108172000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6108172000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   6108172000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6108172000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   6108172000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6108172000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29606121                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29606121                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29606121                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29606121                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29606121                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29606121                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013825                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013825                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013825                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013825                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013825                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013825                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14923.131424                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14923.131424                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -615,122 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks        20827                       # number of writebacks
-system.cpu0.icache.writebacks::total            20827                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       408804                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       408804                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       408804                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       408804                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       408804                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       408804                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4872150503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4872150503                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4872150503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4872150503                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4872150503                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4872150503                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       409309                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       409309                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       409309                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       409309                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       409309                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       409309                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4879387500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4879387500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4879387500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4879387500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4879387500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4879387500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    351814000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013881                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013881                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013881                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013881                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013881                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013881                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013825                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013825                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013825                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                330880                       # number of replacements
-system.cpu0.dcache.tagsinuse               457.764906                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                12284019                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                331392                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 37.067941                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                330813                       # number of replacements
+system.cpu0.dcache.tagsinuse               457.939353                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                12292528                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                331325                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 37.101118                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle             664264000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   457.764906                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.894072                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.894072                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6607497                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6607497                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5356507                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5356507                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147994                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       147994                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149732                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149732                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11964004                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11964004                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11964004                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11964004                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       228069                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       228069                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141727                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       141727                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9289                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9289                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7498                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7498                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       369796                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        369796                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       369796                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       369796                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3436407000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3436407000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4917296000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   4917296000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100570500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    100570500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74480000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     74480000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8353703000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8353703000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8353703000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8353703000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6835566                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6835566                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5498234                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5498234                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157283                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157283                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157230                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       157230                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12333800                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12333800                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12333800                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12333800                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033365                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033365                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025777                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.025777                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059059                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059059                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047688                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047688                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029982                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029982                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029982                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029982                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9933.315551                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9933.315551                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720                       # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data   457.939353                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.894413                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.894413                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6612408                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6612408                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5360091                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5360091                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147992                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       147992                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149726                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149726                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11972499                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11972499                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11972499                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11972499                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       228125                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       228125                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       141749                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       141749                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9279                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9279                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7492                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7492                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       369874                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        369874                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       369874                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       369874                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3443081500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3443081500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4917870500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4917870500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100339500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    100339500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74628000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     74628000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8360952000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8360952000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8360952000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8360952000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6840533                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6840533                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5501840                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5501840                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157271                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157271                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12342373                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12342373                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12342373                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12342373                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033349                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033349                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025764                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025764                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059000                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059000                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047654                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047654                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029968                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029968                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029968                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029968                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9961.025093                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9961.025093                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -739,62 +737,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       306522                       # number of writebacks
-system.cpu0.dcache.writebacks::total           306522                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228069                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       228069                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141727                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       141727                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9289                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9289                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7492                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7492                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       369796                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       369796                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       369796                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       369796                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2751577168                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2751577168                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4491927564                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4491927564                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72683507                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72683507                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     51983021                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     51983021                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7243504732                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7243504732                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7243504732                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7243504732                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10423590500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10423590500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    819778500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    819778500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11243369000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11243369000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033365                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033365                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025777                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025777                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059059                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059059                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047650                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047650                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029982                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029982                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029982                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029982                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7824.685865                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7824.685865                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6938.470502                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6938.470502                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       306322                       # number of writebacks
+system.cpu0.dcache.writebacks::total           306322                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228125                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       228125                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141749                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141749                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9279                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9279                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7485                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7485                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       369874                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       369874                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       369874                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       369874                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2758091164                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2758091164                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4492431566                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4492431566                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72483506                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72483506                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     52154019                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     52154019                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7250522730                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7250522730                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7250522730                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7250522730                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10425846000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10425846000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    819721500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    819721500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11245567500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11245567500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033349                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033349                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025764                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025764                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047609                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047609                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029968                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029968                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029968                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029968                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7811.564393                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7811.564393                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6967.804810                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6967.804810                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -804,9 +802,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     8311872                       # DTB read hits
-system.cpu1.dtb.read_misses                      3663                       # DTB read misses
-system.cpu1.dtb.write_hits                    5828412                       # DTB write hits
+system.cpu1.dtb.read_hits                     8314117                       # DTB read hits
+system.cpu1.dtb.read_misses                      3669                       # DTB read misses
+system.cpu1.dtb.write_hits                    5830380                       # DTB write hits
 system.cpu1.dtb.write_misses                     1436                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
@@ -817,13 +815,13 @@ system.cpu1.dtb.align_faults                        0                       # Nu
 system.cpu1.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 8315535                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5829848                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 8317786                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5831816                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         14140284                       # DTB hits
-system.cpu1.dtb.misses                           5099                       # DTB misses
-system.cpu1.dtb.accesses                     14145383                       # DTB accesses
-system.cpu1.itb.inst_hits                    32285286                       # ITB inst hits
+system.cpu1.dtb.hits                         14144497                       # DTB hits
+system.cpu1.dtb.misses                           5105                       # DTB misses
+system.cpu1.dtb.accesses                     14149602                       # DTB accesses
+system.cpu1.itb.inst_hits                    33196626                       # ITB inst hits
 system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -840,79 +838,79 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                32287457                       # ITB inst accesses
-system.cpu1.itb.hits                         32285286                       # DTB hits
+system.cpu1.itb.inst_accesses                33198797                       # ITB inst accesses
+system.cpu1.itb.hits                         33196626                       # DTB hits
 system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     32287457                       # DTB accesses
-system.cpu1.numCycles                      2341739150                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     33198797                       # DTB accesses
+system.cpu1.numCycles                      2343593518                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   31681481                       # Number of instructions committed
-system.cpu1.committedOps                     40192806                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             36864445                       # Number of integer alu accesses
+system.cpu1.committedInsts                   32586009                       # Number of instructions committed
+system.cpu1.committedOps                     41102854                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             37326288                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     962202                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3487066                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    36864445                       # number of integer instructions
+system.cpu1.num_func_calls                     962171                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3714570                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    37326288                       # number of integer instructions
 system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          210742691                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          38544620                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          213739964                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          39466250                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14678127                       # number of memory refs
-system.cpu1.num_load_insts                    8633777                       # Number of load instructions
-system.cpu1.num_store_insts                   6044350                       # Number of store instructions
-system.cpu1.num_idle_cycles              1858809543.114650                       # Number of idle cycles
-system.cpu1.num_busy_cycles              482929606.885350                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.206227                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.793773                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14682267                       # number of memory refs
+system.cpu1.num_load_insts                    8636040                       # Number of load instructions
+system.cpu1.num_store_insts                   6046227                       # Number of store instructions
+system.cpu1.num_idle_cycles              1858750530.714142                       # Number of idle cycles
+system.cpu1.num_busy_cycles              484842987.285858                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.206880                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.793120                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   43917                       # number of quiesce instructions executed
-system.cpu1.icache.replacements                454429                       # number of replacements
-system.cpu1.icache.tagsinuse               478.358537                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                31830341                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                454941                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 69.965866                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           92993102000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   478.358537                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.934294                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.934294                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     31830341                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       31830341                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     31830341                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        31830341                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     31830341                       # number of overall hits
-system.cpu1.icache.overall_hits::total       31830341                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       454941                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       454941                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       454941                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        454941                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       454941                       # number of overall misses
-system.cpu1.icache.overall_misses::total       454941                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6716097000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6716097000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6716097000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6716097000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6716097000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6716097000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     32285282                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     32285282                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     32285282                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     32285282                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     32285282                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     32285282                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014091                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014091                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014091                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014091                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014091                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014091                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14762.567014                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14762.567014                       # average overall miss latency
+system.cpu1.kern.inst.quiesce                   43921                       # number of quiesce instructions executed
+system.cpu1.icache.replacements                454393                       # number of replacements
+system.cpu1.icache.tagsinuse               478.384673                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                32741717                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                454905                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 71.974845                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           92994898000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   478.384673                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.934345                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.934345                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     32741717                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       32741717                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     32741717                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        32741717                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     32741717                       # number of overall hits
+system.cpu1.icache.overall_hits::total       32741717                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       454905                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       454905                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       454905                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        454905                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       454905                       # number of overall misses
+system.cpu1.icache.overall_misses::total       454905                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6718353500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6718353500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6718353500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6718353500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6718353500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6718353500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     33196622                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     33196622                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     33196622                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     33196622                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     33196622                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     33196622                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013703                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.013703                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013703                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.013703                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013703                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.013703                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14768.695662                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14768.695662                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -921,122 +919,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks        23436                       # number of writebacks
-system.cpu1.icache.writebacks::total            23436                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       454941                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       454941                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       454941                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       454941                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       454941                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       454941                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5350372502                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5350372502                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5350372502                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5350372502                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5350372502                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5350372502                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       454905                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       454905                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       454905                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       454905                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       454905                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       454905                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5352734000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5352734000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5352734000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5352734000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5352734000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5352734000                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014091                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014091                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014091                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013703                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013703                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013703                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                292285                       # number of replacements
-system.cpu1.dcache.tagsinuse               472.233445                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                11962904                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                292625                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 40.881346                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           84136899000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   472.233445                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.922331                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.922331                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6947233                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6947233                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4827936                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4827936                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81814                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        81814                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82788                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        82788                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11775169                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11775169                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11775169                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11775169                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       170612                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       170612                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       150091                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       150091                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11098                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11098                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10047                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10047                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       320703                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        320703                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       320703                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       320703                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2368289000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2368289000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5141096000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   5141096000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106270500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    106270500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     87322000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     87322000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   7509385000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   7509385000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   7509385000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   7509385000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7117845                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7117845                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4978027                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4978027                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92912                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        92912                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92835                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92835                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     12095872                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12095872                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     12095872                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12095872                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023970                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023970                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030151                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030151                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119446                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119446                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108224                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108224                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026513                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026513                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026513                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026513                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9575.644260                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9575.644260                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8691.350652                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8691.350652                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446                       # average overall miss latency
+system.cpu1.dcache.replacements                292476                       # number of replacements
+system.cpu1.dcache.tagsinuse               472.237187                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                11966907                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                292816                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 40.868351                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           84138671000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   472.237187                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.922338                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.922338                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6949314                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6949314                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4829723                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4829723                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81817                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81817                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82772                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82772                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11779037                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11779037                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11779037                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11779037                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       170766                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       170766                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       150259                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       150259                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11112                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11112                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10077                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10077                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       321025                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        321025                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       321025                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       321025                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2375372000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2375372000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5143695000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   5143695000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106521500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    106521500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     88394000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     88394000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   7519067000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   7519067000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   7519067000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   7519067000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7120080                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7120080                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4979982                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4979982                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92929                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        92929                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92849                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92849                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     12100062                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12100062                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     12100062                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12100062                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023984                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.023984                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030173                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030173                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119575                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119575                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108531                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108531                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026531                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026531                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026531                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026531                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9586.168107                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9586.168107                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8771.856703                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8771.856703                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1045,62 +1041,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       266082                       # number of writebacks
-system.cpu1.dcache.writebacks::total           266082                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170612                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       170612                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150091                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       150091                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11098                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11098                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10038                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10038                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       320703                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       320703                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       320703                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       320703                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1855824122                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1855824122                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4690597670                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4690597670                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72957002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     72957002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57198010                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57198010                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6546421792                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   6546421792                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6546421792                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6546421792                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39677118500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39677118500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023970                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023970                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030151                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030151                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119446                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119446                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108127                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108127                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026513                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026513                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026513                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026513                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6573.887367                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6573.887367                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5698.148037                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5698.148037                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       266164                       # number of writebacks
+system.cpu1.dcache.writebacks::total           266164                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170766                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       170766                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150259                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       150259                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11112                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11112                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10067                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10067                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       321025                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       321025                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       321025                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       321025                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1862452631                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1862452631                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4692688176                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4692688176                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73165002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     73165002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     58182011                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     58182011                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6555140807                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   6555140807                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6555140807                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   6555140807                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39709759000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39709759000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023984                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023984                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030173                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030173                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119575                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119575                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108423                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108423                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026531                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026531                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026531                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026531                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6584.323434                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6584.323434                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5779.478593                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5779.478593                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1122,10 +1118,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 550047772786                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 550791407487                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index b0e885f8a..adf32d590 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -250,7 +250,7 @@ header_cycles=1
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index a0fa03c1d..a561bb329 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 09:08:16
-gem5 started Jul  2 2012 15:20:44
+gem5 compiled Jul 26 2012 21:40:00
+gem5 started Jul 27 2012 00:56:10
 gem5 executing on zizzer
-command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2593402521000 because m5_exit instruction encountered
+Exiting @ tick 2594327510000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 5473fafb1..724af2042 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,16 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.593403                       # Number of seconds simulated
-sim_ticks                                2593402521000                       # Number of ticks simulated
-final_tick                               2593402521000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.594328                       # Number of seconds simulated
+sim_ticks                                2594327510000                       # Number of ticks simulated
+final_tick                               2594327510000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 766927                       # Simulator instruction rate (inst/s)
-host_op_rate                                   979485                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            33608362861                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384708                       # Number of bytes of host memory used
-host_seconds                                    77.17                       # Real time elapsed on the host
-sim_insts                                    59180230                       # Number of instructions simulated
-sim_ops                                      75582343                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 600896                       # Simulator instruction rate (inst/s)
+host_op_rate                                   764626                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25897323777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390576                       # Number of bytes of host memory used
+host_seconds                                   100.18                       # Real time elapsed on the host
+sim_insts                                    60196191                       # Number of instructions simulated
+sim_ops                                      76598245                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            704288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9067216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132455344                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       704288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          704288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3695616                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6711688                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17207                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15494347                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57744                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811762                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47289092                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               271472                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3495016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51055753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          271472                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             271472                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1424499                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1162564                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2587063                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1424499                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47289092                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              271472                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4657580                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53642816                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -23,179 +61,141 @@ system.realview.nvmem.bw_inst_read::cpu.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            704224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9067536                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132455600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       704224                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704224                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3695808                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6711880                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17206                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141714                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494351                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57747                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811765                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47305958                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               271544                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3496386                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51074062                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          271544                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             271544                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1425081                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1162979                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2588059                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1425081                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47305958                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              271544                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4659365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53662121                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         62163                       # number of replacements
-system.l2c.tagsinuse                     51413.022429                       # Cycle average of tags in use
-system.l2c.total_refs                         1730961                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        127547                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         13.571162                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2544159444000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        38018.047073                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker        3.884744                       # Average occupied blocks per requestor
+system.l2c.replacements                         62159                       # number of replacements
+system.l2c.tagsinuse                     51417.185894                       # Cycle average of tags in use
+system.l2c.total_refs                         1682923                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127542                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.195049                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2544924960000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        38023.288706                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        3.884784                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.itb.walker        0.000558                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           7004.232123                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6386.857931                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.580109                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu.inst           7004.395748                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6385.616098                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.580189                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.dtb.walker       0.000059                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.106876                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.097456                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.784500                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          8759                       # number of ReadReq hits
+system.l2c.occ_percent::cpu.inst             0.106879                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.097437                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.784564                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          8754                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.itb.walker          3544                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              843511                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              367799                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1223613                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          646378                       # number of Writeback hits
-system.l2c.Writeback_hits::total               646378                       # number of Writeback hits
+system.l2c.ReadReq_hits::cpu.inst              843519                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              370124                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1225941                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          596001                       # number of Writeback hits
+system.l2c.Writeback_hits::total               596001                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            114402                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               114402                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           8759                       # number of demand (read+write) hits
+system.l2c.ReadExReq_hits::cpu.data            114391                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               114391                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           8754                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu.itb.walker           3544                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               843511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               482201                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1338015                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          8759                       # number of overall hits
+system.l2c.demand_hits::cpu.inst               843519                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               484515                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1340332                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          8754                       # number of overall hits
 system.l2c.overall_hits::cpu.itb.walker          3544                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              843511                       # number of overall hits
-system.l2c.overall_hits::cpu.data              482201                       # number of overall hits
-system.l2c.overall_hits::total                1338015                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              843519                       # number of overall hits
+system.l2c.overall_hits::cpu.data              484515                       # number of overall hits
+system.l2c.overall_hits::total                1340332                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             10590                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             10591                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data             10247                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20844                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2881                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2881                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133061                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133061                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::total                20845                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2879                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2879                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133059                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133059                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              10590                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143308                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153905                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              10591                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143306                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153904                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             10590                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143308                       # number of overall misses
-system.l2c.overall_misses::total               153905                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             10591                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143306                       # number of overall misses
+system.l2c.overall_misses::total               153904                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu.dtb.walker       260500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    552215500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    533568500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1086148500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    552260500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    533540500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1086165500                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu.data      1040000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total      1040000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6924755000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6924755000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6923957000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6923957000                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu.dtb.walker       260500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    552215500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7458323500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8010903500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    552260500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7457497500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8010122500                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu.dtb.walker       260500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    552215500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7458323500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8010903500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker         8764                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu.inst    552260500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7457497500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8010122500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         8759                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu.itb.walker         3546                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          854101                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          378046                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1244457                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       646378                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           646378                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2907                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2907                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        247463                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247463                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         8764                       # number of demand (read+write) accesses
+system.l2c.ReadReq_accesses::cpu.inst          854110                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          380371                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1246786                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       596001                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           596001                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2905                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2905                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        247450                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247450                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         8759                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu.itb.walker         3546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           854101                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           625509                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1491920                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         8764                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           854110                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           627821                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1494236                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         8759                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu.itb.walker         3546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          854101                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          625509                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1491920                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          854110                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          627821                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1494236                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000564                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012399                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.027105                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016749                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.991056                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991056                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.537701                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.537701                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012400                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026939                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016719                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.991050                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991050                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.537721                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.537721                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.000564                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012399                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.229106                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103159                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012400                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.228259                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.102998                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.000564                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012399                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.229106                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103159                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012400                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.228259                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.102998                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52100                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.995279                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52070.703621                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52108.448474                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   360.985769                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   360.985769                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52041.958200                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52041.958200                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.320650                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52067.971113                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52106.764212                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   361.236540                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   361.236540                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52036.743099                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52036.743099                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52144.995279                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52044.013593                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52050.963257                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52046.226869                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52144.995279                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52044.013593                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52050.963257                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52046.226869                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -204,92 +204,92 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57747                       # number of writebacks
-system.l2c.writebacks::total                    57747                       # number of writebacks
+system.l2c.writebacks::writebacks               57744                       # number of writebacks
+system.l2c.writebacks::total                    57744                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        10590                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        10591                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.data        10247                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           20844                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2881                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2881                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133061                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133061                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20845                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2879                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2879                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133059                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133059                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         10590                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143308                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153905                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         10591                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143306                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153904                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        10590                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143308                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153905                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        10591                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143306                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153904                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       200000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425129000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    410601000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    836010000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115527000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    115527000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5328003000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5328003000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425162000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    410573000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    836015000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115365000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    115365000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5327229000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5327229000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       200000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    425129000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5738604000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6164013000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    425162000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5737802000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6163244000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       200000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    425129000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5738604000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6164013000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    425162000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5737802000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6163244000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst    264840000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131438638000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131703478000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31164555000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31164555000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131435179000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131700019000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31197392500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31197392500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst    264840000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162603193000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162868033000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 162897411500                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.027105                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016749                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991056                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991056                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537701                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537701                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026939                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016719                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991050                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991050                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537721                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537721                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.229106                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.103159                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.102998                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.229106                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.103159                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.102998                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40070.362057                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40107.944732                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.618188                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.618188                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.807893                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40041.807893                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40043.849611                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40050.765082                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40050.765082                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -307,26 +307,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14995175                       # DTB read hits
-system.cpu.dtb.read_misses                       7360                       # DTB read misses
-system.cpu.dtb.write_hits                    11229808                       # DTB write hits
+system.cpu.dtb.read_hits                     14995137                       # DTB read hits
+system.cpu.dtb.read_misses                       7357                       # DTB read misses
+system.cpu.dtb.write_hits                    11229787                       # DTB write hits
 system.cpu.dtb.write_misses                      2205                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3488                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3485                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    182                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15002535                       # DTB read accesses
-system.cpu.dtb.write_accesses                11232013                       # DTB write accesses
+system.cpu.dtb.read_accesses                 15002494                       # DTB read accesses
+system.cpu.dtb.write_accesses                11231992                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26224983                       # DTB hits
-system.cpu.dtb.misses                            9565                       # DTB misses
-system.cpu.dtb.accesses                      26234548                       # DTB accesses
-system.cpu.itb.inst_hits                     60461981                       # ITB inst hits
+system.cpu.dtb.hits                          26224924                       # DTB hits
+system.cpu.dtb.misses                            9562                       # DTB misses
+system.cpu.dtb.accesses                      26234486                       # DTB accesses
+system.cpu.itb.inst_hits                     61490084                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -343,79 +343,79 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 60466452                       # ITB inst accesses
-system.cpu.itb.hits                          60461981                       # DTB hits
+system.cpu.itb.inst_accesses                 61494555                       # ITB inst accesses
+system.cpu.itb.hits                          61490084                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      60466452                       # DTB accesses
-system.cpu.numCycles                       5186805042                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61494555                       # DTB accesses
+system.cpu.numCycles                       5188655020                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    59180230                       # Number of instructions committed
-system.cpu.committedOps                      75582343                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68351784                       # Number of integer alu accesses
+system.cpu.committedInsts                    60196191                       # Number of instructions committed
+system.cpu.committedOps                      76598245                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              68865648                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2139562                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7653493                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68351784                       # number of integer instructions
+system.cpu.num_func_calls                     2139540                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7910583                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     68865648                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           391402858                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           73137157                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           394743471                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           74177139                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27392171                       # number of memory refs
-system.cpu.num_load_insts                    15659029                       # Number of load instructions
-system.cpu.num_store_insts                   11733142                       # Number of store instructions
-system.cpu.num_idle_cycles               4570470450.554237                       # Number of idle cycles
-system.cpu.num_busy_cycles               616334591.445762                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.118827                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.881173                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      27392126                       # number of memory refs
+system.cpu.num_load_insts                    15659006                       # Number of load instructions
+system.cpu.num_store_insts                   11733120                       # Number of store instructions
+system.cpu.num_idle_cycles               4570211154.554238                       # Number of idle cycles
+system.cpu.num_busy_cycles               618443865.445762                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.119192                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.880808                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    82989                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 855209                       # number of replacements
-system.cpu.icache.tagsinuse                510.928777                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59606260                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 855721                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  69.656185                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            18855254000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.928777                       # Average occupied blocks per requestor
+system.cpu.icache.replacements                 855220                       # number of replacements
+system.cpu.icache.tagsinuse                510.929118                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 60634352                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 855732                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  70.856707                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            18856022000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.929118                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.997908                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.997908                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59606260                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59606260                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59606260                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59606260                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59606260                       # number of overall hits
-system.cpu.icache.overall_hits::total        59606260                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       855721                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        855721                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       855721                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         855721                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       855721                       # number of overall misses
-system.cpu.icache.overall_misses::total        855721                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12570164500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12570164500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12570164500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12570164500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12570164500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12570164500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     60461981                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60461981                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60461981                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60461981                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60461981                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60461981                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014153                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014153                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014153                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014153                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014153                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014153                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14689.559448                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14689.559448                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14689.559448                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14689.559448                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14689.559448                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14689.559448                       # average overall miss latency
+system.cpu.icache.ReadReq_hits::cpu.inst     60634352                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60634352                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60634352                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60634352                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60634352                       # number of overall hits
+system.cpu.icache.overall_hits::total        60634352                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       855732                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        855732                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       855732                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         855732                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       855732                       # number of overall misses
+system.cpu.icache.overall_misses::total        855732                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12556184500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12556184500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12556184500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12556184500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12556184500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12556184500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     61490084                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61490084                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61490084                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61490084                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61490084                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61490084                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013917                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013917                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013917                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013917                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14673.033730                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14673.033730                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -424,114 +424,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        50294                       # number of writebacks
-system.cpu.icache.writebacks::total             50294                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       855721                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       855721                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       855721                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       855721                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       855721                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       855721                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10001095500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10001095500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10001095500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10001095500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10001095500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10001095500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       855732                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       855732                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       855732                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       855732                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       855732                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       855732                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9987081500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9987081500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9987081500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9987081500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9987081500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9987081500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014153                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014153                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014153                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11687.332086                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11687.332086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11687.332086                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013917                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 627384                       # number of replacements
-system.cpu.dcache.tagsinuse                511.875582                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 23653412                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 627896                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  37.670907                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 627309                       # number of replacements
+system.cpu.dcache.tagsinuse                511.875626                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 23653426                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 627821                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.675430                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              661351000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.875582                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.875626                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13194595                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13194595                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972161                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972161                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236089                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236089                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247660                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247660                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23166756                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23166756                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23166756                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23166756                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368861                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368861                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250370                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250370                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11572                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11572                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       619231                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         619231                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       619231                       # number of overall misses
-system.cpu.dcache.overall_misses::total        619231                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5722405000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5722405000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9232056000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9232056000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    172133500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    172133500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14954461000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14954461000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14954461000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14954461000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13563456                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13563456                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247661                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247661                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247660                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247660                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23785987                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23785987                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23785987                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23785987                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027195                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027195                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024492                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024492                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046725                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046725                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.026033                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026033                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.026033                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026033                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15513.716549                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15513.716549                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36873.650997                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36873.650997                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        14875                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        14875                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24150.052242                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24150.052242                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24150.052242                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24150.052242                       # average overall miss latency
+system.cpu.dcache.ReadReq_hits::cpu.data     13194612                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13194612                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9972158                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9972158                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236094                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236094                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247657                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247657                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      23166770                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23166770                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23166770                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23166770                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       368807                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        368807                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250355                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250355                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11564                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11564                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       619162                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         619162                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       619162                       # number of overall misses
+system.cpu.dcache.overall_misses::total        619162                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5738700500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5738700500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9229453000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9229453000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    171857500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    171857500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14968153500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14968153500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14968153500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14968153500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13563419                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13563419                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222513                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222513                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247658                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247658                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247657                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247657                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23785932                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23785932                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23785932                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23785932                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027191                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027191                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024491                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024491                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046693                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046693                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026031                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026031                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026031                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026031                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24174.858115                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24174.858115                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -540,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       596084                       # number of writebacks
-system.cpu.dcache.writebacks::total            596084                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368861                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368861                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250370                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250370                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11572                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11572                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       619231                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       619231                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       619231                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       619231                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4614667500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4614667500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8480868000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8480868000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    137416000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    137416000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13095535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13095535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13095535500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13095535500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146835601000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146835601000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40324843500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40324843500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027195                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027195                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024492                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024492                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046725                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046725                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026033                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026033                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026033                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026033                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       596001                       # number of writebacks
+system.cpu.dcache.writebacks::total            596001                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368807                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       368807                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250355                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250355                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11564                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11564                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       619162                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       619162                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       619162                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       619162                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4631124500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4631124500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8478310000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8478310000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    137164000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    137164000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13109434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13109434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13109434500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13109434500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40357680500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40357680500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027191                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027191                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024491                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024491                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046693                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046693                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026031                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026031                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -609,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1341484384445                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1342178832750                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index a4365933a..725aa519b 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 memories=system.physmem
@@ -934,7 +934,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -954,7 +954,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index d8387d75d..7a86428b1 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 22 2012 08:05:39
-gem5 started Jul 22 2012 08:43:43
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jul 26 2012 21:30:36
+gem5 started Jul 26 2012 22:49:04
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112043255000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 96f4e7d80..4f10e01e9 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1067695                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2186181                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27315912254                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 409548                       # Number of bytes of host memory used
-host_seconds                                   187.15                       # Real time elapsed on the host
+host_inst_rate                                1419112                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2905734                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36306590178                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 362152                       # Number of bytes of host memory used
+host_seconds                                   140.80                       # Real time elapsed on the host
 sim_insts                                   199813914                       # Number of instructions simulated
 sim_ops                                     409133298                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2464768                       # Number of bytes read from this memory
@@ -48,9 +48,9 @@ system.physmem.bw_total::cpu.data             2073572                       # To
 system.physmem.bw_total::total                4540656                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        106561                       # number of replacements
 system.l2c.tagsinuse                     64822.143261                       # Cycle average of tags in use
-system.l2c.total_refs                         3457342                       # Total number of references to valid blocks.
+system.l2c.total_refs                         3456533                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                        170680                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         20.256281                       # Average number of references to valid blocks.
+system.l2c.avg_refs                         20.251541                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
 system.l2c.occ_blocks::writebacks        51981.461987                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.dtb.walker        0.004954                       # Average occupied blocks per requestor
@@ -68,8 +68,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker          2700                       # nu
 system.l2c.ReadReq_hits::cpu.inst              777957                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.data             1275395                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2062630                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1538939                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1538939                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1538130                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1538130                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               28                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::cpu.data            179208                       # number of ReadExReq hits
@@ -108,8 +108,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker         2705                       #
 system.l2c.ReadReq_accesses::cpu.inst          791299                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu.data         1307579                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2108163                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1538939                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1538939                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1538130                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1538130                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu.data         1824                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            1824                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu.data        313585                       # number of ReadExReq accesses(hits+misses)
@@ -275,8 +275,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          809                       # number of writebacks
-system.cpu.icache.writebacks::total               809                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3335                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.026444                       # Cycle average of tags in use
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 8535283af..ae091f3af 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -930,7 +930,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -950,7 +950,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 64807f302..4564af214 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 22 2012 08:05:39
-gem5 started Jul 22 2012 08:43:19
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jul 26 2012 21:30:36
+gem5 started Jul 26 2012 22:51:36
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5191766314000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 49cb796d4..a4ae62a22 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.191766                       # Nu
 sim_ticks                                5191766314000                       # Number of ticks simulated
 final_tick                               5191766314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 672863                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1291533                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25283717995                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 405876                       # Number of bytes of host memory used
-host_seconds                                   205.34                       # Real time elapsed on the host
+host_inst_rate                                 787684                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1511929                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            29598304712                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 358992                       # Number of bytes of host memory used
+host_seconds                                   175.41                       # Real time elapsed on the host
 sim_insts                                   138165780                       # Number of instructions simulated
 sim_ops                                     265203824                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2891072                       # Number of bytes read from this memory
@@ -44,9 +44,9 @@ system.physmem.bw_total::cpu.data             1721828                       # To
 system.physmem.bw_total::total                3993388                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                         86221                       # number of replacements
 system.l2c.tagsinuse                     64766.656127                       # Cycle average of tags in use
-system.l2c.total_refs                         3491043                       # Total number of references to valid blocks.
+system.l2c.total_refs                         3490237                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                        150947                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         23.127608                       # Average number of references to valid blocks.
+system.l2c.avg_refs                         23.122268                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
 system.l2c.occ_blocks::writebacks        50170.355166                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.itb.walker        0.141198                       # Average occupied blocks per requestor
@@ -62,8 +62,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker          2757                       # nu
 system.l2c.ReadReq_hits::cpu.inst              777565                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.data             1279351                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2065979                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1542135                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1542135                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1541329                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1541329                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data              319                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 319                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::cpu.data            200451                       # number of ReadExReq hits
@@ -115,8 +115,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker         2762                       #
 system.l2c.ReadReq_accesses::cpu.inst          790398                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu.data         1307724                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2107190                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1542135                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1542135                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1541329                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1541329                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu.data         1665                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            1665                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu.data        312686                       # number of ReadExReq accesses(hits+misses)
@@ -431,8 +431,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          806                       # number of writebacks
-system.cpu.icache.writebacks::total               806                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       790411                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total       790411                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst       790411                       # number of demand (read+write) MSHR misses
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index 47099262f..3be58b836 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -155,30 +155,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -214,16 +204,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -260,76 +245,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -337,10 +302,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 1832a62b7..0c7f2991f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:30:17
-gem5 started Jul 10 2012 17:30:49
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 13:42:35
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index dc174d88f..bae589857 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000279                       # Nu
 sim_ticks                                      279353                       # Number of ticks simulated
 final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24575                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24573                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1071866                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236072                       # Number of bytes of host memory used
-host_seconds                                     0.26                       # Real time elapsed on the host
+host_inst_rate                                  12119                       # Simulator instruction rate (inst/s)
+host_op_rate                                    12118                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 528605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226340                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               23969673                       # Wr
 system.physmem.bw_total::cpu.inst            91840789                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            55485354                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              147326143                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 81f78cde4..f0fb5fcd1 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -152,30 +152,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -210,16 +200,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -256,76 +241,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -333,10 +298,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index aac08e2fa..691f6347c 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:36:02
-gem5 started Jul 10 2012 17:36:36
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:41:04
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 91d67e04f..ddb3e7d12 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000224                       # Nu
 sim_ticks                                      223694                       # Number of ticks simulated
 final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21381                       # Simulator instruction rate (inst/s)
-host_op_rate                                    21380                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 746759                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236312                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
+host_inst_rate                                  30014                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30012                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1048235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226460                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               29933749                       # Wr
 system.physmem.bw_total::cpu.inst           114692392                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            69291085                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              183983477                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 4e5ea8bc4..260fc7a89 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -161,30 +161,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -221,16 +211,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -267,76 +252,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -344,10 +309,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index e3a769a26..63d892f7f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:34:13
-gem5 started Jul 10 2012 17:45:14
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:42:12
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 7722b3fbe..9ad88fcd3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000232                       # Nu
 sim_ticks                                      231701                       # Number of ticks simulated
 final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36777                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36773                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1330353                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234436                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  50012                       # Simulator instruction rate (inst/s)
+host_op_rate                                    50005                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1808952                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224692                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               28899314                       # Wr
 system.physmem.bw_total::cpu.inst           110728914                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            66896561                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              177625474                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 9fd0a4ee1..c7cccc96e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -138,16 +138,11 @@ version=0
 [system.dir_cntrl0.probeFilter]
 type=RubyCache
 assoc=4
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=1024
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
@@ -172,44 +167,29 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -262,64 +242,61 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=2
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 8fc46fbe9..f1ba4ed84 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:16:15
-gem5 started Jul 10 2012 17:50:25
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:41:27
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index a0796133c..842792d27 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000208                       # Nu
 sim_ticks                                      208400                       # Number of ticks simulated
 final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40149                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40144                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1306231                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233684                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  52133                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1696034                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224184                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
@@ -33,30 +33,6 @@ system.physmem.bw_write::total               32130518                       # Wr
 system.physmem.bw_total::cpu.inst           123109405                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            74376200                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              197485605                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.dir_cntrl0.probeFilter.num_data_array_reads            0                       # number of data array reads
-system.dir_cntrl0.probeFilter.num_data_array_writes            0                       # number of data array writes
-system.dir_cntrl0.probeFilter.num_tag_array_reads            0                       # number of tag array reads
-system.dir_cntrl0.probeFilter.num_tag_array_writes            0                       # number of tag array writes
-system.dir_cntrl0.probeFilter.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.dir_cntrl0.probeFilter.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index bc15d1f8b..317cc6a7e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -155,30 +155,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -214,16 +204,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -260,76 +245,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -337,10 +302,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index d29f3759f..d8d70a93e 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:30:17
-gem5 started Jul 10 2012 17:31:25
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 13:42:35
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 20b3bd153..748d8a973 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000105                       # Nu
 sim_ticks                                      104867                       # Number of ticks simulated
 final_tick                                     104867                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25231                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25226                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1026377                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233832                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                   4864                       # Simulator instruction rate (inst/s)
+host_op_rate                                     4864                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 197908                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224040                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               19624858                       # Wr
 system.physmem.bw_total::cpu.inst            98601085                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            48385097                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              146986182                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 5b6cac45b..34c479e22 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -152,30 +152,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -210,16 +200,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -256,76 +241,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -333,10 +298,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 4b0921627..dc8b54148 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:36:02
-gem5 started Jul 10 2012 17:37:10
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:41:15
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 6d74d1d8c..07e9173f4 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000085                       # Nu
 sim_ticks                                       85418                       # Number of ticks simulated
 final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21617                       # Simulator instruction rate (inst/s)
-host_op_rate                                    21614                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 716318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234076                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  30509                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30502                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1010829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224228                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               24093282                       # Wr
 system.physmem.bw_total::cpu.inst           121051769                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            59402000                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              180453769                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 2b2f5fcb6..ea15696c3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -161,30 +161,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -221,16 +211,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -267,76 +252,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -344,10 +309,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 851a68508..3e1c7a0df 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:34:13
-gem5 started Jul 10 2012 17:45:47
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:42:22
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 0bb4f7ab2..0b4d202c9 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                       87899                       # Number of ticks simulated
 final_tick                                      87899                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36684                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36675                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1250644                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233044                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  49141                       # Simulator instruction rate (inst/s)
+host_op_rate                                    49125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1675041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223232                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -33,24 +33,6 @@ system.physmem.bw_write::total               23413236                       # Wr
 system.physmem.bw_total::cpu.inst           117635013                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            57725344                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              175360357                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index d24ccea68..5531e80ff 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -138,16 +138,11 @@ version=0
 [system.dir_cntrl0.probeFilter]
 type=RubyCache
 assoc=4
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=1024
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
@@ -172,44 +167,29 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -262,64 +242,61 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=2
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 2612c0b40..423daf7c7 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:16:15
-gem5 started Jul 10 2012 17:50:59
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:42:34
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 17ceaae11..002b923d5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000078                       # Nu
 sim_ticks                                       78448                       # Number of ticks simulated
 final_tick                                      78448                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40059                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40048                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1218818                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232472                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                   9618                       # Simulator instruction rate (inst/s)
+host_op_rate                                     9618                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 292754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222892                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
@@ -33,30 +33,6 @@ system.physmem.bw_write::total               26233938                       # Wr
 system.physmem.bw_total::cpu.inst           131807057                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            64679788                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              196486845                       # Total bandwidth to/from this memory (bytes/s)
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.dir_cntrl0.probeFilter.num_data_array_reads            0                       # number of data array reads
-system.dir_cntrl0.probeFilter.num_data_array_writes            0                       # number of data array writes
-system.dir_cntrl0.probeFilter.num_tag_array_reads            0                       # number of tag array reads
-system.dir_cntrl0.probeFilter.num_tag_array_writes            0                       # number of tag array writes
-system.dir_cntrl0.probeFilter.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.dir_cntrl0.probeFilter.num_data_array_stalls            0                       # number of stalls caused by data array
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index 5b264ec2e..35cfc3441 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -14,7 +14,7 @@ init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -249,30 +249,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -312,30 +302,20 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.sequencer]
 type=RubySequencer
@@ -375,30 +355,20 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.sequencer]
 type=RubySequencer
@@ -438,30 +408,20 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.sequencer]
 type=RubySequencer
@@ -501,30 +461,20 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.sequencer]
 type=RubySequencer
@@ -564,30 +514,20 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.sequencer]
 type=RubySequencer
@@ -627,30 +567,20 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.sequencer]
 type=RubySequencer
@@ -690,30 +620,20 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.sequencer]
 type=RubySequencer
@@ -749,16 +669,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -795,174 +710,119 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers00
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl1
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers01
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl2
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers02
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.ext_links3]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl3
-int_node=system.ruby.network.topology.ext_links3.int_node
+int_node=system.ruby.network.topology.routers03
 latency=1
 link_id=3
 weight=1
 
-[system.ruby.network.topology.ext_links3.int_node]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.ext_links4]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl4
-int_node=system.ruby.network.topology.ext_links4.int_node
+int_node=system.ruby.network.topology.routers04
 latency=1
 link_id=4
 weight=1
 
-[system.ruby.network.topology.ext_links4.int_node]
-type=BasicRouter
-router_id=4
-
 [system.ruby.network.topology.ext_links5]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl5
-int_node=system.ruby.network.topology.ext_links5.int_node
+int_node=system.ruby.network.topology.routers05
 latency=1
 link_id=5
 weight=1
 
-[system.ruby.network.topology.ext_links5.int_node]
-type=BasicRouter
-router_id=5
-
 [system.ruby.network.topology.ext_links6]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl6
-int_node=system.ruby.network.topology.ext_links6.int_node
+int_node=system.ruby.network.topology.routers06
 latency=1
 link_id=6
 weight=1
 
-[system.ruby.network.topology.ext_links6.int_node]
-type=BasicRouter
-router_id=6
-
 [system.ruby.network.topology.ext_links7]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl7
-int_node=system.ruby.network.topology.ext_links7.int_node
+int_node=system.ruby.network.topology.routers07
 latency=1
 link_id=7
 weight=1
 
-[system.ruby.network.topology.ext_links7.int_node]
-type=BasicRouter
-router_id=7
-
 [system.ruby.network.topology.ext_links8]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links8.int_node
+int_node=system.ruby.network.topology.routers08
 latency=1
 link_id=8
 weight=1
 
-[system.ruby.network.topology.ext_links8.int_node]
-type=BasicRouter
-router_id=8
-
 [system.ruby.network.topology.ext_links9]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links9.int_node
+int_node=system.ruby.network.topology.routers09
 latency=1
 link_id=9
 weight=1
 
-[system.ruby.network.topology.ext_links9.int_node]
-type=BasicRouter
-router_id=9
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=10
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=10
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=11
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -970,8 +830,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=12
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links3]
@@ -979,8 +839,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=13
-node_a=system.ruby.network.topology.ext_links3.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links4]
@@ -988,8 +848,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=14
-node_a=system.ruby.network.topology.ext_links4.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links5]
@@ -997,8 +857,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=15
-node_a=system.ruby.network.topology.ext_links5.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links6]
@@ -1006,8 +866,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=16
-node_a=system.ruby.network.topology.ext_links6.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links7]
@@ -1015,8 +875,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=17
-node_a=system.ruby.network.topology.ext_links7.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links8]
@@ -1024,8 +884,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=18
-node_a=system.ruby.network.topology.ext_links8.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links9]
@@ -1033,10 +893,54 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=19
-node_a=system.ruby.network.topology.ext_links9.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
 weight=1
 
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index bc0d86d72..4c179bc95 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:30:17
-gem5 started Jul 10 2012 17:31:57
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 14:40:22
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index 3b11b4fe0..c7afc7b3a 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -4,111 +4,9 @@ sim_seconds                                  0.022495                       # Nu
 sim_ticks                                    22495354                       # Number of ticks simulated
 final_tick                                   22495354                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 170886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380372                       # Number of bytes of host memory used
-host_seconds                                   131.64                       # Real time elapsed on the host
-system.l1_cntrl4.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                 256726                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370452                       # Number of bytes of host memory used
+host_seconds                                    87.62                       # Real time elapsed on the host
 system.cpu0.num_reads                           99326                       # number of read accesses completed
 system.cpu0.num_writes                          53132                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index ff00bba8d..e3b9d4def 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -246,30 +246,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -307,30 +297,20 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.sequencer]
 type=RubySequencer
@@ -368,30 +348,20 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.sequencer]
 type=RubySequencer
@@ -429,30 +399,20 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.sequencer]
 type=RubySequencer
@@ -490,30 +450,20 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.sequencer]
 type=RubySequencer
@@ -551,30 +501,20 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.sequencer]
 type=RubySequencer
@@ -612,30 +552,20 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.sequencer]
 type=RubySequencer
@@ -673,30 +603,20 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.sequencer]
 type=RubySequencer
@@ -731,16 +651,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -777,174 +692,119 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers00
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl1
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers01
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl2
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers02
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.ext_links3]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl3
-int_node=system.ruby.network.topology.ext_links3.int_node
+int_node=system.ruby.network.topology.routers03
 latency=1
 link_id=3
 weight=1
 
-[system.ruby.network.topology.ext_links3.int_node]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.ext_links4]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl4
-int_node=system.ruby.network.topology.ext_links4.int_node
+int_node=system.ruby.network.topology.routers04
 latency=1
 link_id=4
 weight=1
 
-[system.ruby.network.topology.ext_links4.int_node]
-type=BasicRouter
-router_id=4
-
 [system.ruby.network.topology.ext_links5]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl5
-int_node=system.ruby.network.topology.ext_links5.int_node
+int_node=system.ruby.network.topology.routers05
 latency=1
 link_id=5
 weight=1
 
-[system.ruby.network.topology.ext_links5.int_node]
-type=BasicRouter
-router_id=5
-
 [system.ruby.network.topology.ext_links6]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl6
-int_node=system.ruby.network.topology.ext_links6.int_node
+int_node=system.ruby.network.topology.routers06
 latency=1
 link_id=6
 weight=1
 
-[system.ruby.network.topology.ext_links6.int_node]
-type=BasicRouter
-router_id=6
-
 [system.ruby.network.topology.ext_links7]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl7
-int_node=system.ruby.network.topology.ext_links7.int_node
+int_node=system.ruby.network.topology.routers07
 latency=1
 link_id=7
 weight=1
 
-[system.ruby.network.topology.ext_links7.int_node]
-type=BasicRouter
-router_id=7
-
 [system.ruby.network.topology.ext_links8]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links8.int_node
+int_node=system.ruby.network.topology.routers08
 latency=1
 link_id=8
 weight=1
 
-[system.ruby.network.topology.ext_links8.int_node]
-type=BasicRouter
-router_id=8
-
 [system.ruby.network.topology.ext_links9]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links9.int_node
+int_node=system.ruby.network.topology.routers09
 latency=1
 link_id=9
 weight=1
 
-[system.ruby.network.topology.ext_links9.int_node]
-type=BasicRouter
-router_id=9
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=10
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=10
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=11
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -952,8 +812,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=12
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links3]
@@ -961,8 +821,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=13
-node_a=system.ruby.network.topology.ext_links3.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links4]
@@ -970,8 +830,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=14
-node_a=system.ruby.network.topology.ext_links4.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links5]
@@ -979,8 +839,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=15
-node_a=system.ruby.network.topology.ext_links5.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links6]
@@ -988,8 +848,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=16
-node_a=system.ruby.network.topology.ext_links6.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links7]
@@ -997,8 +857,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=17
-node_a=system.ruby.network.topology.ext_links7.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links8]
@@ -1006,8 +866,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=18
-node_a=system.ruby.network.topology.ext_links8.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links9]
@@ -1015,10 +875,54 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=19
-node_a=system.ruby.network.topology.ext_links9.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
 weight=1
 
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 3dcad7574..ca77e3fc7 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:36:02
-gem5 started Jul 10 2012 17:37:43
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:41:26
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index c85767a76..fcc191198 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,111 +4,9 @@ sim_seconds                                  0.019401                       # Nu
 sim_ticks                                    19400856                       # Number of ticks simulated
 final_tick                                   19400856                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  50488                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380584                       # Number of bytes of host memory used
-host_seconds                                   384.27                       # Real time elapsed on the host
-system.l1_cntrl4.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                  79524                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370632                       # Number of bytes of host memory used
+host_seconds                                   243.96                       # Real time elapsed on the host
 system.cpu0.num_reads                           98844                       # number of read accesses completed
 system.cpu0.num_writes                          53478                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index 93f57099a..4af9d9478 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -255,30 +255,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -322,30 +312,20 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.sequencer]
 type=RubySequencer
@@ -389,30 +369,20 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.sequencer]
 type=RubySequencer
@@ -456,30 +426,20 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.sequencer]
 type=RubySequencer
@@ -523,30 +483,20 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.sequencer]
 type=RubySequencer
@@ -590,30 +540,20 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.sequencer]
 type=RubySequencer
@@ -657,30 +597,20 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.sequencer]
 type=RubySequencer
@@ -724,30 +654,20 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.sequencer]
 type=RubySequencer
@@ -784,16 +704,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -830,174 +745,119 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers00
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl1
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers01
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl2
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers02
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.ext_links3]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl3
-int_node=system.ruby.network.topology.ext_links3.int_node
+int_node=system.ruby.network.topology.routers03
 latency=1
 link_id=3
 weight=1
 
-[system.ruby.network.topology.ext_links3.int_node]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.ext_links4]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl4
-int_node=system.ruby.network.topology.ext_links4.int_node
+int_node=system.ruby.network.topology.routers04
 latency=1
 link_id=4
 weight=1
 
-[system.ruby.network.topology.ext_links4.int_node]
-type=BasicRouter
-router_id=4
-
 [system.ruby.network.topology.ext_links5]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl5
-int_node=system.ruby.network.topology.ext_links5.int_node
+int_node=system.ruby.network.topology.routers05
 latency=1
 link_id=5
 weight=1
 
-[system.ruby.network.topology.ext_links5.int_node]
-type=BasicRouter
-router_id=5
-
 [system.ruby.network.topology.ext_links6]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl6
-int_node=system.ruby.network.topology.ext_links6.int_node
+int_node=system.ruby.network.topology.routers06
 latency=1
 link_id=6
 weight=1
 
-[system.ruby.network.topology.ext_links6.int_node]
-type=BasicRouter
-router_id=6
-
 [system.ruby.network.topology.ext_links7]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl7
-int_node=system.ruby.network.topology.ext_links7.int_node
+int_node=system.ruby.network.topology.routers07
 latency=1
 link_id=7
 weight=1
 
-[system.ruby.network.topology.ext_links7.int_node]
-type=BasicRouter
-router_id=7
-
 [system.ruby.network.topology.ext_links8]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links8.int_node
+int_node=system.ruby.network.topology.routers08
 latency=1
 link_id=8
 weight=1
 
-[system.ruby.network.topology.ext_links8.int_node]
-type=BasicRouter
-router_id=8
-
 [system.ruby.network.topology.ext_links9]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links9.int_node
+int_node=system.ruby.network.topology.routers09
 latency=1
 link_id=9
 weight=1
 
-[system.ruby.network.topology.ext_links9.int_node]
-type=BasicRouter
-router_id=9
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=10
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=10
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=11
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -1005,8 +865,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=12
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links3]
@@ -1014,8 +874,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=13
-node_a=system.ruby.network.topology.ext_links3.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links4]
@@ -1023,8 +883,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=14
-node_a=system.ruby.network.topology.ext_links4.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links5]
@@ -1032,8 +892,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=15
-node_a=system.ruby.network.topology.ext_links5.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links6]
@@ -1041,8 +901,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=16
-node_a=system.ruby.network.topology.ext_links6.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links7]
@@ -1050,8 +910,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=17
-node_a=system.ruby.network.topology.ext_links7.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links8]
@@ -1059,8 +919,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=18
-node_a=system.ruby.network.topology.ext_links8.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
 weight=1
 
 [system.ruby.network.topology.int_links9]
@@ -1068,10 +928,54 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=19
-node_a=system.ruby.network.topology.ext_links9.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
 weight=1
 
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index 096fa6972..4dc86aa94 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:34:13
-gem5 started Jul 10 2012 17:46:20
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:42:33
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 2de7fc80b..284e6ab5c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -4,111 +4,9 @@ sim_seconds                                  0.019665                       # Nu
 sim_ticks                                    19665440                       # Number of ticks simulated
 final_tick                                   19665440                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 111694                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379960                       # Number of bytes of host memory used
-host_seconds                                   176.06                       # Real time elapsed on the host
-system.l1_cntrl4.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                 168119                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370164                       # Number of bytes of host memory used
+host_seconds                                   116.97                       # Real time elapsed on the host
 system.cpu0.num_reads                           99534                       # number of read accesses completed
 system.cpu0.num_writes                          53920                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 9e9ce8534..34695a208 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -220,16 +220,11 @@ version=0
 [system.dir_cntrl0.probeFilter]
 type=RubyCache
 assoc=4
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=1024
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.funcmem]
 type=SimpleMemory
@@ -266,44 +261,29 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -344,44 +324,29 @@ version=1
 [system.l1_cntrl1.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl1.sequencer]
 type=RubySequencer
@@ -422,44 +387,29 @@ version=2
 [system.l1_cntrl2.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl2.sequencer]
 type=RubySequencer
@@ -500,44 +450,29 @@ version=3
 [system.l1_cntrl3.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl3.sequencer]
 type=RubySequencer
@@ -578,44 +513,29 @@ version=4
 [system.l1_cntrl4.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl4.sequencer]
 type=RubySequencer
@@ -656,44 +576,29 @@ version=5
 [system.l1_cntrl5.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl5.sequencer]
 type=RubySequencer
@@ -734,44 +639,29 @@ version=6
 [system.l1_cntrl6.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl6.sequencer]
 type=RubySequencer
@@ -812,44 +702,29 @@ version=7
 [system.l1_cntrl7.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl7.sequencer]
 type=RubySequencer
@@ -902,160 +777,110 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl1
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl2
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.ext_links3]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl3
-int_node=system.ruby.network.topology.ext_links3.int_node
+int_node=system.ruby.network.topology.routers3
 latency=1
 link_id=3
 weight=1
 
-[system.ruby.network.topology.ext_links3.int_node]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.ext_links4]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl4
-int_node=system.ruby.network.topology.ext_links4.int_node
+int_node=system.ruby.network.topology.routers4
 latency=1
 link_id=4
 weight=1
 
-[system.ruby.network.topology.ext_links4.int_node]
-type=BasicRouter
-router_id=4
-
 [system.ruby.network.topology.ext_links5]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl5
-int_node=system.ruby.network.topology.ext_links5.int_node
+int_node=system.ruby.network.topology.routers5
 latency=1
 link_id=5
 weight=1
 
-[system.ruby.network.topology.ext_links5.int_node]
-type=BasicRouter
-router_id=5
-
 [system.ruby.network.topology.ext_links6]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl6
-int_node=system.ruby.network.topology.ext_links6.int_node
+int_node=system.ruby.network.topology.routers6
 latency=1
 link_id=6
 weight=1
 
-[system.ruby.network.topology.ext_links6.int_node]
-type=BasicRouter
-router_id=6
-
 [system.ruby.network.topology.ext_links7]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl7
-int_node=system.ruby.network.topology.ext_links7.int_node
+int_node=system.ruby.network.topology.routers7
 latency=1
 link_id=7
 weight=1
 
-[system.ruby.network.topology.ext_links7.int_node]
-type=BasicRouter
-router_id=7
-
 [system.ruby.network.topology.ext_links8]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links8.int_node
+int_node=system.ruby.network.topology.routers8
 latency=1
 link_id=8
 weight=1
 
-[system.ruby.network.topology.ext_links8.int_node]
-type=BasicRouter
-router_id=8
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=9
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers9
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=9
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=10
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -1063,8 +888,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=11
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links3]
@@ -1072,8 +897,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=12
-node_a=system.ruby.network.topology.ext_links3.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers3
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links4]
@@ -1081,8 +906,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=13
-node_a=system.ruby.network.topology.ext_links4.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers4
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links5]
@@ -1090,8 +915,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=14
-node_a=system.ruby.network.topology.ext_links5.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers5
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links6]
@@ -1099,8 +924,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=15
-node_a=system.ruby.network.topology.ext_links6.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers6
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links7]
@@ -1108,8 +933,8 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=16
-node_a=system.ruby.network.topology.ext_links7.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers7
+node_b=system.ruby.network.topology.routers9
 weight=1
 
 [system.ruby.network.topology.int_links8]
@@ -1117,10 +942,50 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=17
-node_a=system.ruby.network.topology.ext_links8.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers8
+node_b=system.ruby.network.topology.routers9
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers4]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers5]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers6]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers7]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers8]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers9]
+type=BasicRouter
+router_id=9
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index cc01f71f1..bc60d72d3 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:16:15
-gem5 started Jul 10 2012 17:51:31
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:42:34
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 75db37f25..7c588684e 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,159 +4,9 @@ sim_seconds                                  0.019129                       # Nu
 sim_ticks                                    19129199                       # Number of ticks simulated
 final_tick                                   19129199                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 120686                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379940                       # Number of bytes of host memory used
-host_seconds                                   158.50                       # Real time elapsed on the host
-system.l1_cntrl4.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl4.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl4.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl4.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl4.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl4.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl4.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl5.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl5.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl5.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl5.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl5.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl5.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl6.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl6.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl6.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl6.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl6.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl6.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl7.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl7.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl7.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl7.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl7.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl7.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl1.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl1.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl1.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl1.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl1.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl1.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl2.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl2.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl2.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl2.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl2.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl2.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl3.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl3.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl3.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl3.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl3.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl3.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.dir_cntrl0.probeFilter.num_data_array_reads            0                       # number of data array reads
-system.dir_cntrl0.probeFilter.num_data_array_writes            0                       # number of data array writes
-system.dir_cntrl0.probeFilter.num_tag_array_reads            0                       # number of tag array reads
-system.dir_cntrl0.probeFilter.num_tag_array_writes            0                       # number of tag array writes
-system.dir_cntrl0.probeFilter.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.dir_cntrl0.probeFilter.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                 171697                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369968                       # Number of bytes of host memory used
+host_seconds                                   111.41                       # Real time elapsed on the host
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          53893                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
index f8c719b99..993287fd9 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
@@ -93,30 +93,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -152,16 +142,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -198,76 +183,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -275,10 +240,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index a5b5eb0e5..bfa4f7e73 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:30:17
-gem5 started Jul 10 2012 17:34:42
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:53:20
+gem5 started Jun  4 2012 14:40:53
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index 3aa96ab1f..f6f4e6847 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -4,26 +4,8 @@ sim_seconds                                  0.000350                       # Nu
 sim_ticks                                      349711                       # Number of ticks simulated
 final_tick                                     349711                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1546655                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230968                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                2288501                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221264                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index dc2ecd66a..a92426643 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -90,30 +90,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -148,16 +138,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -194,76 +179,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -271,10 +236,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 3eb17b7ab..473ebc3b9 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:36:02
-gem5 started Jul 10 2012 17:44:41
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:54:55
+gem5 started Jun  4 2012 14:42:00
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index da0ebfcc7..22e36183d 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,26 +4,8 @@ sim_seconds                                  0.000358                       # Nu
 sim_ticks                                      357561                       # Number of ticks simulated
 final_tick                                     357561                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 486616                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231064                       # Number of bytes of host memory used
-host_seconds                                     0.73                       # Real time elapsed on the host
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                 776030                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221440                       # Number of bytes of host memory used
+host_seconds                                     0.46                       # Real time elapsed on the host
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index ee2d6f075..529933d46 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -99,30 +99,20 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -159,16 +149,11 @@ version=0
 [system.l2_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.physmem]
 type=SimpleMemory
@@ -205,76 +190,56 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l2_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.ext_links2]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links2.int_node
+int_node=system.ruby.network.topology.routers2
 latency=1
 link_id=2
 weight=1
 
-[system.ruby.network.topology.ext_links2.int_node]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers3
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=3
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=4
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers3
 weight=1
 
 [system.ruby.network.topology.int_links2]
@@ -282,10 +247,26 @@ type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=5
-node_a=system.ruby.network.topology.ext_links2.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers3
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index f70cf8f6c..a79f03bf6 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:34:13
-gem5 started Jul 10 2012 17:49:52
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:56:32
+gem5 started Jun  4 2012 14:43:05
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index de9b59632..b667f4459 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -4,26 +4,8 @@ sim_seconds                                  0.000259                       # Nu
 sim_ticks                                      259241                       # Number of ticks simulated
 final_tick                                     259241                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1392990                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230820                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l2_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l2_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                2053459                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221360                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 22a3e7356..c79554200 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -76,16 +76,11 @@ version=0
 [system.dir_cntrl0.probeFilter]
 type=RubyCache
 assoc=4
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=1024
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
@@ -110,44 +105,29 @@ version=0
 [system.l1_cntrl0.L1DcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L1IcacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=256
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.L2cacheMemory]
 type=RubyCache
 assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
-resourceStalls=false
 size=512
 start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
 
 [system.l1_cntrl0.sequencer]
 type=RubySequencer
@@ -200,64 +180,61 @@ topology=system.ruby.network.topology
 
 [system.ruby.network.topology]
 type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
 description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 print_config=false
-routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
 
 [system.ruby.network.topology.ext_links0]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.l1_cntrl0
-int_node=system.ruby.network.topology.ext_links0.int_node
+int_node=system.ruby.network.topology.routers0
 latency=1
 link_id=0
 weight=1
 
-[system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
-router_id=0
-
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
-children=int_node
 bandwidth_factor=16
 ext_node=system.dir_cntrl0
-int_node=system.ruby.network.topology.ext_links1.int_node
+int_node=system.ruby.network.topology.routers1
 latency=1
 link_id=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
-router_id=1
-
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
-children=node_b
 bandwidth_factor=16
 latency=1
 link_id=2
-node_a=system.ruby.network.topology.ext_links0.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
 weight=1
 
-[system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
-router_id=2
-
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
 latency=1
 link_id=3
-node_a=system.ruby.network.topology.ext_links1.int_node
-node_b=system.ruby.network.topology.int_links0.node_b
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
 weight=1
 
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
 [system.ruby.profiler]
 type=RubyProfiler
 all_instructions=false
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 4942a327e..4f76e711e 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 15:16:15
-gem5 started Jul 10 2012 17:54:42
-gem5 executing on sc2b0605
+gem5 compiled Jun  4 2012 11:51:44
+gem5 started Jun  4 2012 13:42:34
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index e6a46ea4d..863fa07d3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,32 +4,8 @@ sim_seconds                                  0.000206                       # Nu
 sim_ticks                                      205611                       # Number of ticks simulated
 final_tick                                     205611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1499366                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230800                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L1IcacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.l1_cntrl0.L2cacheMemory.num_data_array_reads            0                       # number of data array reads
-system.l1_cntrl0.L2cacheMemory.num_data_array_writes            0                       # number of data array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_reads            0                       # number of tag array reads
-system.l1_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
-system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.l1_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.dir_cntrl0.probeFilter.num_data_array_reads            0                       # number of data array reads
-system.dir_cntrl0.probeFilter.num_data_array_writes            0                       # number of data array writes
-system.dir_cntrl0.probeFilter.num_tag_array_reads            0                       # number of tag array reads
-system.dir_cntrl0.probeFilter.num_tag_array_writes            0                       # number of tag array writes
-system.dir_cntrl0.probeFilter.num_tag_array_stalls            0                       # number of stalls caused by tag array
-system.dir_cntrl0.probeFilter.num_data_array_stalls            0                       # number of stalls caused by data array
+host_tick_rate                                2093129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221128                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 
 ---------- End Simulation Statistics   ----------