Regressions: Update stats due to change in MESI protocol
This commit is contained in:
Nilay Vaish
parent
5b557a314f
commit
b7cf64398f
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@ -1,6 +1,7 @@
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[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
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boot_osflags=a
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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memories=system.physmem system.funcmem
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num_work_ids=16
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physmem=system.physmem
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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@ -224,6 +231,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl0.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -275,6 +283,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl1.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -326,6 +335,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl2.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -377,6 +387,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl3.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -428,6 +439,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl4.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -479,6 +491,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl5.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -530,6 +543,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl6.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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@ -581,6 +595,7 @@ l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.l1_cntrl7.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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File diff suppressed because it is too large
Load diff
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@ -1,74 +1,74 @@
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system.cpu7: completed 10000 read, 5407 write accesses @2193104
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system.cpu5: completed 10000 read, 5417 write accesses @2227894
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system.cpu3: completed 10000 read, 5304 write accesses @2241899
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system.cpu0: completed 10000 read, 5406 write accesses @2286999
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system.cpu6: completed 10000 read, 5500 write accesses @2314615
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system.cpu2: completed 10000 read, 5192 write accesses @2332464
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system.cpu4: completed 10000 read, 5484 write accesses @2351825
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system.cpu1: completed 10000 read, 5601 write accesses @2421215
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system.cpu7: completed 20000 read, 10600 write accesses @4362574
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system.cpu2: completed 20000 read, 10442 write accesses @4540254
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system.cpu5: completed 20000 read, 10862 write accesses @4558355
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system.cpu3: completed 20000 read, 10634 write accesses @4562696
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system.cpu0: completed 20000 read, 10789 write accesses @4572225
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system.cpu6: completed 20000 read, 10964 write accesses @4613315
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system.cpu4: completed 20000 read, 10859 write accesses @4624135
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system.cpu1: completed 20000 read, 10860 write accesses @4669865
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system.cpu7: completed 30000 read, 16054 write accesses @6655525
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system.cpu0: completed 30000 read, 16092 write accesses @6770115
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system.cpu1: completed 30000 read, 16284 write accesses @6828865
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system.cpu3: completed 30000 read, 16125 write accesses @6864285
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system.cpu4: completed 30000 read, 16227 write accesses @6890965
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system.cpu6: completed 30000 read, 16336 write accesses @6904064
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system.cpu2: completed 30000 read, 15932 write accesses @6953085
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system.cpu5: completed 30000 read, 16240 write accesses @6957625
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system.cpu7: completed 40000 read, 21410 write accesses @8901178
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system.cpu0: completed 40000 read, 21509 write accesses @9069465
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system.cpu1: completed 40000 read, 21632 write accesses @9091094
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system.cpu3: completed 40000 read, 21475 write accesses @9116195
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system.cpu4: completed 40000 read, 21761 write accesses @9209395
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system.cpu5: completed 40000 read, 21553 write accesses @9245188
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system.cpu6: completed 40000 read, 21832 write accesses @9310296
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system.cpu2: completed 40000 read, 21265 write accesses @9325324
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system.cpu7: completed 50000 read, 26853 write accesses @11255815
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system.cpu0: completed 50000 read, 26977 write accesses @11286865
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system.cpu1: completed 50000 read, 27136 write accesses @11385455
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system.cpu5: completed 50000 read, 26999 write accesses @11446175
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system.cpu4: completed 50000 read, 27138 write accesses @11497105
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system.cpu3: completed 50000 read, 26925 write accesses @11513845
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system.cpu6: completed 50000 read, 27245 write accesses @11629194
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system.cpu2: completed 50000 read, 26613 write accesses @11642405
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system.cpu0: completed 60000 read, 32322 write accesses @13513714
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system.cpu7: completed 60000 read, 32300 write accesses @13580354
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system.cpu5: completed 60000 read, 32335 write accesses @13650056
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system.cpu1: completed 60000 read, 32734 write accesses @13710275
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system.cpu4: completed 60000 read, 32403 write accesses @13735965
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system.cpu2: completed 60000 read, 31942 write accesses @13824435
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system.cpu6: completed 60000 read, 32511 write accesses @13871344
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system.cpu3: completed 60000 read, 32324 write accesses @13913205
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system.cpu0: completed 70000 read, 37723 write accesses @15813186
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system.cpu7: completed 70000 read, 37805 write accesses @15917425
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system.cpu5: completed 70000 read, 37663 write accesses @15942505
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system.cpu4: completed 70000 read, 37631 write accesses @16028785
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system.cpu1: completed 70000 read, 38017 write accesses @16031454
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system.cpu3: completed 70000 read, 37707 write accesses @16112322
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system.cpu6: completed 70000 read, 37910 write accesses @16120997
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system.cpu2: completed 70000 read, 37183 write accesses @16150764
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system.cpu0: completed 80000 read, 42908 write accesses @18001745
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system.cpu5: completed 80000 read, 42901 write accesses @18163144
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system.cpu4: completed 80000 read, 42765 write accesses @18206905
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system.cpu7: completed 80000 read, 43338 write accesses @18261574
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system.cpu6: completed 80000 read, 43257 write accesses @18334555
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system.cpu1: completed 80000 read, 43298 write accesses @18408395
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system.cpu3: completed 80000 read, 43106 write accesses @18453978
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system.cpu2: completed 80000 read, 42466 write accesses @18467507
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system.cpu0: completed 90000 read, 48230 write accesses @20259175
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system.cpu5: completed 90000 read, 48356 write accesses @20526365
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system.cpu7: completed 90000 read, 48874 write accesses @20532605
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system.cpu4: completed 90000 read, 48159 write accesses @20555334
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system.cpu1: completed 90000 read, 48676 write accesses @20572365
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system.cpu6: completed 90000 read, 48688 write accesses @20703625
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system.cpu2: completed 90000 read, 47767 write accesses @20716675
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system.cpu3: completed 90000 read, 48620 write accesses @20769265
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system.cpu0: completed 100000 read, 53615 write accesses @22570074
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system.cpu7: completed 10000 read, 5315 write accesses @2178175
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system.cpu3: completed 10000 read, 5321 write accesses @2258665
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system.cpu4: completed 10000 read, 5425 write accesses @2267755
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system.cpu6: completed 10000 read, 5427 write accesses @2268141
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system.cpu0: completed 10000 read, 5406 write accesses @2273125
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system.cpu1: completed 10000 read, 5452 write accesses @2273264
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system.cpu5: completed 10000 read, 5563 write accesses @2285825
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system.cpu2: completed 10000 read, 5393 write accesses @2319830
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system.cpu6: completed 20000 read, 10754 write accesses @4478934
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system.cpu7: completed 20000 read, 10722 write accesses @4479230
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system.cpu3: completed 20000 read, 10700 write accesses @4490364
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system.cpu1: completed 20000 read, 10770 write accesses @4490415
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system.cpu2: completed 20000 read, 10639 write accesses @4498895
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system.cpu5: completed 20000 read, 10822 write accesses @4521505
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system.cpu4: completed 20000 read, 10759 write accesses @4557615
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system.cpu0: completed 20000 read, 10835 write accesses @4559745
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system.cpu2: completed 30000 read, 15995 write accesses @6715895
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system.cpu6: completed 30000 read, 16176 write accesses @6737577
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system.cpu7: completed 30000 read, 16133 write accesses @6741445
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system.cpu5: completed 30000 read, 16232 write accesses @6761017
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system.cpu1: completed 30000 read, 16230 write accesses @6767058
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system.cpu3: completed 30000 read, 16227 write accesses @6779365
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system.cpu4: completed 30000 read, 16123 write accesses @6794365
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system.cpu0: completed 30000 read, 16180 write accesses @6842625
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system.cpu5: completed 40000 read, 21501 write accesses @9004145
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system.cpu3: completed 40000 read, 21499 write accesses @9006504
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system.cpu6: completed 40000 read, 21666 write accesses @9018985
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system.cpu4: completed 40000 read, 21471 write accesses @9035325
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system.cpu7: completed 40000 read, 21682 write accesses @9038295
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system.cpu2: completed 40000 read, 21469 write accesses @9046715
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system.cpu1: completed 40000 read, 21651 write accesses @9051455
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system.cpu0: completed 40000 read, 21538 write accesses @9086675
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system.cpu6: completed 50000 read, 27114 write accesses @11277374
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system.cpu3: completed 50000 read, 26914 write accesses @11278005
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system.cpu7: completed 50000 read, 27059 write accesses @11289715
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system.cpu5: completed 50000 read, 26974 write accesses @11300494
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system.cpu2: completed 50000 read, 27018 write accesses @11307085
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system.cpu1: completed 50000 read, 26955 write accesses @11338755
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system.cpu0: completed 50000 read, 26964 write accesses @11375085
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system.cpu4: completed 50000 read, 26957 write accesses @11429764
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system.cpu6: completed 60000 read, 32482 write accesses @13471525
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system.cpu3: completed 60000 read, 32172 write accesses @13503805
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system.cpu5: completed 60000 read, 32381 write accesses @13517804
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system.cpu7: completed 60000 read, 32276 write accesses @13525105
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system.cpu2: completed 60000 read, 32332 write accesses @13536245
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system.cpu1: completed 60000 read, 32320 write accesses @13562114
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system.cpu0: completed 60000 read, 32359 write accesses @13656465
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system.cpu4: completed 60000 read, 32583 write accesses @13754744
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system.cpu5: completed 70000 read, 37779 write accesses @15741524
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system.cpu3: completed 70000 read, 37626 write accesses @15742775
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system.cpu6: completed 70000 read, 37950 write accesses @15755405
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system.cpu7: completed 70000 read, 37483 write accesses @15767164
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system.cpu1: completed 70000 read, 37652 write accesses @15806815
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system.cpu2: completed 70000 read, 37653 write accesses @15812414
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system.cpu0: completed 70000 read, 37652 write accesses @15945564
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system.cpu4: completed 70000 read, 37919 write accesses @15985575
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system.cpu7: completed 80000 read, 42762 write accesses @17959865
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system.cpu5: completed 80000 read, 43041 write accesses @17974164
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system.cpu3: completed 80000 read, 42943 write accesses @17982045
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system.cpu6: completed 80000 read, 43147 write accesses @17984384
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system.cpu1: completed 80000 read, 42940 write accesses @18041354
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system.cpu2: completed 80000 read, 43118 write accesses @18148206
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system.cpu0: completed 80000 read, 42966 write accesses @18152744
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system.cpu4: completed 80000 read, 43236 write accesses @18256215
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system.cpu5: completed 90000 read, 48432 write accesses @20226495
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system.cpu6: completed 90000 read, 48567 write accesses @20256365
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system.cpu7: completed 90000 read, 48171 write accesses @20262095
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system.cpu3: completed 90000 read, 48375 write accesses @20266104
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system.cpu1: completed 90000 read, 48524 write accesses @20337685
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system.cpu0: completed 90000 read, 48274 write accesses @20381074
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system.cpu2: completed 90000 read, 48595 write accesses @20447365
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system.cpu4: completed 90000 read, 48684 write accesses @20509404
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system.cpu3: completed 100000 read, 53763 write accesses @22495354
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hack: be nice to actually delete the event here
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@ -1,10 +1,12 @@
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Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
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Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jan 23 2012 03:44:57
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gem5 started Jan 23 2012 04:22:01
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gem5 executing on zizzer
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command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
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gem5 compiled Feb 12 2012 12:56:01
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gem5 started Feb 12 2012 12:56:15
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gem5 executing on ribera.cs.wisc.edu
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command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 22570074 because maximum number of loads reached
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Exiting @ tick 22495354 because maximum number of loads reached
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@ -1,12 +1,12 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.022570 # Number of seconds simulated
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sim_ticks 22570074 # Number of ticks simulated
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final_tick 22570074 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.022495 # Number of seconds simulated
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sim_ticks 22495354 # Number of ticks simulated
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final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_tick_rate 89999 # Simulator tick rate (ticks/s)
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host_mem_usage 347844 # Number of bytes of host memory used
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host_seconds 250.78 # Real time elapsed on the host
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host_tick_rate 204320 # Simulator tick rate (ticks/s)
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host_mem_usage 380432 # Number of bytes of host memory used
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host_seconds 110.10 # Real time elapsed on the host
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system.physmem.bytes_read 0 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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@ -19,29 +19,29 @@ system.funcmem.bytes_written 0 # Nu
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system.funcmem.num_reads 0 # Number of read requests responded to by this memory
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system.funcmem.num_writes 0 # Number of write requests responded to by this memory
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system.funcmem.num_other 0 # Number of other requests responded to by this memory
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system.cpu0.num_reads 100000 # number of read accesses completed
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system.cpu0.num_writes 53615 # number of write accesses completed
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system.cpu0.num_reads 99326 # number of read accesses completed
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system.cpu0.num_writes 53132 # number of write accesses completed
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system.cpu0.num_copies 0 # number of copy accesses completed
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system.cpu1.num_reads 98926 # number of read accesses completed
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system.cpu1.num_writes 53490 # number of write accesses completed
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system.cpu1.num_reads 99634 # number of read accesses completed
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system.cpu1.num_writes 53798 # number of write accesses completed
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system.cpu1.num_copies 0 # number of copy accesses completed
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system.cpu2.num_reads 98053 # number of read accesses completed
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system.cpu2.num_writes 52227 # number of write accesses completed
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system.cpu2.num_reads 99031 # number of read accesses completed
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system.cpu2.num_writes 53441 # number of write accesses completed
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system.cpu2.num_copies 0 # number of copy accesses completed
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system.cpu3.num_reads 98222 # number of read accesses completed
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system.cpu3.num_writes 53057 # number of write accesses completed
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system.cpu3.num_reads 100000 # number of read accesses completed
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system.cpu3.num_writes 53763 # number of write accesses completed
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system.cpu3.num_copies 0 # number of copy accesses completed
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system.cpu4.num_reads 98292 # number of read accesses completed
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system.cpu4.num_writes 52603 # number of write accesses completed
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system.cpu4.num_reads 98726 # number of read accesses completed
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system.cpu4.num_writes 53438 # number of write accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
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system.cpu5.num_reads 98988 # number of read accesses completed
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system.cpu5.num_writes 53055 # number of write accesses completed
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system.cpu5.num_reads 99955 # number of read accesses completed
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system.cpu5.num_writes 53794 # number of write accesses completed
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system.cpu5.num_copies 0 # number of copy accesses completed
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system.cpu6.num_reads 98007 # number of read accesses completed
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system.cpu6.num_writes 53041 # number of write accesses completed
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system.cpu6.num_reads 99893 # number of read accesses completed
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system.cpu6.num_writes 53796 # number of write accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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system.cpu7.num_reads 99081 # number of read accesses completed
|
||||
system.cpu7.num_writes 53785 # number of write accesses completed
|
||||
system.cpu7.num_reads 99993 # number of read accesses completed
|
||||
system.cpu7.num_writes 53567 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
full_system=false
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
|
@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
|
|||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy tester
|
||||
boot_osflags=a
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -78,6 +85,7 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/23/2012 04:22:04
|
||||
Real time: Feb/12/2012 12:56:15
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.63
|
||||
Virtual_time_in_minutes: 0.0105
|
||||
Virtual_time_in_hours: 0.000175
|
||||
Virtual_time_in_days: 7.29167e-06
|
||||
Virtual_time_in_seconds: 0.46
|
||||
Virtual_time_in_minutes: 0.00766667
|
||||
Virtual_time_in_hours: 0.000127778
|
||||
Virtual_time_in_days: 5.32407e-06
|
||||
|
||||
Ruby_current_time: 363611
|
||||
Ruby_current_time: 366301
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 363611
|
||||
Ruby_cycles: 366301
|
||||
|
||||
mbytes_resident: 39.3828
|
||||
mbytes_total: 209.344
|
||||
resident_ratio: 0.188125
|
||||
mbytes_resident: 39.4219
|
||||
mbytes_total: 241.242
|
||||
resident_ratio: 0.163461
|
||||
|
||||
ruby_cycles_executed: [ 363612 ]
|
||||
ruby_cycles_executed: [ 366302 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -66,15 +66,15 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1005 average: 15.8269 | standard deviation: 1.12204 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 55 936 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1006 average: 15.8469 | standard deviation: 1.1157 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 35 957 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 45325 count: 990 average: 5734.15 | standard deviation: 8337.32 | 76 21 69 108 63 78 75 44 25 38 32 18 17 15 12 7 10 11 13 11 7 5 7 8 2 2 3 1 3 1 4 4 4 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 4 5 2 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 7 8 2 5 6 4 2 0 3 4 3 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 2 0 2 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 256 max: 45325 count: 45 average: 7821.33 | standard deviation: 10900.5 | 7 0 1 6 1 1 4 1 2 4 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 256 max: 43192 count: 890 average: 5921.87 | standard deviation: 8354.16 | 69 16 57 85 53 68 69 41 23 34 32 16 16 15 12 7 10 10 13 11 7 5 7 8 2 2 3 1 3 0 4 4 3 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 3 5 0 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 5 7 2 5 6 3 2 0 3 3 2 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 1 0 2 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 1980 count: 55 average: 988.782 | standard deviation: 366.735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 1 1 2 3 0 0 3 0 3 3 0 2 1 1 2 0 1 0 1 0 0 0 1 1 0 0 1 0 0 3 0 0 0 2 1 0 1 1 1 1 1 0 1 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 256 max: 45325 count: 990 average: 5734.15 | standard deviation: 8337.32 | 76 21 69 108 63 78 75 44 25 38 32 18 17 15 12 7 10 11 13 11 7 5 7 8 2 2 3 1 3 1 4 4 4 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 4 5 2 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 7 8 2 5 6 4 2 0 3 4 3 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 2 0 2 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 8679 count: 991 average: 5857.33 | standard deviation: 2249.49 | 58 7 1 1 1 0 3 2 3 1 4 10 1 4 5 6 6 3 1 5 1 4 4 2 2 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 9 3 6 5 11 12 16 25 25 27 21 16 26 37 28 18 27 29 32 30 33 30 43 30 22 35 23 25 22 21 30 11 12 11 21 8 7 8 5 6 8 4 7 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 8181 count: 42 average: 5660.79 | standard deviation: 2406.12 | 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 3 0 3 1 0 0 0 3 1 1 0 1 2 2 0 0 0 2 2 2 2 1 2 0 2 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8679 count: 891 average: 6182.81 | standard deviation: 1925.75 | 53 6 0 0 1 0 2 1 1 0 1 2 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 8 3 6 4 10 9 16 22 24 27 21 16 23 36 27 18 26 27 30 30 33 30 41 28 20 33 22 23 22 19 30 11 11 11 20 8 7 8 5 6 8 4 6 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 16 max: 1864 count: 58 average: 999.586 | standard deviation: 349.911 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 2 0 1 0 4 1 2 1 0 0 0 0 3 0 0 0 3 0 2 0 1 1 2 1 0 1 3 2 2 0 0 0 1 0 0 0 1 1 0 3 1 0 0 0 1 1 1 1 1 0 1 2 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 64 max: 8679 count: 991 average: 5857.33 | standard deviation: 2249.49 | 58 7 1 1 1 0 3 2 3 1 4 10 1 4 5 6 6 3 1 5 1 4 4 2 2 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 9 3 6 5 11 12 16 25 25 27 21 16 26 37 28 18 27 29 32 30 33 30 43 30 22 35 23 25 22 21 30 11 12 11 21 8 7 8 5 6 8 4 7 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 256 max: 45325 count: 45 average: 7821.33 | standard deviation: 10900.5 | 7 0 1 6 1 1 4 1 2 4 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_NULL: [binsize: 256 max: 43192 count: 890 average: 5921.87 | standard deviation: 8354.16 | 69 16 57 85 53 68 69 41 23 34 32 16 16 15 12 7 10 10 13 11 7 5 7 8 2 2 3 1 3 0 4 4 3 1 1 1 4 0 1 1 1 0 1 1 1 0 2 0 2 1 3 1 1 4 3 1 2 1 3 0 2 3 2 3 5 0 5 1 3 1 1 1 0 3 4 2 3 5 2 2 3 4 6 2 5 5 7 2 5 6 3 2 0 3 3 2 4 3 0 0 4 2 2 1 0 1 2 0 2 0 1 1 0 2 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 1980 count: 55 average: 988.782 | standard deviation: 366.735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 1 1 2 3 0 0 3 0 3 3 0 2 1 1 2 0 1 0 1 0 0 0 1 1 0 0 1 0 0 3 0 0 0 2 1 0 1 1 1 1 1 0 1 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 64 max: 8181 count: 42 average: 5660.79 | standard deviation: 2406.12 | 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 3 0 3 1 0 0 0 3 1 1 0 1 2 2 0 0 0 2 2 2 2 1 2 0 2 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 64 max: 8679 count: 891 average: 6182.81 | standard deviation: 1925.75 | 53 6 0 0 1 0 2 1 1 0 1 2 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 2 1 3 3 8 3 6 4 10 9 16 22 24 27 21 16 23 36 27 18 26 27 30 30 33 30 41 28 20 33 22 23 22 19 30 11 11 11 20 8 7 8 5 6 8 4 6 2 2 1 2 0 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_NULL: [binsize: 16 max: 1864 count: 58 average: 999.586 | standard deviation: 349.911 | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 2 0 1 0 4 1 2 1 0 0 0 0 3 0 0 0 3 0 2 0 1 1 2 1 0 1 3 2 2 0 0 0 1 0 0 0 1 1 0 3 1 0 0 0 1 1 1 1 1 0 1 2 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -101,12 +101,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 64 max: 1871 count: 7077 average: 36.6084 | standard deviation: 151.734 | 6477 143 39 71 25 30 49 30 38 33 27 37 15 21 8 10 2 3 2 2 2 3 1 0 4 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 10 count: 4540 average: 0.27511 | standard deviation: 0.967186 | 4062 142 118 124 37 26 11 11 5 2 2 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 1871 count: 2537 average: 101.628 | standard deviation: 240.096 | 1937 143 39 71 25 30 49 30 38 33 27 37 15 21 8 10 2 3 2 2 2 3 1 0 4 1 2 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_delay_cycles: [binsize: 64 max: 1983 count: 7123 average: 42.2206 | standard deviation: 170.679 | 6474 162 29 70 40 20 46 28 39 41 18 41 16 18 24 9 6 6 11 4 4 5 1 4 1 2 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 12 count: 4572 average: 0.276903 | standard deviation: 0.988226 | 4110 109 134 119 38 30 14 11 2 1 2 0 2 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 64 max: 1983 count: 2551 average: 117.394 | standard deviation: 269.356 | 1902 162 29 70 40 20 46 28 39 41 18 41 16 18 24 9 6 6 11 4 4 5 1 4 1 2 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 551 average: 0.136116 | standard deviation: 0.766337 | 529 4 3 6 4 2 1 1 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 10 count: 3989 average: 0.294309 | standard deviation: 0.990299 | 3533 138 115 118 33 24 10 10 4 2 2 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 7 count: 549 average: 0.142077 | standard deviation: 0.713529 | 523 4 7 6 5 3 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 12 count: 4023 average: 0.295302 | standard deviation: 1.01872 | 3587 105 127 113 33 27 14 10 2 1 2 0 2 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -119,148 +119,148 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10428
|
||||
page_faults: 0
|
||||
page_reclaims: 11076
|
||||
page_faults: 18
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 80
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 5404 43232
|
||||
total_msg_count_Request_Control: 1653 13224
|
||||
total_msg_count_Response_Data: 7779 560088
|
||||
total_msg_count_Response_Control: 7929 63432
|
||||
total_msg_count_Writeback_Data: 3666 263952
|
||||
total_msg_count_Control: 5469 43752
|
||||
total_msg_count_Request_Control: 1647 13176
|
||||
total_msg_count_Response_Data: 7878 567216
|
||||
total_msg_count_Response_Control: 8000 64000
|
||||
total_msg_count_Writeback_Data: 3657 263304
|
||||
total_msg_count_Writeback_Control: 93 744
|
||||
total_msgs: 26524 total_bytes: 944672
|
||||
total_msgs: 26744 total_bytes: 952192
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 1.54279
|
||||
links_utilized_percent_switch_0_link_0: 1.3161 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.76947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 1.53514
|
||||
links_utilized_percent_switch_0_link_0: 1.31572 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 1.75457 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 918 66096 [ 0 918 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 758 6064 [ 0 758 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 919 7352 [ 919 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 919 7352 [ 0 57 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 32 256 [ 32 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 759 6072 [ 0 759 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 926 7408 [ 0 59 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.70619
|
||||
links_utilized_percent_switch_1_link_0: 2.98272 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.42966 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.70775
|
||||
links_utilized_percent_switch_1_link_0: 2.97815 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.43734 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 918 7344 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1798 14384 [ 0 936 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 30 240 [ 30 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1710 123120 [ 0 1710 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 845 6760 [ 0 845 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1817 14536 [ 0 951 866 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1729 124488 [ 0 1729 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 849 6792 [ 0 849 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 1.16361
|
||||
links_utilized_percent_switch_2_link_0: 1.11355 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.21366 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 1.17246
|
||||
links_utilized_percent_switch_2_link_0: 1.12121 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 1.22372 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 792 57024 [ 0 792 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 879 7032 [ 0 879 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 803 57816 [ 0 803 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 90 720 [ 0 90 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 892 7136 [ 0 892 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 1.80417
|
||||
links_utilized_percent_switch_3_link_0: 1.3161 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 2.98286 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.11355 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 1.80521
|
||||
links_utilized_percent_switch_3_link_0: 1.31613 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 2.97829 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 1.12121 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 551 4408 [ 551 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 918 66096 [ 0 918 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 758 6064 [ 0 758 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 918 7344 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1798 14384 [ 0 936 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1222 87984 [ 728 494 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 549 4392 [ 549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 759 6072 [ 0 759 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 926 7408 [ 926 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 897 64584 [ 0 897 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1818 14544 [ 0 951 867 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1219 87768 [ 729 490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 31 248 [ 31 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 883 7064 [ 883 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 792 57024 [ 0 792 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 897 7176 [ 897 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 803 57816 [ 0 803 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 90 720 [ 0 90 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 55
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 55
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 58
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 58
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 55 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 58 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 865
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 865
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 870
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 870
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.50867%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.4913%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 4.13793%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 95.8621%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 865 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 870 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [45 ] 45
|
||||
Ifetch [147 ] 147
|
||||
Store [894 ] 894
|
||||
Inv [551 ] 551
|
||||
L1_Replacement [512283 ] 512283
|
||||
Load [42 ] 42
|
||||
Ifetch [63 ] 63
|
||||
Store [893 ] 893
|
||||
Inv [549 ] 549
|
||||
L1_Replacement [10707 ] 10707
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [38 ] 38
|
||||
Data_Exclusive [36 ] 36
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [880 ] 880
|
||||
Data_all_Acks [890 ] 890
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [758 ] 758
|
||||
WB_Ack [759 ] 759
|
||||
|
||||
- Transitions -
|
||||
NP Load [39 ] 39
|
||||
NP Ifetch [55 ] 55
|
||||
NP Store [826 ] 826
|
||||
NP Inv [3 ] 3
|
||||
NP Load [36 ] 36
|
||||
NP Ifetch [58 ] 58
|
||||
NP Store [834 ] 834
|
||||
NP Inv [4 ] 4
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
I Store [0 ] 0
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [147 ] 147
|
||||
I L1_Replacement [154 ] 154
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Inv [29 ] 29
|
||||
S L1_Replacement [8 ] 8
|
||||
S Inv [32 ] 32
|
||||
S L1_Replacement [7 ] 7
|
||||
|
||||
E Load [0 ] 0
|
||||
E Ifetch [0 ] 0
|
||||
E Store [0 ] 0
|
||||
E Inv [6 ] 6
|
||||
E Inv [4 ] 4
|
||||
E L1_Replacement [32 ] 32
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
|
|
@ -268,9 +268,9 @@ E Fwd_GET_INSTR [0 ] 0
|
|||
|
||||
M Load [6 ] 6
|
||||
M Ifetch [0 ] 0
|
||||
M Store [66 ] 66
|
||||
M Inv [95 ] 95
|
||||
M L1_Replacement [728 ] 728
|
||||
M Store [59 ] 59
|
||||
M Inv [101 ] 101
|
||||
M L1_Replacement [730 ] 730
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
|
@ -279,18 +279,18 @@ IS Load [0 ] 0
|
|||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [19 ] 19
|
||||
IS L1_Replacement [23106 ] 23106
|
||||
IS Data_Exclusive [38 ] 38
|
||||
IS L1_Replacement [418 ] 418
|
||||
IS Data_Exclusive [36 ] 36
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [37 ] 37
|
||||
IS Data_all_Acks [39 ] 39
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [488262 ] 488262
|
||||
IM L1_Replacement [9366 ] 9366
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [824 ] 824
|
||||
IM Data_all_Acks [832 ] 832
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -311,97 +311,92 @@ IS_I DataS_fromL1 [0 ] 0
|
|||
IS_I Data_all_Acks [19 ] 19
|
||||
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [92 ] 92
|
||||
M_I Store [1 ] 1
|
||||
M_I Inv [399 ] 399
|
||||
M_I Ifetch [5 ] 5
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [389 ] 389
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [359 ] 359
|
||||
|
||||
E_I Load [0 ] 0
|
||||
E_I Ifetch [0 ] 0
|
||||
E_I Store [0 ] 0
|
||||
E_I L1_Replacement [0 ] 0
|
||||
M_I WB_Ack [371 ] 371
|
||||
|
||||
SINK_WB_ACK Load [0 ] 0
|
||||
SINK_WB_ACK Ifetch [0 ] 0
|
||||
SINK_WB_ACK Store [1 ] 1
|
||||
SINK_WB_ACK Store [0 ] 0
|
||||
SINK_WB_ACK Inv [0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 ] 0
|
||||
SINK_WB_ACK WB_Ack [399 ] 399
|
||||
SINK_WB_ACK WB_Ack [388 ] 388
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 883
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 883
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 897
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 897
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.30351%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 5.77576%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.9207%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 4.01338%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.13155%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.8551%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 883 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 897 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [55 ] 55
|
||||
L1_GETS [39 ] 39
|
||||
L1_GETX [824 ] 824
|
||||
L1_GET_INSTR [58 ] 58
|
||||
L1_GETS [36 ] 36
|
||||
L1_GETX [832 ] 832
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [383 ] 383
|
||||
L1_PUTX_old [3508 ] 3508
|
||||
L1_PUTX [377 ] 377
|
||||
L1_PUTX_old [757 ] 757
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [314 ] 314
|
||||
L2_Replacement_clean [23024 ] 23024
|
||||
Mem_Data [883 ] 883
|
||||
Mem_Ack [879 ] 879
|
||||
WB_Data [478 ] 478
|
||||
WB_Data_clean [16 ] 16
|
||||
L2_Replacement [331 ] 331
|
||||
L2_Replacement_clean [1184 ] 1184
|
||||
Mem_Data [897 ] 897
|
||||
Mem_Ack [892 ] 892
|
||||
WB_Data [472 ] 472
|
||||
WB_Data_clean [18 ] 18
|
||||
Ack [0 ] 0
|
||||
Ack_all [57 ] 57
|
||||
Ack_all [59 ] 59
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [861 ] 861
|
||||
Exclusive_Unblock [866 ] 866
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [51 ] 51
|
||||
NP L1_GETS [38 ] 38
|
||||
NP L1_GETX [794 ] 794
|
||||
NP L1_GET_INSTR [55 ] 55
|
||||
NP L1_GETS [36 ] 36
|
||||
NP L1_GETX [806 ] 806
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [146 ] 146
|
||||
NP L1_PUTX_old [259 ] 259
|
||||
|
||||
SS L1_GET_INSTR [1 ] 1
|
||||
SS L1_GETS [1 ] 1
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [3 ] 3
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [51 ] 51
|
||||
SS L2_Replacement_clean [55 ] 55
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [3 ] 3
|
||||
M L1_GETS [0 ] 0
|
||||
M L1_GETX [27 ] 27
|
||||
M L1_GETX [23 ] 23
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [314 ] 314
|
||||
M L2_Replacement_clean [14 ] 14
|
||||
M L2_Replacement [331 ] 331
|
||||
M L2_Replacement_clean [13 ] 13
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [359 ] 359
|
||||
MT L1_PUTX [371 ] 371
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L2_Replacement_clean [500 ] 500
|
||||
MT L2_Replacement_clean [494 ] 494
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -409,8 +404,8 @@ M_I L1_GETS [0 ] 0
|
|||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [253 ] 253
|
||||
M_I Mem_Ack [879 ] 879
|
||||
M_I L1_PUTX_old [129 ] 129
|
||||
M_I Mem_Ack [892 ] 892
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -429,10 +424,10 @@ MCT_I L1_GETS [0 ] 0
|
|||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [1514 ] 1514
|
||||
MCT_I WB_Data [478 ] 478
|
||||
MCT_I WB_Data_clean [16 ] 16
|
||||
MCT_I Ack_all [6 ] 6
|
||||
MCT_I L1_PUTX_old [176 ] 176
|
||||
MCT_I WB_Data [472 ] 472
|
||||
MCT_I WB_Data_clean [18 ] 18
|
||||
MCT_I Ack_all [4 ] 4
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
|
|
@ -441,7 +436,7 @@ I_I L1_UPGRADE [0 ] 0
|
|||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [51 ] 51
|
||||
I_I Ack_all [55 ] 55
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
|
|
@ -459,8 +454,8 @@ ISS L1_GETX [0 ] 0
|
|||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [526 ] 526
|
||||
ISS Mem_Data [38 ] 38
|
||||
ISS L2_Replacement_clean [3 ] 3
|
||||
ISS Mem_Data [36 ] 36
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -469,8 +464,8 @@ IS L1_GETX [0 ] 0
|
|||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [1318 ] 1318
|
||||
IS Mem_Data [51 ] 51
|
||||
IS L2_Replacement_clean [69 ] 69
|
||||
IS Mem_Data [55 ] 55
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -479,8 +474,8 @@ IM L1_GETX [0 ] 0
|
|||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [9234 ] 9234
|
||||
IM Mem_Data [794 ] 794
|
||||
IM L2_Replacement_clean [231 ] 231
|
||||
IM Mem_Data [806 ] 806
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -499,12 +494,12 @@ MT_MB L1_GET_INSTR [0 ] 0
|
|||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [24 ] 24
|
||||
MT_MB L1_PUTX_old [1595 ] 1595
|
||||
MT_MB L1_PUTX [6 ] 6
|
||||
MT_MB L1_PUTX_old [193 ] 193
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [11381 ] 11381
|
||||
MT_MB L2_Replacement_clean [319 ] 319
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [858 ] 858
|
||||
MT_MB Exclusive_Unblock [863 ] 863
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -556,37 +551,37 @@ MT_SB Unblock [0 ] 0
|
|||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1675
|
||||
memory_reads: 883
|
||||
memory_writes: 792
|
||||
memory_refreshes: 758
|
||||
memory_total_request_delays: 1135
|
||||
memory_delays_per_request: 0.677612
|
||||
memory_delays_in_input_queue: 142
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 990
|
||||
memory_stalls_for_bank_busy: 236
|
||||
memory_total_requests: 1700
|
||||
memory_reads: 897
|
||||
memory_writes: 802
|
||||
memory_refreshes: 763
|
||||
memory_total_request_delays: 1143
|
||||
memory_delays_per_request: 0.672353
|
||||
memory_delays_in_input_queue: 158
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 983
|
||||
memory_stalls_for_bank_busy: 180
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 85
|
||||
memory_stalls_for_bus: 355
|
||||
memory_stalls_for_arbitration: 84
|
||||
memory_stalls_for_bus: 390
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 236
|
||||
memory_stalls_for_read_read_turnaround: 78
|
||||
accesses_per_bank: 45 47 58 82 66 78 55 33 49 52 38 55 46 40 51 49 52 40 55 65 70 48 54 42 54 49 52 46 55 52 44 53
|
||||
memory_stalls_for_read_write_turnaround: 247
|
||||
memory_stalls_for_read_read_turnaround: 82
|
||||
accesses_per_bank: 52 56 61 98 64 67 64 53 45 52 56 48 55 35 40 46 42 46 59 50 52 46 56 44 56 57 52 59 52 58 40 39
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [883 ] 883
|
||||
Data [792 ] 792
|
||||
Memory_Data [883 ] 883
|
||||
Memory_Ack [792 ] 792
|
||||
Fetch [897 ] 897
|
||||
Data [803 ] 803
|
||||
Memory_Data [897 ] 897
|
||||
Memory_Ack [802 ] 802
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [87 ] 87
|
||||
CleanReplacement [90 ] 90
|
||||
|
||||
- Transitions -
|
||||
I Fetch [883 ] 883
|
||||
I Fetch [897 ] 897
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -602,20 +597,20 @@ ID_W Memory_Ack [0 ] 0
|
|||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [792 ] 792
|
||||
M Data [803 ] 803
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [87 ] 87
|
||||
M CleanReplacement [90 ] 90
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [883 ] 883
|
||||
IM Memory_Data [897 ] 897
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [792 ] 792
|
||||
MI Memory_Ack [802 ] 802
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 23 2012 03:44:57
|
||||
gem5 started Jan 23 2012 04:22:03
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
gem5 compiled Feb 12 2012 12:56:01
|
||||
gem5 started Feb 12 2012 12:56:15
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 363611 because Ruby Tester completed
|
||||
Exiting @ tick 366301 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000364 # Number of seconds simulated
|
||||
sim_ticks 363611 # Number of ticks simulated
|
||||
final_tick 363611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000366 # Number of seconds simulated
|
||||
sim_ticks 366301 # Number of ticks simulated
|
||||
final_tick 366301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 742759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214372 # Number of bytes of host memory used
|
||||
host_seconds 0.49 # Real time elapsed on the host
|
||||
host_tick_rate 1737283 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247036 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
system.physmem.bytes_read 0 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 0 # Number of bytes written to this memory
|
||||
|
|
|
|||
Loading…
Reference in a new issue