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stats: update stats for previous cset

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Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
This commit is contained in:
Steve Reinhardt 2010-09-21 23:07:35 -07:00
parent e918536380
commit 13a15c55a4
115 changed files with 8078 additions and 8472 deletions
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2
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
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@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:56:01
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -46,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 169506496500 because target called exit()
Exiting @ tick 165376986500 because target called exit()

649
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 178555 # Simulator instruction rate (inst/s)
host_mem_usage 207544 # Number of bytes of host memory used
host_seconds 3167.39 # Real time elapsed on the host
host_tick_rate 53516139 # Simulator tick rate (ticks/s)
host_inst_rate 264030 # Simulator instruction rate (inst/s)
host_mem_usage 193748 # Number of bytes of host memory used
host_seconds 2142.00 # Real time elapsed on the host
host_tick_rate 77206740 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.169506 # Number of seconds simulated
sim_ticks 169506496500 # Number of ticks simulated
sim_seconds 0.165377 # Number of seconds simulated
sim_ticks 165376986500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 # Number of instructions committed
system.cpu.commit.COM:loads 115049510 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads
system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks.
system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153171054 # number of overall hits
system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3157471 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses
system.cpu.dcache.overall_hits 152530559 # number of overall hits
system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1933689 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 471007 # number of replacements
system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 471004 # number of replacements
system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use
system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 336082 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 163170180 # DTB accesses
system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use
system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 423151 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 163094811 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 163108618 # DTB hits
system.cpu.dtb.data_misses 61562 # DTB misses
system.cpu.dtb.data_hits 163045966 # DTB hits
system.cpu.dtb.data_misses 48845 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 122378622 # DTB read accesses
system.cpu.dtb.read_accesses 122278185 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 122354151 # DTB read hits
system.cpu.dtb.read_misses 24471 # DTB read misses
system.cpu.dtb.write_accesses 40791558 # DTB write accesses
system.cpu.dtb.read_hits 122255138 # DTB read hits
system.cpu.dtb.read_misses 23047 # DTB read misses
system.cpu.dtb.write_accesses 40816626 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 40754467 # DTB write hits
system.cpu.dtb.write_misses 37091 # DTB write misses
system.cpu.fetch.Branches 76519042 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65743933 # Number of cache lines fetched
system.cpu.fetch.Cycles 196171036 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1323544 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 700543147 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4180854 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.225711 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65743933 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 65741179 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.066420 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 337425275 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.076143 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.069329 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 40790828 # DTB write hits
system.cpu.dtb.write_misses 25798 # DTB write misses
system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched
system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 206998212 61.35% 61.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10205574 3.02% 64.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 16013127 4.75% 69.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13976667 4.14% 73.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12062274 3.57% 76.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13987466 4.15% 80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5886424 1.74% 82.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3487900 1.03% 83.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 54807631 16.24% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 337425275 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 65743933 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36198.392555 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65742751 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 42786500 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1182 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32385000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 912 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 72086.349781 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 65743933 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36198.392555 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency
system.cpu.icache.demand_hits 65742751 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 42786500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
system.cpu.icache.demand_misses 1182 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32385000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 912 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.379446 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 777.105869 # Average occupied blocks per context
system.cpu.icache.overall_accesses 65743933 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36198.392555 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context
system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 65742751 # number of overall hits
system.cpu.icache.overall_miss_latency 42786500 # number of overall miss cycles
system.cpu.icache.overall_hits 65648097 # number of overall hits
system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
system.cpu.icache.overall_misses 1182 # number of overall misses
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32385000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1178 # number of overall misses
system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 912 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 36 # number of replacements
system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks.
system.cpu.icache.replacements 32 # number of replacements
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 777.105869 # Cycle average of tags in use
system.cpu.icache.total_refs 65742751 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use
system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1587719 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67446690 # Number of branches executed
system.cpu.iew.EXEC:nop 43287555 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.768234 # Inst execution rate
system.cpu.iew.EXEC:refs 164109637 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41186586 # Number of stores executed
system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67433622 # Number of branches executed
system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate
system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41211382 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 494218268 # num instructions consuming a value
system.cpu.iew.WB:count 596241723 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.805354 # average fanout of values written-back
system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value
system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 398020536 # num instructions producing a value
system.cpu.iew.WB:rate 1.758758 # insts written-back per cycle
system.cpu.iew.WB:sent 597367655 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4601660 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2251946 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 127252956 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3156398 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 43259984 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 665052109 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 122923051 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6371334 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 599454333 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2449 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 397916939 # num instructions producing a value
system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle
system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 33854 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 10007520 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 83713 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 175 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 5470953 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 10609 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 93535 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5935 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 12203446 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3447461 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 93535 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 944573 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3657087 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.668232 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.668232 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438988101 72.46% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6710 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 124874272 20.61% 93.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956540 6.93% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 605825667 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 6927509 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011435 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5320205 76.80% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 51 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 1245764 17.98% 94.78% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 361489 5.22% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 337425275 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.795437 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.663310 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 95395357 28.27% 28.27% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 68329461 20.25% 48.52% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 80056631 23.73% 72.25% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 36910615 10.94% 83.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 31840128 9.44% 92.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 12299933 3.65% 96.27% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 10951663 3.25% 99.51% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1050952 0.31% 99.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 590535 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 337425275 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.787028 # Inst issue rate
system.cpu.iq.iqInstsAdded 621764526 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605825667 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 54809333 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 18475 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 31050369 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate
system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 65743973 # ITB accesses
system.cpu.itb.fetch_accesses 65649312 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 65743933 # ITB hits
system.cpu.itb.fetch_misses 40 # ITB misses
system.cpu.itb.fetch_hits 65649275 # ITB hits
system.cpu.itb.fetch_misses 37 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,107 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 256831 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12642 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 8367822000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.950777 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 244189 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7606267000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950777 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 244189 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 219184 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 183819 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1213040500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.161348 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 35365 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1096881500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.161348 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 35365 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 79334 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2708405000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 79334 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2461697500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 79334 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 336082 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 336082 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5312.500000 # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.798768 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 382500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 476015 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34271.956402 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 196461 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9580862500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.587280 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 279554 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 8703148500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.587280 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 279554 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052597 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.448200 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1723.488326 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14686.601231 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 476015 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34271.956402 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 196461 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9580862500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.587280 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 279554 # number of overall misses
system.cpu.l2cache.overall_hits 383257 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 92753 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 8703148500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.587280 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 279554 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 84626 # number of replacements
system.cpu.l2cache.sampled_refs 100342 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 74446 # number of replacements
system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16410.089557 # Cycle average of tags in use
system.cpu.l2cache.total_refs 381176 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use
system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 62683 # number of writebacks
system.cpu.memDep0.conflictingLoads 23861424 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 18454491 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 127252956 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 43259984 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 339012994 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14846495 # Number of cycles rename is blocking
system.cpu.l2cache.writebacks 59324 # number of writebacks
system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 330753974 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 36228613 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 153406470 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1884931 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 97 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 897942713 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 681539497 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 519842559 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 115704820 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 10007520 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 43459223 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 55987670 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 747 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 87364721 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed
system.cpu.timesIdled 36935 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:59:22
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:13:16
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -46,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 777351681000 because target called exit()
Exiting @ tick 765623032000 because target called exit()

181
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1386497 # Simulator instruction rate (inst/s)
host_mem_usage 206712 # Number of bytes of host memory used
host_seconds 434.08 # Real time elapsed on the host
host_tick_rate 1790782589 # Simulator tick rate (ticks/s)
host_inst_rate 1603392 # Simulator instruction rate (inst/s)
host_mem_usage 192888 # Number of bytes of host memory used
host_seconds 375.37 # Real time elapsed on the host
host_tick_rate 2039675547 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.777352 # Number of seconds simulated
sim_ticks 777351681000 # Number of ticks simulated
sim_seconds 0.765623 # Number of seconds simulated
sim_ticks 765623032000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4227398000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3623702000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39124493 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 17781358000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.008284 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 326828 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 16800874000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008284 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 326828 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 41678.513805 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153437303 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 22008756000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003430 # miss rate for demand accesses
system.cpu.dcache.demand_misses 528060 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 20424576000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003430 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 528060 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999560 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.197079 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.999553 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 41678.513805 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153437303 # number of overall hits
system.cpu.dcache.overall_miss_latency 22008756000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003430 # miss rate for overall accesses
system.cpu.dcache.overall_misses 528060 # number of overall misses
system.cpu.dcache.overall_hits 153509968 # number of overall hits
system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_misses 455395 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 20424576000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003430 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 528060 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325740 # number of writebacks
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 408190 # number of writebacks
system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 153965363 # DTB hits
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 673.252668 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.328778 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,37 +164,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12405 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12571416000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.951193 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 241758 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9670320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.951193 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 167657 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1787240000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.170126 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34370 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1374800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170126 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34370 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 72665 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 72665 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2906600000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 325740 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.553777 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 180062 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 14358656000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.605292 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 276128 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 11045120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.605292 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052155 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.448358 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1709.012624 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14691.802112 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.052565 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.491366 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 180062 # number of overall hits
system.cpu.l2cache.overall_miss_latency 14358656000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.605292 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 276128 # number of overall misses
system.cpu.l2cache.overall_hits 364159 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 92031 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 83906 # number of replacements
system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 73734 # number of replacements
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use
system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 62672 # number of writebacks
system.cpu.l2cache.writebacks 59341 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1554703362 # number of cpu cycles simulated
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154866966 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

2
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:54:54
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:05:18
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -45,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 807517408000 because target called exit()
Exiting @ tick 796759936000 because target called exit()

179
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1492183 # Simulator instruction rate (inst/s)
host_mem_usage 211112 # Number of bytes of host memory used
host_seconds 401.17 # Real time elapsed on the host
host_tick_rate 2012902303 # Simulator tick rate (ticks/s)
host_inst_rate 1338185 # Simulator instruction rate (inst/s)
host_mem_usage 196956 # Number of bytes of host memory used
host_seconds 447.34 # Real time elapsed on the host
host_tick_rate 1781116972 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated
sim_seconds 0.807517 # Number of seconds simulated
sim_ticks 807517408000 # Number of ticks simulated
sim_seconds 0.796760 # Number of seconds simulated
sim_ticks 796759936000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses
system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses
system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 216715375 # number of overall hits
system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses
system.cpu.dcache.overall_misses 497093 # number of overall misses
system.cpu.dcache.overall_hits 216774877 # number of overall hits
system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses
system.cpu.dcache.overall_misses 437591 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 433495 # number of replacements
system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 305501 # number of writebacks
system.cpu.dcache.writebacks 392389 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context
system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use
system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use
system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 170026 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 268208 # number of overall misses
system.cpu.l2cache.overall_hits 348237 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 89997 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 80841 # number of replacements
system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 71809 # number of replacements
system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use
system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 60805 # number of writebacks
system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1615034816 # number of cpu cycles simulated
system.cpu.numCycles 1593519872 # number of cpu cycles simulated
system.cpu.num_insts 598619824 # Number of instructions executed
system.cpu.num_refs 219174038 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

2
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:05:09
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:20:33
M5 executing on phenom
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -45,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1088441503500 because target called exit()
Exiting @ tick 1095331467500 because target called exit()

649
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,423 +1,414 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 76473 # Simulator instruction rate (inst/s)
host_mem_usage 212472 # Number of bytes of host memory used
host_seconds 18380.70 # Real time elapsed on the host
host_tick_rate 59216546 # Simulator tick rate (ticks/s)
host_inst_rate 138841 # Simulator instruction rate (inst/s)
host_mem_usage 198176 # Number of bytes of host memory used
host_seconds 10123.96 # Real time elapsed on the host
host_tick_rate 108192045 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618369 # Number of instructions simulated
sim_seconds 1.088442 # Number of seconds simulated
sim_ticks 1088441503500 # Number of ticks simulated
sim_insts 1405618374 # Number of instructions simulated
sim_seconds 1.095331 # Number of seconds simulated
sim_ticks 1095331467500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 175591574 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 198504175 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 83489596 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 252577407 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 252577407 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 9068364 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1951658061 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.763216 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.203742 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 1072656731 55.24% 55.24% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 568585470 29.28% 84.51% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 11084197 0.57% 99.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 4503092 0.23% 99.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 8072747 0.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 1079992719 55.34% 55.34% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 573544089 29.39% 84.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 118996755 6.10% 90.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 118578034 6.08% 96.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 27958213 1.43% 98.33% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 7829070 0.40% 98.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 11095017 0.57% 99.30% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 4595800 0.24% 99.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 9068364 0.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489537512 # Number of instructions committed
system.cpu.commit.COM:loads 402517247 # Number of loads committed
system.cpu.commit.COM:committed_per_cycle::total 1951658061 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489537517 # Number of instructions committed
system.cpu.commit.COM:loads 402517252 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569375203 # Number of memory references committed
system.cpu.commit.COM:refs 569375208 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions
system.cpu.commit.branchMispredicts 83489596 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489537517 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405618369 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated
system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 421715823 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6923.398779 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 420813257 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12864854000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002140 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 902566 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 664404 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1648890500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses
system.cpu.commit.commitSquashedInsts 1344365389 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405618374 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405618374 # Number of Instructions Simulated
system.cpu.cpi 1.558505 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.558505 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 428071377 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6644.344451 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 427202678 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12103469000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002029 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 868699 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 619015 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1658986500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 249684 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 684500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164663038 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 80123447685 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.013147 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2193592 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1850133 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 12044158308 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002058 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 343459 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 165064790 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 25958081664 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010739 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1791840 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1512123 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 3237699799 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001676 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 279717 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 1118.737886 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30033.448450 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 92988301685 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005260 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3096158 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2514537 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 13693048808 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000988 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 581621 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 594928007 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14305.954795 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
system.cpu.dcache.demand_hits 592267468 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 38061550664 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.004472 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2660539 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2131138 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4896686299 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000890 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 529401 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 588572453 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30033.448450 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.577700 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 594928007 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14305.954795 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 585476295 # number of overall hits
system.cpu.dcache.overall_miss_latency 92988301685 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005260 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3096158 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2514537 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 13693048808 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000988 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 581621 # number of overall MSHR misses
system.cpu.dcache.overall_hits 592267468 # number of overall hits
system.cpu.dcache.overall_miss_latency 38061550664 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.004472 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2660539 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2131138 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4896686299 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000890 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 529401 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 509328 # number of replacements
system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 525312 # number of replacements
system.cpu.dcache.sampled_refs 529408 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use
system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 343309 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched
system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total)
system.cpu.dcache.tagsinuse 4095.577700 # Cycle average of tags in use
system.cpu.dcache.total_refs 592268787 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 165936000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 467492 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 419165001 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3408944329 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 761736999 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 767859019 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 238675861 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2897042 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 252577407 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355041427 # Number of cache lines fetched
system.cpu.fetch.Cycles 1184621367 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 11557522 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3696750718 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 90055290 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.115297 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355041427 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 175591574 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.687503 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 2190333922 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.687757 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.837142 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1360754025 62.13% 62.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 248782776 11.36% 73.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 79015111 3.61% 77.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 36736924 1.68% 78.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 85275355 3.89% 82.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 39319900 1.80% 84.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 30979848 1.41% 85.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 19612924 0.90% 86.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 289857059 13.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 2190333922 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 355041427 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 33183.081998 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355039305 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 70414500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 740 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 48047500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 2122 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 746 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 47881500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 1376 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 258210.403636 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 70574500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 355041427 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 33183.081998 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency
system.cpu.icache.demand_hits 355039305 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 70414500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_misses 2121 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 740 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 48047500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 2122 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 746 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 47881500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 1376 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.517204 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1059.233334 # Average occupied blocks per context
system.cpu.icache.overall_accesses 350205998 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33274.163131 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.517160 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1059.143452 # Average occupied blocks per context
system.cpu.icache.overall_accesses 355041427 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33183.081998 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 350203877 # number of overall hits
system.cpu.icache.overall_miss_latency 70574500 # number of overall miss cycles
system.cpu.icache.overall_hits 355039305 # number of overall hits
system.cpu.icache.overall_miss_latency 70414500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_misses 2121 # number of overall misses
system.cpu.icache.overall_mshr_hits 740 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 48047500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 2122 # number of overall misses
system.cpu.icache.overall_mshr_hits 746 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 47881500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 1376 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 223 # number of replacements
system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks.
system.cpu.icache.replacements 218 # number of replacements
system.cpu.icache.sampled_refs 1375 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1059.233334 # Cycle average of tags in use
system.cpu.icache.total_refs 350203877 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1059.143452 # Cycle average of tags in use
system.cpu.icache.total_refs 355039305 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1347738 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 126526916 # Number of branches executed
system.cpu.iew.EXEC:nop 340982559 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.865733 # Inst execution rate
system.cpu.iew.EXEC:refs 746184493 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 208199925 # Number of stores executed
system.cpu.idleCycles 329014 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 129329311 # Number of branches executed
system.cpu.iew.EXEC:nop 343977069 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.860181 # Inst execution rate
system.cpu.iew.EXEC:refs 750434371 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 206174463 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1479878942 # num instructions consuming a value
system.cpu.iew.WB:count 1850747692 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.963175 # average fanout of values written-back
system.cpu.iew.WB:consumers 1480496045 # num instructions consuming a value
system.cpu.iew.WB:count 1847584929 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.961963 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1425382580 # num instructions producing a value
system.cpu.iew.WB:rate 0.850182 # insts written-back per cycle
system.cpu.iew.WB:sent 1860799390 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 88298258 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3065589 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 732363888 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21345183 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 16501703 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 296834010 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2838380214 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 537984568 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 98702938 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1884599663 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 42681 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1424182878 # num instructions producing a value
system.cpu.iew.WB:rate 0.843391 # insts written-back per cycle
system.cpu.iew.WB:sent 1859595547 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 91828645 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2291655 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 731683017 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21329829 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 16631995 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 299730608 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2833977471 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 544259908 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 92682608 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1884367319 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 43246 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 10075 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 233579864 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 76418 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 5071 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 238675861 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 70086 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 3315 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 116246268 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 24120 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 28836 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 116166112 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 85848 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 6177679 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 329846641 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 129976054 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 6177679 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2822462 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 85475796 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.645702 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.645702 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 6831445 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 329165765 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 132872652 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 6831445 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2781524 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 89047121 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.641641 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.641641 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178510091 59.42% 59.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2995561 0.15% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 574193114 28.95% 88.52% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 227603835 11.48% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1175590605 59.46% 59.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2994259 0.15% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 570634170 28.86% 88.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 227830893 11.52% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1983302601 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 6030045 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.003040 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 1977049927 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4131140 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002090 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 148667 2.47% 2.47% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.47% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 233339 3.87% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5333431 88.45% 94.78% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 314608 5.22% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 148870 3.60% 3.60% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.60% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.60% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 222262 5.38% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3423281 82.87% 91.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 336727 8.15% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 2175535270 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.911639 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.163576 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 2190333922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902625 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.145189 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 1067990413 49.09% 49.09% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 580044793 26.66% 75.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 292279315 13.43% 89.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 158370905 7.28% 96.47% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 51349615 2.36% 98.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 15864540 0.73% 99.56% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 8721161 0.40% 99.96% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 777887 0.04% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 136641 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 1077130624 49.18% 49.18% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 581443700 26.55% 75.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 301967857 13.79% 89.51% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 159877963 7.30% 96.81% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 45264546 2.07% 98.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 18451049 0.84% 99.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 4794612 0.22% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1273045 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 130526 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 2175535270 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.911075 # Inst issue rate
system.cpu.iq.iqInstsAdded 2475761446 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1983302601 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21636209 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1050320205 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 3387342 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19392538 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1256970263 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 275262 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 11754 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 9040806000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.957299 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 263508 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8213610000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits
system.cpu.iq.ISSUE:issued_per_cycle::total 2190333922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.902489 # Inst issue rate
system.cpu.iq.iqInstsAdded 2468355699 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1977049927 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21644703 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1031033219 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 637277 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19401032 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1242826340 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 279724 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 218618 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2110047500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.218451 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 61106 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1917896000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.218451 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 61106 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 251060 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 217208 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1153541000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.134836 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33852 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1049484000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.134836 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33852 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 467492 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 467492 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.866131 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 530784 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34368.757767 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 435826 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3263588500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.178901 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 94958 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2967380000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.178901 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 94958 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.061469 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.477467 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2014.215255 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15645.646003 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 530784 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34368.757767 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 216644 # number of overall hits
system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 298161 # number of overall misses
system.cpu.l2cache.overall_hits 435826 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3263588500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.178901 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 94958 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2967380000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.178901 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 94958 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 83969 # number of replacements
system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 76745 # number of replacements
system.cpu.l2cache.sampled_refs 92262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use
system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17659.861257 # Cycle average of tags in use
system.cpu.l2cache.total_refs 541221 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61561 # number of writebacks
system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 2176883008 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed
system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.l2cache.writebacks 59365 # number of writebacks
system.cpu.memDep0.conflictingLoads 443698156 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 136383139 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 731683017 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 299730608 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 2190662936 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 17189054 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244779268 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 463 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 34257 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 824291881 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 24214806 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 4869886562 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3060544953 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2396042530 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 704670101 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 238675861 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 33809858 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1151263262 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 371697167 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21697179 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 175779479 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21533408 # count of temporary serializing insts renamed
system.cpu.timesIdled 8581 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:04:04
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:28:00
M5 executing on phenom
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -45,4 +43,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2075400743000 because target called exit()
Exiting @ tick 2064258667000 because target called exit()

195
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1385286 # Simulator instruction rate (inst/s)
host_mem_usage 211532 # Number of bytes of host memory used
host_seconds 1075.25 # Real time elapsed on the host
host_tick_rate 1930162951 # Simulator tick rate (ticks/s)
host_inst_rate 1333935 # Simulator instruction rate (inst/s)
host_mem_usage 197236 # Number of bytes of host memory used
host_seconds 1116.64 # Real time elapsed on the host
host_tick_rate 1848636408 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.075401 # Number of seconds simulated
sim_ticks 2075400743000 # Number of ticks simulated
sim_seconds 2.064259 # Number of seconds simulated
sim_ticks 2064258667000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses
system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568847975 # number of overall hits
system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses
system.cpu.dcache.overall_misses 511685 # number of overall misses
system.cpu.dcache.overall_hits 568906446 # number of overall hits
system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_misses 453214 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316439 # number of writebacks
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 407009 # number of writebacks
system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use
system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -142,37 +142,28 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1737320000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 173281 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 14614444000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 11241880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.618599 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 281047 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052996 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1736.572582 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14664.762880 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 173281 # number of overall hits
system.cpu.l2cache.overall_miss_latency 14614444000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.618599 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 281047 # number of overall misses
system.cpu.l2cache.overall_hits 361985 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 92343 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 11241880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.618599 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 281047 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 82461 # number of replacements
system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 74112 # number of replacements
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use
system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61551 # number of writebacks
system.cpu.l2cache.writebacks 59035 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4150801486 # number of cpu cycles simulated
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.num_insts 1489523295 # Number of instructions executed
system.cpu.num_refs 569365767 # Number of memory references
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls

2
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864

12
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:20:12
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:33:02
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:29:10
M5 executing on phenom
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -46,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1814105620000 because target called exit()
Exiting @ tick 1803258587000 because target called exit()

179
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1308474 # Simulator instruction rate (inst/s)
host_mem_usage 210192 # Number of bytes of host memory used
host_seconds 1237.60 # Real time elapsed on the host
host_tick_rate 1465826235 # Simulator tick rate (ticks/s)
host_inst_rate 1292356 # Simulator instruction rate (inst/s)
host_mem_usage 195556 # Number of bytes of host memory used
host_seconds 1253.03 # Real time elapsed on the host
host_tick_rate 1439113315 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619366787 # Number of instructions simulated
sim_seconds 1.814106 # Number of seconds simulated
sim_ticks 1814105620000 # Number of ticks simulated
sim_seconds 1.803259 # Number of seconds simulated
sim_ticks 1803258587000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses
system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 606722925 # number of overall hits
system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses
system.cpu.dcache.overall_misses 505257 # number of overall misses
system.cpu.dcache.overall_hits 606786134 # number of overall hits
system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
system.cpu.dcache.overall_misses 442048 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 306200 # number of writebacks
system.cpu.dcache.writebacks 396372 # number of writebacks
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use
system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -132,37 +132,28 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 177813 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 264957 # number of overall misses
system.cpu.l2cache.overall_hits 353302 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 89468 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 81078 # number of replacements
system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 71208 # number of replacements
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use
system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61253 # number of writebacks
system.cpu.l2cache.writebacks 58007 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3628211240 # number of cpu cycles simulated
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.num_insts 1619366787 # Number of instructions executed
system.cpu.num_refs 607228182 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/home/stever/m5/m5_system_2.0b3/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -661,7 +661,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@ -681,7 +681,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -807,7 +807,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]

16
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,14 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 12:51:14
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:51:16
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:17:04
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 125480500
Exiting @ tick 1906675009500 because m5_exit instruction encountered
info: Launching CPU 1 @ 118370500
Exiting @ tick 1900828642500 because m5_exit instruction encountered

2000
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/home/stever/m5/m5_system_2.0b3/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -356,7 +356,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@ -376,7 +376,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -502,7 +502,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]

14
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 12:51:14
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:51:33
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:17:56
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1865288389500 because m5_exit instruction encountered
Exiting @ tick 1865720303500 because m5_exit instruction encountered

996
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 14:11:34
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:14:22
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 152155526000 because target called exit()
Exiting @ tick 148086219000 because target called exit()

205
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1008175 # Simulator instruction rate (inst/s)
host_mem_usage 344580 # Number of bytes of host memory used
host_seconds 90.44 # Real time elapsed on the host
host_tick_rate 1682447495 # Simulator tick rate (ticks/s)
host_inst_rate 1157512 # Simulator instruction rate (inst/s)
host_mem_usage 330420 # Number of bytes of host memory used
host_seconds 78.77 # Real time elapsed on the host
host_tick_rate 1880000368 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91176087 # Number of instructions simulated
sim_seconds 0.152156 # Number of seconds simulated
sim_ticks 152155526000 # Number of ticks simulated
sim_seconds 0.148086 # Number of seconds simulated
sim_ticks 148086219000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 14013.157105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 21664622 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12615288000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 12614616000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.039894 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 900198 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 9914694000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 9914022000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55998.688893 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.688893 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4642766 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5381586000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.020280 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 96102 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5093280000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.020280 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 96102 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 4692259 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009835 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009835 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18063.709726 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26307388 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 17996874000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.036490 # miss rate for demand accesses
system.cpu.dcache.demand_misses 996300 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 14657.853184 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11657.853184 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26356881 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 13878158000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.034677 # miss rate for demand accesses
system.cpu.dcache.demand_misses 946807 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 15007974000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.036490 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 996300 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 11037737000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.034677 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 946807 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.874745 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3582.956819 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.871309 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3568.882850 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18063.709726 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 14657.853184 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.853184 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26307388 # number of overall hits
system.cpu.dcache.overall_miss_latency 17996874000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.036490 # miss rate for overall accesses
system.cpu.dcache.overall_misses 996300 # number of overall misses
system.cpu.dcache.overall_hits 26356881 # number of overall hits
system.cpu.dcache.overall_miss_latency 13878158000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.034677 # miss rate for overall accesses
system.cpu.dcache.overall_misses 946807 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 15007974000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.036490 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 996300 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 11037737000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.034677 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 946807 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 942711 # number of replacements
system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3582.956819 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3568.882850 # Cycle average of tags in use
system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54487870000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 96132 # number of writebacks
system.cpu.dcache.warmup_cycle 54482100000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 942313 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 107819118 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 54667.779633 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51667.779633 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 107818519 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 32746000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 30949000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 107819118 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 54667.779633 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
system.cpu.icache.demand_hits 107818519 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 32746000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 30949000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.249735 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 511.457636 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.249185 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 510.330850 # Average occupied blocks per context
system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 107818519 # number of overall hits
system.cpu.icache.overall_miss_latency 32746000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_misses 599 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 30949000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 511.457636 # Cycle average of tags in use
system.cpu.icache.tagsinuse 510.330850 # Cycle average of tags in use
system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2423512000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 46606 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 46606 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 899919 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 45656000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.000975 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 878 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 49493 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2573636000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 49493 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1979720000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 49493 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 96132 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 96132 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 899937 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 942313 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 942313 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 52.533433 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 103.596349 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 899922 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2469168000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.050120 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 47484 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 931998 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016263 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1899360000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.050120 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 47484 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016263 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.009784 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.265384 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 320.609441 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8696.109935 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.271910 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 325.103802 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8909.939708 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 899922 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2469168000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.050120 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 47484 # number of overall misses
system.cpu.l2cache.overall_hits 931998 # number of overall hits
system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016263 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15408 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1899360000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.050120 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 47484 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016263 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 678 # number of replacements
system.cpu.l2cache.sampled_refs 15344 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 634 # number of replacements
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 9016.719375 # Cycle average of tags in use
system.cpu.l2cache.total_refs 806073 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 9235.043509 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1594555 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 35 # number of writebacks
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 304311052 # number of cpu cycles simulated
system.cpu.numCycles 296172438 # number of cpu cycles simulated
system.cpu.num_insts 91176087 # Number of instructions executed
system.cpu.num_refs 27330336 # Number of memory references
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls

4
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:06:13
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:31:43
M5 executing on phenom
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 366433850000 because target called exit()
Exiting @ tick 362430887000 because target called exit()

223
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 994564 # Simulator instruction rate (inst/s)
host_mem_usage 343716 # Number of bytes of host memory used
host_seconds 245.17 # Real time elapsed on the host
host_tick_rate 1494621764 # Simulator tick rate (ticks/s)
host_inst_rate 1229097 # Simulator instruction rate (inst/s)
host_mem_usage 329428 # Number of bytes of host memory used
host_seconds 198.39 # Real time elapsed on the host
host_tick_rate 1826897848 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366434 # Number of seconds simulated
sim_ticks 366433850000 # Number of ticks simulated
sim_seconds 0.362431 # Number of seconds simulated
sim_ticks 362430887000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55998.672804 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.672804 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22807014 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5316346000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004145 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 94937 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5031535000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004145 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 94937 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18045.256400 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104134591 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 17824996000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
system.cpu.dcache.demand_misses 987794 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 14861614000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 987794 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.871491 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3569.628477 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18045.256400 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 104134591 # number of overall hits
system.cpu.dcache.overall_miss_latency 17824996000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
system.cpu.dcache.overall_misses 987794 # number of overall misses
system.cpu.dcache.overall_hits 104182818 # number of overall hits
system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_misses 939567 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 14861614000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 987794 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3569.628477 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134378918000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94947 # number of writebacks
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 935237 # number of writebacks
system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 726.243472 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.354281 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 244420630 # number of overall hits
system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 882 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 726.243472 # Cycle average of tags in use
system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -142,37 +142,28 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2428972000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 46711 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868440000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 46711 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 48231 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2508012000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 48231 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1929240000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 48231 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 94947 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 94947 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 51.538160 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 892656 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2485444000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.050823 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 47797 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1911880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.050823 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 47797 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.011380 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.262199 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 372.883816 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8591.744977 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.011460 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.270424 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 892656 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2485444000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.050823 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 47797 # number of overall misses
system.cpu.l2cache.overall_hits 924805 # number of overall hits
system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15648 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1911880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.050823 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 47797 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 891 # number of replacements
system.cpu.l2cache.sampled_refs 15566 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 865 # number of replacements
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8964.628794 # Cycle average of tags in use
system.cpu.l2cache.total_refs 802243 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 41 # number of writebacks
system.cpu.l2cache.writebacks 40 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 732867700 # number of cpu cycles simulated
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.num_insts 243835278 # Number of instructions executed
system.cpu.num_refs 105711442 # Number of memory references
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls

4
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:20:12
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:47:25
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:29:54
M5 executing on phenom
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 378879619000 because target called exit()
Exiting @ tick 370010840000 because target called exit()

187
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1022159 # Simulator instruction rate (inst/s)
host_mem_usage 344728 # Number of bytes of host memory used
host_seconds 263.85 # Real time elapsed on the host
host_tick_rate 1435967954 # Simulator tick rate (ticks/s)
host_inst_rate 1130440 # Simulator instruction rate (inst/s)
host_mem_usage 330088 # Number of bytes of host memory used
host_seconds 238.58 # Real time elapsed on the host
host_tick_rate 1550911771 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269696010 # Number of instructions simulated
sim_seconds 0.378880 # Number of seconds simulated
sim_ticks 378879619000 # Number of ticks simulated
sim_seconds 0.370011 # Number of seconds simulated
sim_ticks 370010840000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15327.890775 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12327.890775 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 30053702000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 24171542000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55478.946733 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52478.946733 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 31241017 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 11025553000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006321 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 198734 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 10429351000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006321 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 198734 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19022.982198 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency
system.cpu.dcache.demand_hits 120059747 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 41079255000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.017669 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2159454 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 34600893000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.017669 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2159454 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995362 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.003489 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19022.982198 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 120059747 # number of overall hits
system.cpu.dcache.overall_miss_latency 41079255000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.017669 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2159454 # number of overall misses
system.cpu.dcache.overall_hits 120152372 # number of overall hits
system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2066829 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 34600893000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.017669 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2159454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4077.003489 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 127444032000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 283281 # number of writebacks
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1437080 # number of writebacks
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.325684 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 667.001102 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -124,91 +124,82 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 667.001102 # Cycle average of tags in use
system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.299104 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 2466 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 5389467000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.976760 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 103643 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4145720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.976760 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 103643 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1898729 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3265548000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.032015 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 62799 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2511960000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.032015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 62799 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 92625 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.385965 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 4815980000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 92625 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3705000000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 92625 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 283281 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 283281 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 19.797170 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000.186251 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1901195 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 8655015000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.080499 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 166442 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 6657680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.080499 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 166442 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.204822 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.350671 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6711.601001 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11490.800356 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.186251 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1901195 # number of overall hits
system.cpu.l2cache.overall_miss_latency 8655015000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.080499 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 166442 # number of overall misses
system.cpu.l2cache.overall_hits 1991062 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 76575 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 6657680000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.080499 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 166442 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 81066 # number of replacements
system.cpu.l2cache.sampled_refs 106133 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 49212 # number of replacements
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18202.401357 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2101133 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 48460 # number of writebacks
system.cpu.l2cache.writebacks 29460 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 757759238 # number of cpu cycles simulated
system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.num_insts 269696010 # Number of instructions executed
system.cpu.num_refs 122219139 # Number of memory references
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls

4
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:57:01
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:07:44
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -74,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 745672616000 because target called exit()
Exiting @ tick 719872424000 because target called exit()

181
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1125820 # Simulator instruction rate (inst/s)
host_mem_usage 214880 # Number of bytes of host memory used
host_seconds 496.95 # Real time elapsed on the host
host_tick_rate 1500512692 # Simulator tick rate (ticks/s)
host_inst_rate 1404297 # Simulator instruction rate (inst/s)
host_mem_usage 200728 # Number of bytes of host memory used
host_seconds 398.40 # Real time elapsed on the host
host_tick_rate 1806912378 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 559470527 # Number of instructions simulated
sim_seconds 0.745673 # Number of seconds simulated
sim_ticks 745672616000 # Number of ticks simulated
sim_seconds 0.719872 # Number of seconds simulated
sim_ticks 719872424000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 16376290000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 15508654000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14027302000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 13159666000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 55072849 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 35260840000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011754 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 654998 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 33295846000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 654998 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 55371547 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10029586000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006394 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 356300 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 8960686000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006394 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 356300 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35909.141485 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
system.cpu.dcache.demand_hits 181616179 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 51637130000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.007856 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1437994 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 22415.807657 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency
system.cpu.dcache.demand_hits 181914877 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 25538240000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006224 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1139296 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 47323148000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.007856 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1437994 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 22120352000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006224 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1139296 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.992972 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4067.215006 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.992721 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4066.183353 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35909.141485 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 22415.807657 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 181616179 # number of overall hits
system.cpu.dcache.overall_miss_latency 51637130000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.007856 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1437994 # number of overall misses
system.cpu.dcache.overall_hits 181914877 # number of overall hits
system.cpu.dcache.overall_miss_latency 25538240000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006224 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1139296 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 47323148000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.007856 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1437994 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 22120352000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006224 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1139296 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1135200 # number of replacements
system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4067.215006 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4066.183353 # Cycle average of tags in use
system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 808512 # number of writebacks
system.cpu.dcache.writebacks 1025629 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 11521 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.485313 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 993.921198 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.482234 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 987.615046 # Average occupied blocks per context
system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 9788 # number of replacements
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 993.921198 # Cycle average of tags in use
system.cpu.icache.tagsinuse 987.615046 # Cycle average of tags in use
system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 33786 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 16770728000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.905175 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 322514 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 12900560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.905175 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 322514 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 236267 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 6241716000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.336887 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 120033 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336887 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 120033 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 662657 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 6856720000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165962 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 131860 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 5274400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165962 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 131860 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 298698 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 15530424000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 298698 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11947920000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 298698 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 808512 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 808512 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 683315 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 5782504000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.139962 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 111202 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4448080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139962 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 111202 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1025629 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1025629 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.737661 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 6.147006 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 696443 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 23627448000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.394827 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 454374 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 919582 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 12024220000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.200931 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 231235 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 18174960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.394827 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 454374 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 9249400000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.200931 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 231235 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.184240 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.380639 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6037.178832 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12472.788257 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.178887 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.445562 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 5861.784368 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14600.161549 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 696443 # number of overall hits
system.cpu.l2cache.overall_miss_latency 23627448000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.394827 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 454374 # number of overall misses
system.cpu.l2cache.overall_hits 919582 # number of overall hits
system.cpu.l2cache.overall_miss_latency 12024220000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.200931 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 231235 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 18174960000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.394827 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 454374 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 9249400000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.200931 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 231235 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 232496 # number of replacements
system.cpu.l2cache.sampled_refs 251560 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 212119 # number of replacements
system.cpu.l2cache.sampled_refs 232160 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18509.967089 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1191806 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 525324932000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 186433 # number of writebacks
system.cpu.l2cache.tagsinuse 20461.945917 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1427089 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 510281834000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 172310 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1491345232 # number of cpu cycles simulated
system.cpu.numCycles 1439744848 # number of cpu cycles simulated
system.cpu.num_insts 559470527 # Number of instructions executed
system.cpu.num_refs 184987503 # Number of memory references
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls

4
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:20:12
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:22:00
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:23:05
M5 executing on phenom
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -76,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1701783891000 because target called exit()
Exiting @ tick 1658729604000 because target called exit()

211
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1040513 # Simulator instruction rate (inst/s)
host_mem_usage 213908 # Number of bytes of host memory used
host_seconds 1437.46 # Real time elapsed on the host
host_tick_rate 1183878785 # Simulator tick rate (ticks/s)
host_inst_rate 1334580 # Simulator instruction rate (inst/s)
host_mem_usage 199248 # Number of bytes of host memory used
host_seconds 1120.73 # Real time elapsed on the host
host_tick_rate 1480046497 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495700521 # Number of instructions simulated
sim_seconds 1.701784 # Number of seconds simulated
sim_ticks 1701783891000 # Number of ticks simulated
sim_seconds 1.658730 # Number of seconds simulated
sim_ticks 1658729604000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 22845.361911 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19845.360753 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 39463398000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 34281154000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 53546.298194 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50546.298194 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 147974496 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 63490113500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.007949 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1185705 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 59932998500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007949 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1185705 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
@ -37,50 +37,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35341.333979 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency
system.cpu.dcache.demand_hits 530349271 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 102953511500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005463 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2913119 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 94214152500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005463 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2913119 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997733 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4086.713108 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.997674 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35341.333979 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 530349271 # number of overall hits
system.cpu.dcache.overall_miss_latency 102953511500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005463 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2913119 # number of overall misses
system.cpu.dcache.overall_hits 530743932 # number of overall hits
system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2518458 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 94214152500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005463 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2913119 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4086.713108 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1528950 # number of writebacks
system.cpu.dcache.writebacks 2223170 # number of writebacks
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 128394000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -92,31 +92,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 128394000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.433486 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 887.780127 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.430777 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1068344296 # number of overall hits
system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_misses 2814 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 128394000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -124,91 +124,82 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 887.780127 # Cycle average of tags in use
system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.015933 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 69270 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 37532259500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.912432 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 721774 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28870960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.912432 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 721774 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1364108 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 19038240000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.211602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 366120 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 14644800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.211602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 366120 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 394661 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.993171 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 20520396000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 394661 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 15786440000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 394661 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1528950 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1528950 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.977137 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000.010571 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1433378 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 56570499500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.431486 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1087894 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 43515760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.431486 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1087894 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.230883 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.374106 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7565.560471 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12258.710159 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.230381 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.417452 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.010571 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1433378 # number of overall hits
system.cpu.l2cache.overall_miss_latency 56570499500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.431486 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1087894 # number of overall misses
system.cpu.l2cache.overall_hits 1941663 # number of overall hits
system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 579609 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 43515760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.431486 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1087894 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 603454 # number of replacements
system.cpu.l2cache.sampled_refs 621473 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 568906 # number of replacements
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 19824.270630 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2471683 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 910963647000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 436481 # number of writebacks
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 411709 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 3403567782 # number of cpu cycles simulated
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
system.cpu.num_insts 1495700521 # Number of instructions executed
system.cpu.num_refs 533262345 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls

2
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

12
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -18,4 +16,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 136571603500 because target called exit()
Exiting @ tick 134780256500 because target called exit()

627
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,339 +1,339 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 136199 # Simulator instruction rate (inst/s)
host_mem_usage 214028 # Number of bytes of host memory used
host_seconds 2757.55 # Real time elapsed on the host
host_tick_rate 49526494 # Simulator tick rate (ticks/s)
host_inst_rate 209084 # Simulator instruction rate (inst/s)
host_mem_usage 200220 # Number of bytes of host memory used
host_seconds 1796.28 # Real time elapsed on the host
host_tick_rate 75032789 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.136572 # Number of seconds simulated
sim_ticks 136571603500 # Number of ticks simulated
sim_seconds 0.134780 # Number of seconds simulated
sim_ticks 134780256500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 34712245 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 43971564 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1375 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5750083 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 35466067 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 62830534 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 12729193 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 34013245 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 43763729 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1420 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5537198 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 35178330 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 62077463 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 12488414 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 44587532 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 12727499 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 13095097 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 257005436 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.551191 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.213326 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 254238271 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.568075 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.238705 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 123174402 47.93% 47.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 51601116 20.08% 68.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 20452287 7.96% 75.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 20740884 8.07% 84.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 11122877 4.33% 88.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8764041 3.41% 91.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5151763 2.00% 93.78% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 3270567 1.27% 95.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 12727499 4.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 122261214 48.09% 48.09% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 50419868 19.83% 67.92% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 19851999 7.81% 75.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 19999442 7.87% 83.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 10886968 4.28% 87.88% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 9291241 3.65% 91.53% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5249545 2.06% 93.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 3182897 1.25% 94.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 13095097 5.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 257005436 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 254238271 # Number of insts commited each cycle
system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:loads 100651995 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5745758 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 5532855 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 99827575 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 94873241 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
system.cpu.cpi 0.727267 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.727267 # CPI: Total CPI of All Threads
system.cpu.cpi 0.717728 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.717728 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 95959241 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33093.582888 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31984.199796 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 95957558 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 55696500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 702 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31376500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_accesses 95565604 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33374.015748 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31987.257900 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 95563953 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 55100500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1651 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 670 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31379500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30331.836439 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36071.185392 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73502803 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 543728500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000244 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 17926 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 14695 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 116546000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3231 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 30116.133558 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35471.048513 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73502909 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 536669500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 17820 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 14625 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 113330000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40579.607280 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40485.360393 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 169479970 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30568.871437 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169460361 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 599425000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000116 # miss rate for demand accesses
system.cpu.dcache.demand_misses 19609 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 15397 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 147922500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_accesses 169086333 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30392.378409 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169066862 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 591770000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000115 # miss rate for demand accesses
system.cpu.dcache.demand_misses 19471 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 15295 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 144709500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4212 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.804256 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3294.233360 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169479970 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30568.871437 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.804225 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3294.106020 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169086333 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30392.378409 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 169460361 # number of overall hits
system.cpu.dcache.overall_miss_latency 599425000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000116 # miss rate for overall accesses
system.cpu.dcache.overall_misses 19609 # number of overall misses
system.cpu.dcache.overall_mshr_hits 15397 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 147922500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_hits 169066862 # number of overall hits
system.cpu.dcache.overall_miss_latency 591770000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000115 # miss rate for overall accesses
system.cpu.dcache.overall_misses 19471 # number of overall misses
system.cpu.dcache.overall_mshr_hits 15295 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 144709500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4212 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 781 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3294.233360 # Cycle average of tags in use
system.cpu.dcache.total_refs 169460440 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3294.106020 # Cycle average of tags in use
system.cpu.dcache.total_refs 169066865 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 638 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 21059081 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4405 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11508131 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 539100093 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 134649980 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 100169012 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15996729 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 13181 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1127363 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 185557278 # DTB accesses
system.cpu.dcache.writebacks 662 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 22152007 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4419 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11286796 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 532040738 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 132274950 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 98625859 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15181213 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 13245 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1185455 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 184734537 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 185509117 # DTB hits
system.cpu.dtb.data_misses 48161 # DTB misses
system.cpu.dtb.data_hits 184683089 # DTB hits
system.cpu.dtb.data_misses 51448 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 105313060 # DTB read accesses
system.cpu.dtb.read_accesses 104442295 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 105266355 # DTB read hits
system.cpu.dtb.read_misses 46705 # DTB read misses
system.cpu.dtb.write_accesses 80244218 # DTB write accesses
system.cpu.dtb.read_hits 104392308 # DTB read hits
system.cpu.dtb.read_misses 49987 # DTB read misses
system.cpu.dtb.write_accesses 80292242 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 80242762 # DTB write hits
system.cpu.dtb.write_misses 1456 # DTB write misses
system.cpu.fetch.Branches 62830534 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 64860863 # Number of cache lines fetched
system.cpu.fetch.Cycles 168703371 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1410406 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 552550587 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6169479 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.230028 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 64860863 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 47441438 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.022934 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 273002165 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.023979 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.024544 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 80290781 # DTB write hits
system.cpu.dtb.write_misses 1461 # DTB write misses
system.cpu.fetch.Branches 62077463 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 63755206 # Number of cache lines fetched
system.cpu.fetch.Cycles 165857748 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1527822 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 544006695 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 5884776 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.230291 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 63755206 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 46501659 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.018125 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 269419484 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.019181 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.021968 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 169159964 61.96% 61.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10172385 3.73% 65.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10846224 3.97% 69.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 7014396 2.57% 72.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 14631841 5.36% 77.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9961062 3.65% 81.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7189550 2.63% 83.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4041352 1.48% 85.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39985391 14.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 167317249 62.10% 62.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9830332 3.65% 65.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10264297 3.81% 69.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 7467850 2.77% 72.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 14528793 5.39% 77.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9632139 3.58% 81.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7095921 2.63% 83.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3870398 1.44% 85.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39412505 14.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 273002165 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 64860863 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32283.674736 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30878.201844 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 64856030 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 156027000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4833 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 929 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120548500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000060 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3904 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 269419484 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 63755206 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32282.788581 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30880.348450 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 63750372 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 156055000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4834 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 931 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120526000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3903 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 16612.712602 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 16333.684858 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 64860863 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32283.674736 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
system.cpu.icache.demand_hits 64856030 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 156027000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses
system.cpu.icache.demand_misses 4833 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 929 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120548500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000060 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3904 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 63755206 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32282.788581 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
system.cpu.icache.demand_hits 63750372 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 156055000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
system.cpu.icache.demand_misses 4834 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 931 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120526000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.891431 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1825.650576 # Average occupied blocks per context
system.cpu.icache.overall_accesses 64860863 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32283.674736 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.891530 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1825.852920 # Average occupied blocks per context
system.cpu.icache.overall_accesses 63755206 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32282.788581 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 64856030 # number of overall hits
system.cpu.icache.overall_miss_latency 156027000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses
system.cpu.icache.overall_misses 4833 # number of overall misses
system.cpu.icache.overall_mshr_hits 929 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120548500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000060 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3904 # number of overall MSHR misses
system.cpu.icache.overall_hits 63750372 # number of overall hits
system.cpu.icache.overall_miss_latency 156055000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
system.cpu.icache.overall_misses 4834 # number of overall misses
system.cpu.icache.overall_mshr_hits 931 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120526000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1982 # number of replacements
system.cpu.icache.sampled_refs 3904 # Sample count of references to valid blocks.
system.cpu.icache.replacements 1981 # number of replacements
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1825.650576 # Cycle average of tags in use
system.cpu.icache.total_refs 64856030 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1825.852920 # Cycle average of tags in use
system.cpu.icache.total_refs 63750372 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 141045 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 51385726 # Number of branches executed
system.cpu.iew.EXEC:nop 27755438 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.545021 # Inst execution rate
system.cpu.iew.EXEC:refs 192526473 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80254900 # Number of stores executed
system.cpu.idleCycles 141032 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 50928648 # Number of branches executed
system.cpu.iew.EXEC:nop 27198310 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.554098 # Inst execution rate
system.cpu.iew.EXEC:refs 191466035 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80302922 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 290066917 # num instructions consuming a value
system.cpu.iew.WB:count 417830932 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.699779 # average fanout of values written-back
system.cpu.iew.WB:consumers 288648946 # num instructions consuming a value
system.cpu.iew.WB:count 415155943 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.699341 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 202982772 # num instructions producing a value
system.cpu.iew.WB:rate 1.529714 # insts written-back per cycle
system.cpu.iew.WB:sent 418648136 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6175903 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3284723 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125889658 # Number of dispatched load instructions
system.cpu.iew.WB:producers 201863998 # num instructions producing a value
system.cpu.iew.WB:rate 1.540121 # insts written-back per cycle
system.cpu.iew.WB:sent 415846665 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6072161 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3214599 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125039862 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6874932 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 92903281 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 498492595 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 112271573 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 9215998 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 422011987 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 145222 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewDispSquashedInsts 6489838 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 92505583 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 493538259 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 111163113 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8697897 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 418923368 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 138014 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 28045 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15996729 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 550279 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 28455 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15181213 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 561595 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 9131244 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2248 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 8650010 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 47350 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 648565 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 175867 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 25237663 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 19371879 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 648565 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1211280 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4964623 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.375011 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.375011 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 540044 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 176691 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 24387867 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 18974181 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 540044 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1086448 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4985713 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.393286 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.393286 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 168382264 39.05% 39.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2152290 0.50% 39.55% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.55% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34830384 8.08% 47.63% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781044 1.80% 49.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2959993 0.69% 50.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16854742 3.91% 54.03% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1589897 0.37% 54.40% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.40% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 114726286 26.60% 81.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 81917504 19.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 166094034 38.84% 38.85% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2150895 0.50% 39.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34767843 8.13% 47.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7837636 1.83% 49.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2956341 0.69% 50.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16811834 3.93% 53.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571362 0.37% 54.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 113187864 26.47% 80.78% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82209875 19.22% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 431227985 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 9397735 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.021793 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 427621265 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 9425623 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022042 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 51470 0.55% 0.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 51324 0.55% 1.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 3037 0.03% 1.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 5843 0.06% 1.19% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 1281381 13.63% 14.82% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 969484 10.32% 25.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 25.14% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5699185 60.64% 85.78% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1336011 14.22% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 22465 0.24% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 44257 0.47% 0.71% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 507 0.01% 0.71% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 7079 0.08% 0.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 1310742 13.91% 14.69% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 1081807 11.48% 26.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5661778 60.07% 86.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1296988 13.76% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 273002165 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579577 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.704793 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 269419484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.587195 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.714658 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 100185843 36.70% 36.70% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 58377873 21.38% 58.08% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 43478311 15.93% 74.01% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 28530639 10.45% 84.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 23283249 8.53% 92.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 11208488 4.11% 97.09% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5200545 1.90% 99.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1974869 0.72% 99.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 762348 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 98807587 36.67% 36.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 58261038 21.62% 58.30% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 40917124 15.19% 73.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 29020181 10.77% 84.26% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 23205890 8.61% 92.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 11236315 4.17% 97.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5001720 1.86% 98.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2307051 0.86% 99.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 662578 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 273002165 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.578762 # Inst issue rate
system.cpu.iq.iqInstsAdded 470736916 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 431227985 # Number of instructions issued
system.cpu.iq.ISSUE:issued_per_cycle::total 269419484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.586365 # Inst issue rate
system.cpu.iq.iqInstsAdded 466339708 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 427621265 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 94399417 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 779543 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 89739850 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 704910 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 72495736 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 69710487 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 64861170 # ITB accesses
system.cpu.itb.fetch_accesses 63755513 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 64860863 # ITB hits
system.cpu.itb.fetch_hits 63755206 # ITB hits
system.cpu.itb.fetch_misses 307 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -344,106 +344,97 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.066333 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31448.372966 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 110511500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999062 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3196 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 100509000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999062 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3196 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4881 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34355.892097 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31170.255561 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34585.272553 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31456.646478 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 108494000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.980619 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98679500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980619 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4880 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.396450 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.467456 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 145188000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.865806 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4226 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 131725500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865806 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4226 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 36 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34236.111111 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1232500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 638 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 638 # number of Writeback hits
system.cpu.l2cache.ReadReq_miss_latency 145160000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.865779 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4225 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 131691000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865779 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4225 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.134782 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.152443 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8080 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34451.562921 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 658 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 255699500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.918564 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7422 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 8079 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34454.496061 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 253654000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.911251 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7362 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 232234500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.918564 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7422 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 230370500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.911251 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7362 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.108617 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011284 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3559.151087 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 369.756870 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8080 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34451.562921 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.108627 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011574 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3559.477751 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 379.255991 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8079 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34454.496061 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 658 # number of overall hits
system.cpu.l2cache.overall_miss_latency 255699500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.918564 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7422 # number of overall misses
system.cpu.l2cache.overall_hits 717 # number of overall hits
system.cpu.l2cache.overall_miss_latency 253654000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.911251 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7362 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 232234500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.918564 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7422 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 230370500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.911251 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7362 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 14 # number of replacements
system.cpu.l2cache.sampled_refs 4741 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.sampled_refs 4769 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3928.907957 # Cycle average of tags in use
system.cpu.l2cache.total_refs 639 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3938.733742 # Cycle average of tags in use
system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 73373175 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 55113413 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 125889658 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 92903281 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 273143210 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 10612512 # Number of cycles rename is blocking
system.cpu.memDep0.conflictingLoads 72822522 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 52763057 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 125039862 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 92505583 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 269560516 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 11010620 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2173514 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 139438532 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 7156113 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:IQFullEvents 2256823 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 137290050 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 7674469 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 690877715 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 524876259 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 339660686 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 96195896 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15996729 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 10389927 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 80128345 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368569 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37570 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 22417777 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 259 # count of temporary serializing insts renamed
system.cpu.timesIdled 3102 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:RenameLookups 683176131 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 518444566 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 335488186 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 94400681 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15181213 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11169785 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 75955845 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 367135 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37569 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 24308277 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 261 # count of temporary serializing insts renamed
system.cpu.timesIdled 3095 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

12
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:42:55
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -18,4 +16,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
Exiting @ tick 567347489000 because target called exit()
Exiting @ tick 567343170000 because target called exit()

139
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1188061 # Simulator instruction rate (inst/s)
host_mem_usage 213244 # Number of bytes of host memory used
host_seconds 335.56 # Real time elapsed on the host
host_tick_rate 1690751695 # Simulator tick rate (ticks/s)
host_inst_rate 1240949 # Simulator instruction rate (inst/s)
host_mem_usage 199424 # Number of bytes of host memory used
host_seconds 321.26 # Real time elapsed on the host
host_tick_rate 1766004728 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567347 # Number of seconds simulated
sim_ticks 567347489000 # Number of ticks simulated
sim_seconds 0.567343 # Number of seconds simulated
sim_ticks 567343170000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 #
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55961.075070 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52961.075070 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517493 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 181146000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3237 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 171435000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3237 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 54796.274182 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168271033 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 229432000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4187 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 216871000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3288.911680 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54796.274182 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 168271033 # number of overall hits
system.cpu.dcache.overall_miss_latency 229432000 # number of overall miss cycles
system.cpu.dcache.overall_hits 168271068 # number of overall hits
system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4187 # number of overall misses
system.cpu.dcache.overall_misses 4152 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 216871000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3288.911680 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.dcache.writebacks 649 # number of writebacks
system.cpu.dtb.data_accesses 168275276 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 168275220 # DTB hits
@ -122,7 +122,7 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1795.130856 # Average occupied blocks per context
system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1795.130856 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,13 +164,13 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 166348000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999063 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 127960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999063 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
@ -181,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses 4038 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 35 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1820000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1400000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.125220 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 588 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 376324000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.924856 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7237 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 289480000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.924856 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7237 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.103673 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011078 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3397.172145 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 362.997313 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.103674 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 588 # number of overall hits
system.cpu.l2cache.overall_miss_latency 376324000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.924856 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7237 # number of overall misses
system.cpu.l2cache.overall_hits 645 # number of overall hits
system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7180 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 289480000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.924856 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7237 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 14 # number of replacements
system.cpu.l2cache.sampled_refs 4544 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3760.169458 # Cycle average of tags in use
system.cpu.l2cache.total_refs 569 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1134694978 # number of cpu cycles simulated
system.cpu.numCycles 1134686340 # number of cpu cycles simulated
system.cpu.num_insts 398664609 # Number of instructions executed
system.cpu.num_refs 174183455 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls

2
tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

12
tests/long/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:52:33
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:12:46
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -20,4 +18,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.520000
Exiting @ tick 525827779000 because target called exit()
Exiting @ tick 525825884000 because target called exit()

135
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 898977 # Simulator instruction rate (inst/s)
host_mem_usage 219380 # Number of bytes of host memory used
host_seconds 383.10 # Real time elapsed on the host
host_tick_rate 1372552338 # Simulator tick rate (ticks/s)
host_inst_rate 1114146 # Simulator instruction rate (inst/s)
host_mem_usage 205224 # Number of bytes of host memory used
host_seconds 309.12 # Real time elapsed on the host
host_tick_rate 1701065680 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344399678 # Number of instructions simulated
sim_seconds 0.525828 # Number of seconds simulated
sim_ticks 525827779000 # Number of ticks simulated
sim_seconds 0.525826 # Number of seconds simulated
sim_ticks 525825884000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 75091000 #
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 82060677 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 162078000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 82060700 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2895 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 153393000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2895 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 53751.665926 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
system.cpu.dcache.demand_hits 176645795 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 241990000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 53599.464166 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency
system.cpu.dcache.demand_hits 176645818 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 240072000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4502 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 4479 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 228484000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 226635000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4502 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4479 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3079.430321 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 3079.431639 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 53751.665926 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 53599.464166 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 50599.464166 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 176645795 # number of overall hits
system.cpu.dcache.overall_miss_latency 241990000 # number of overall miss cycles
system.cpu.dcache.overall_hits 176645818 # number of overall hits
system.cpu.dcache.overall_miss_latency 240072000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4502 # number of overall misses
system.cpu.dcache.overall_misses 4479 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 228484000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 226635000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4502 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4479 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3079.430321 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3079.431639 # Cycle average of tags in use
system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 974 # number of writebacks
system.cpu.dcache.writebacks 998 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -115,7 +115,7 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1766.000778 # Average occupied blocks per context
system.cpu.icache.occ_blocks::0 1766.001397 # Average occupied blocks per context
system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1766.000778 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1766.001397 # Cycle average of tags in use
system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,13 +150,13 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 149292000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999652 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 2871 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114840000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999652 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 2871 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
@ -167,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses 3977 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1196000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 920000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits
system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.717391 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.725579 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 13234 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 356096000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.341002 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 6848 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 13249 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.340255 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 273920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.341002 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 6848 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.340255 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.010365 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3134.105136 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 339.639233 # Average occupied blocks per context
system.cpu.l2cache.occ_%::1 0.010426 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3134.106018 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 341.623002 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 13234 # number of overall hits
system.cpu.l2cache.overall_miss_latency 356096000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.341002 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 6848 # number of overall misses
system.cpu.l2cache.overall_hits 13249 # number of overall hits
system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.340255 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 6833 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 273920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.341002 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 6848 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.340255 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 48 # number of replacements
system.cpu.l2cache.sampled_refs 4876 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3473.744369 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13250 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3475.729020 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13309 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1051655558 # number of cpu cycles simulated
system.cpu.numCycles 1051651768 # number of cpu cycles simulated
system.cpu.num_insts 344399678 # Number of instructions executed
system.cpu.num_refs 177028576 # Number of memory references
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls

2
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

12
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:01:20
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:48:50
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 702688811500 because target called exit()
Exiting @ tick 702197148500 because target called exit()

620
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,295 +1,295 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 105247 # Simulator instruction rate (inst/s)
host_mem_usage 214344 # Number of bytes of host memory used
host_seconds 17321.56 # Real time elapsed on the host
host_tick_rate 40567294 # Simulator tick rate (ticks/s)
host_inst_rate 211797 # Simulator instruction rate (inst/s)
host_mem_usage 200548 # Number of bytes of host memory used
host_seconds 8607.50 # Real time elapsed on the host
host_tick_rate 81579716 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.702689 # Number of seconds simulated
sim_ticks 702688811500 # Number of ticks simulated
sim_seconds 0.702197 # Number of seconds simulated
sim_ticks 702197148500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 239396241 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 292393914 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 3599 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 28358143 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 232710596 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 347019771 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 49329086 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 239361289 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 292350506 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 817 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 28355767 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 232672074 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 346972918 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 49326443 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 266706457 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 67430429 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 67076252 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1305107182 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.539328 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.193562 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1304193061 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.540407 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.191824 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 596079504 45.67% 45.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 274005611 20.99% 66.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 176024939 13.49% 80.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 67867193 5.20% 85.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 46132467 3.53% 88.89% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 33942844 2.60% 91.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 19726349 1.51% 93.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 23897846 1.83% 94.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 67430429 5.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 594441372 45.58% 45.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 274309752 21.03% 66.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 176336103 13.52% 80.13% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 68165188 5.23% 85.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 46116026 3.54% 88.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 34003883 2.61% 91.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 19794848 1.52% 93.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 23949637 1.84% 94.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 67076252 5.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1305107182 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1304193061 # Number of insts commited each cycle
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
system.cpu.commit.COM:loads 511595302 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 722390433 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 28346322 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 28343948 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 694586134 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 694286197 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.770896 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.770896 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 463358852 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34710.185206 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 461425148 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 72449480000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004173 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1933704 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 474303 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 50656079000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1459401 # number of ReadReq MSHR misses
system.cpu.cpi 0.770357 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.770357 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 463422916 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37046.413098 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34119.469160 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 461494441 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 71443081500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004161 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1928475 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 469203 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 49789586000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1459272 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210236618 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 21543675991 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002648 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 558278 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 484005 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2712773000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000352 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 74273 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 37873.224315 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34361.981856 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210247567 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 20729113991 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 547329 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 475679 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2462036000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71650 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 438.700297 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 438.782653 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 674153748 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 37718.232311 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
system.cpu.dcache.demand_hits 671661766 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 93993155991 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003696 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2491982 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 958308 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 53368852000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002275 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1533674 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 674217812 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 37229.197259 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency
system.cpu.dcache.demand_hits 671742008 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 92172195491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003672 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2475804 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 944882 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 52251622000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002271 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530922 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.104320 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 674153748 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37718.232311 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4095.103693 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 674217812 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37229.197259 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 671661766 # number of overall hits
system.cpu.dcache.overall_miss_latency 93993155991 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003696 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2491982 # number of overall misses
system.cpu.dcache.overall_mshr_hits 958308 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 53368852000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002275 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1533674 # number of overall MSHR misses
system.cpu.dcache.overall_hits 671742008 # number of overall hits
system.cpu.dcache.overall_miss_latency 92172195491 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003672 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2475804 # number of overall misses
system.cpu.dcache.overall_mshr_hits 944882 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 52251622000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002271 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530922 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1526954 # number of replacements
system.cpu.dcache.sampled_refs 1531050 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 1526826 # number of replacements
system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.104320 # Cycle average of tags in use
system.cpu.dcache.total_refs 671672090 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4095.103693 # Cycle average of tags in use
system.cpu.dcache.total_refs 671742017 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74616 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 31207203 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12052 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30419221 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2934529925 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 711825403 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 561989361 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 100109049 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45710 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 85215 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 772921338 # DTB accesses
system.cpu.dcache.writebacks 107349 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 30546765 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 11879 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30415983 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2934070840 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 711662273 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 561899990 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 100055757 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45705 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 84033 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 772892535 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 772287215 # DTB hits
system.cpu.dtb.data_misses 634123 # DTB misses
system.cpu.dtb.data_hits 772261224 # DTB hits
system.cpu.dtb.data_misses 631311 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 514592222 # DTB read accesses
system.cpu.dtb.read_accesses 514571381 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 513995856 # DTB read hits
system.cpu.dtb.read_misses 596366 # DTB read misses
system.cpu.dtb.write_accesses 258329116 # DTB write accesses
system.cpu.dtb.read_hits 513977951 # DTB read hits
system.cpu.dtb.read_misses 593430 # DTB read misses
system.cpu.dtb.write_accesses 258321154 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 258291359 # DTB write hits
system.cpu.dtb.write_misses 37757 # DTB write misses
system.cpu.fetch.Branches 347019771 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 347236210 # Number of cache lines fetched
system.cpu.fetch.Cycles 925540339 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4572630 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3016868050 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28795074 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.246923 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 347236210 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 288725327 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.146660 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1405216231 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.146907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.027321 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 258283273 # DTB write hits
system.cpu.dtb.write_misses 37881 # DTB write misses
system.cpu.fetch.Branches 346972918 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 347200626 # Number of cache lines fetched
system.cpu.fetch.Cycles 925414333 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4548226 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3016464690 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28792576 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.247062 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 347200626 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 288687732 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.147876 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1404248818 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.148098 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.027750 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 826912311 58.85% 58.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 54085812 3.85% 62.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 40125133 2.86% 65.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 63577185 4.52% 70.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121409089 8.64% 78.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 34600240 2.46% 81.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 37932193 2.70% 83.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7024441 0.50% 84.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219549827 15.62% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 826035319 58.82% 58.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 54061013 3.85% 62.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 40121660 2.86% 65.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 63576700 4.53% 70.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121382183 8.64% 78.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 34599008 2.46% 81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 37926839 2.70% 83.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7023317 0.50% 84.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219522779 15.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1405216231 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 347236210 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15852.092893 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.295350 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 347225531 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 169284500 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 1404248818 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 347200626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15854.453498 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.008587 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 347189949 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 169278000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10679 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 894 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 113959000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 10677 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 895 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 113843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9785 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 9782 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 35489.118050 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 35496.365300 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 347236210 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15852.092893 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
system.cpu.icache.demand_hits 347225531 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 169284500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 347200626 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15854.453498 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency
system.cpu.icache.demand_hits 347189949 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 169278000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
system.cpu.icache.demand_misses 10679 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 894 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 113959000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 10677 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 895 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 113843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9785 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 9782 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.787162 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1612.107078 # Average occupied blocks per context
system.cpu.icache.overall_accesses 347236210 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15852.092893 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.787157 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1612.097956 # Average occupied blocks per context
system.cpu.icache.overall_accesses 347200626 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15854.453498 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 347225531 # number of overall hits
system.cpu.icache.overall_miss_latency 169284500 # number of overall miss cycles
system.cpu.icache.overall_hits 347189949 # number of overall hits
system.cpu.icache.overall_miss_latency 169278000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
system.cpu.icache.overall_misses 10679 # number of overall misses
system.cpu.icache.overall_mshr_hits 894 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 113959000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 10677 # number of overall misses
system.cpu.icache.overall_mshr_hits 895 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 113843000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9785 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 9782 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 8113 # number of replacements
system.cpu.icache.sampled_refs 9784 # Sample count of references to valid blocks.
system.cpu.icache.replacements 8111 # number of replacements
system.cpu.icache.sampled_refs 9781 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1612.107078 # Cycle average of tags in use
system.cpu.icache.total_refs 347225531 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1612.097956 # Cycle average of tags in use
system.cpu.icache.total_refs 347189949 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 161393 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 274718833 # Number of branches executed
system.cpu.iew.EXEC:nop 329034713 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.424505 # Inst execution rate
system.cpu.iew.EXEC:refs 773457001 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 258330075 # Number of stores executed
system.cpu.idleCycles 145480 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 274684945 # Number of branches executed
system.cpu.iew.EXEC:nop 329038670 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.425383 # Inst execution rate
system.cpu.iew.EXEC:refs 773428063 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 258322146 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1632862772 # num instructions consuming a value
system.cpu.iew.WB:count 2000954749 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.695811 # average fanout of values written-back
system.cpu.iew.WB:consumers 1632528882 # num instructions consuming a value
system.cpu.iew.WB:count 2000778402 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.695828 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1136164328 # num instructions producing a value
system.cpu.iew.WB:rate 1.423784 # insts written-back per cycle
system.cpu.iew.WB:sent 2001905607 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 30878599 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3451748 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 655963109 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 64 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 51733 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302851236 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2713712461 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 515126926 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84126603 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2001967300 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 131046 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1135959868 # num instructions producing a value
system.cpu.iew.WB:rate 1.424656 # insts written-back per cycle
system.cpu.iew.WB:sent 2001740023 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 30875630 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3371474 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 655915316 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 69 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 46568 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302840686 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2713549765 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 515105917 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84189444 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2001799378 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 130178 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1380 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 100109049 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 140868 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 1349 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 100055757 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 139189 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50632865 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 227 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 50550937 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 225 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3782 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4125 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 144367807 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92056105 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3782 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 787958 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 30090641 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.297191 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.297191 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 3543 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4083 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 144320014 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92045555 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3543 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 788016 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 30087614 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.298099 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.298099 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203926458 57.71% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 17656 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203839026 57.71% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 18400 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851408 1.34% 59.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254704 0.40% 59.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850839 1.34% 59.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254698 0.40% 59.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204647 0.35% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 555703221 26.64% 86.43% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283133054 13.57% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 555691648 26.64% 86.43% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283126808 13.57% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2086093903 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 35524455 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017029 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 2085988822 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 36673966 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017581 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5029 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5496 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # at
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 26764066 75.34% 75.35% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 8755360 24.65% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 27909398 76.10% 76.12% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 8759072 23.88% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1405216231 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.484536 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637275 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1404248818 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.485484 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.638010 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 532926303 37.92% 37.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 283749414 20.19% 58.12% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 275573113 19.61% 77.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 156459284 11.13% 88.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 63140415 4.49% 93.36% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 47210297 3.36% 96.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 32913048 2.34% 99.06% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10225878 0.73% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 3018479 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 532242124 37.90% 37.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 283422756 20.18% 58.09% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 275702525 19.63% 77.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 156569721 11.15% 88.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 62891882 4.48% 93.35% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 46986104 3.35% 96.69% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 33054153 2.35% 99.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10407537 0.74% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2972016 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1405216231 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.484365 # Inst issue rate
system.cpu.iq.iqInstsAdded 2384677684 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2086093903 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 561606840 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12399741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 517624785 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 1404248818 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.485330 # Inst issue rate
system.cpu.iq.iqInstsAdded 2384511026 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2085988822 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 561440182 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12400568 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 517571269 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 347236419 # ITB accesses
system.cpu.itb.fetch_accesses 347200834 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 347236210 # ITB hits
system.cpu.itb.fetch_misses 209 # ITB misses
system.cpu.itb.fetch_hits 347200626 # ITB hits
system.cpu.itb.fetch_misses 208 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,106 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 71649 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2514267000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 71649 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297462000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 71649 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1469186 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 29045 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 49263470000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.980231 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1440141 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644985000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980231 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1440141 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2624 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 89995000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2624 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 81349000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2624 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35152.205453 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32141.578294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2350171000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.933105 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 66857 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148889500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933105 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66857 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1469054 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34210.498210 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.429333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 55232 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 48367555000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.962403 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1413822 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43829089000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962403 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1413822 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107349 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107349 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.023753 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.041538 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540835 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34249.291899 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 29045 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 51777737000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.981150 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1511790 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 1540704 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34253.019054 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 60025 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 50717726000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.961041 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1480679 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 46942447000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.981150 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1511790 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 45977978500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.961041 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1480679 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.927958 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.046323 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 30407.323461 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1517.897239 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540835 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34249.291899 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.881669 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.093123 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 28890.531626 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3051.454384 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540704 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34253.019054 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 29045 # number of overall hits
system.cpu.l2cache.overall_miss_latency 51777737000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.981150 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1511790 # number of overall misses
system.cpu.l2cache.overall_hits 60025 # number of overall hits
system.cpu.l2cache.overall_miss_latency 50717726000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.961041 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1480679 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 46942447000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.981150 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1511790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 45977978500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.961041 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1480679 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 1474292 # number of replacements
system.cpu.l2cache.sampled_refs 1506959 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1480409 # number of replacements
system.cpu.l2cache.sampled_refs 1513096 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31925.220700 # Cycle average of tags in use
system.cpu.l2cache.total_refs 35795 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 31941.986010 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62851 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66899 # number of writebacks
system.cpu.memDep0.conflictingLoads 126385471 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 12290638 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 655963109 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 302851236 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1405377624 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 20016233 # Number of cycles rename is blocking
system.cpu.l2cache.writebacks 66898 # number of writebacks
system.cpu.memDep0.conflictingLoads 122494554 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20280761 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 655915316 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 302840686 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1404394298 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 19598244 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 673555 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 725805122 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10749358 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3307765426 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2838518766 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1890285688 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 546657671 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 100109049 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 12606278 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 505316618 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 21878 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2883 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 26993135 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 69 # count of temporary serializing insts renamed
system.cpu.timesIdled 4180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 671773 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 725577995 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10516920 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 17 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3307285723 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2838114179 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1889955714 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 546658925 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 100055757 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 12336225 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 504986644 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 21672 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2827 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 26425102 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 76 # count of temporary serializing insts renamed
system.cpu.timesIdled 3680 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

12
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:14
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:48:17
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 2814926000000 because target called exit()
Exiting @ tick 2813467842000 because target called exit()

174
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1265087 # Simulator instruction rate (inst/s)
host_mem_usage 213100 # Number of bytes of host memory used
host_seconds 1588.02 # Real time elapsed on the host
host_tick_rate 1772597573 # Simulator tick rate (ticks/s)
host_inst_rate 1340007 # Simulator instruction rate (inst/s)
host_mem_usage 199308 # Number of bytes of host memory used
host_seconds 1499.24 # Real time elapsed on the host
host_tick_rate 1876600376 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814926 # Number of seconds simulated
sim_ticks 2814926000000 # Number of ticks simulated
sim_seconds 2.813468 # Number of seconds simulated
sim_ticks 2813467842000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55392.203496 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.203496 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 80772468000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 76397892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210720566 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4162480000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000353 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 74330 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3939490000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 74330 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55421.682690 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720332400 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 84934948000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002123 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1532522 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 80337382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1532522 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.205038 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55421.682690 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 720332400 # number of overall hits
system.cpu.dcache.overall_miss_latency 84934948000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002123 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1532522 # number of overall misses
system.cpu.dcache.overall_hits 720334778 # number of overall hits
system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1530144 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 80337382000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1532522 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.205038 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74616 # number of writebacks
system.cpu.dcache.writebacks 107612 # number of writebacks
system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 721864922 # DTB hits
@ -122,7 +122,7 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1478.422015 # Average occupied blocks per context
system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1478.422015 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,36 +164,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 29321 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 74852284000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.980037 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1439467 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 57578680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980037 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1439467 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2378 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 123656000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2378 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 95120000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2378 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.023963 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 29321 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 78593788000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1511419 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 60456760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1511419 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.927128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.046829 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 30380.118149 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1534.487101 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 29321 # number of overall hits
system.cpu.l2cache.overall_miss_latency 78593788000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1511419 # number of overall misses
system.cpu.l2cache.overall_hits 60925 # number of overall hits
system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1479815 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 60456760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1511419 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 1473631 # number of replacements
system.cpu.l2cache.sampled_refs 1506296 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1479797 # number of replacements
system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31914.605250 # Cycle average of tags in use
system.cpu.l2cache.total_refs 36095 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use
system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66899 # number of writebacks
system.cpu.l2cache.writebacks 66898 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5629852000 # number of cpu cycles simulated
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722823898 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls

2
tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

12
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 14:03:19
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:06:09
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 2371349716000 because target called exit()
Exiting @ tick 2369896178000 because target called exit()

203
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1110314 # Simulator instruction rate (inst/s)
host_mem_usage 216744 # Number of bytes of host memory used
host_seconds 1650.59 # Real time elapsed on the host
host_tick_rate 1436666087 # Simulator tick rate (ticks/s)
host_inst_rate 1326917 # Simulator instruction rate (inst/s)
host_mem_usage 202424 # Number of bytes of host memory used
host_seconds 1381.15 # Real time elapsed on the host
host_tick_rate 1715881736 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1832675505 # Number of instructions simulated
sim_seconds 2.371350 # Number of seconds simulated
sim_ticks 2371349716000 # Number of ticks simulated
sim_seconds 2.369896 # Number of seconds simulated
sim_ticks 2369896178000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55313.730657 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.730657 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 80822266000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 79731778000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 76438783000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 75348295000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.434541 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.434541 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 276871387 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4159414000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000268 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 74276 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3936586000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 74276 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 276872883 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55346.901240 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency
system.cpu.dcache.demand_hits 895774291 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 84981680000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.001711 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1535437 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 54452.292494 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency
system.cpu.dcache.demand_hits 895775787 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 83526604000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1533941 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 80375369000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001711 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1535437 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 78924781000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1533941 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999748 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.966832 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 4094.966269 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55346.901240 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52346.901240 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54452.292494 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 895774291 # number of overall hits
system.cpu.dcache.overall_miss_latency 84981680000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.001711 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1535437 # number of overall misses
system.cpu.dcache.overall_hits 895775787 # number of overall hits
system.cpu.dcache.overall_miss_latency 83526604000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1533941 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 80375369000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001711 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1535437 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 78924781000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1533941 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1529845 # number of replacements
system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.966832 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.966269 # Cycle average of tags in use
system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 993999000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74582 # number of writebacks
system.cpu.dcache.warmup_cycle 993944000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107259 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 18784.729586 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15784.729586 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 371994000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 312585000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 18784.729586 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 371994000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 312585000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.679847 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1392.325794 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1392.325384 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1390221752 # number of overall hits
system.cpu.icache.overall_miss_latency 371994000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
system.cpu.icache.overall_misses 19803 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 312585000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 18364 # number of replacements
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1392.325794 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1392.325384 # Cycle average of tags in use
system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3784508000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999986 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 72779 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911160000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999986 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 72779 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 41422 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 74856184000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.972030 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1439542 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 57581680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972030 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1439542 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 1496 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 77792000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 1496 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 59840000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 1496 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74582 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 74582 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 67385 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 73506108000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.954499 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1413579 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56543160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954499 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1413579 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.032374 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.050081 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 41423 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 78640692000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.973340 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1512321 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 74072 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 76942944000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.952327 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1479672 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 60492840000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.973340 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1512321 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 59186880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.952327 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1479672 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.927467 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.046803 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 30391.242944 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1533.635543 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.881760 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.092816 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 28893.501877 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3041.393075 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 41423 # number of overall hits
system.cpu.l2cache.overall_miss_latency 78640692000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.973340 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1512321 # number of overall misses
system.cpu.l2cache.overall_hits 74072 # number of overall hits
system.cpu.l2cache.overall_miss_latency 76942944000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.952327 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1479672 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 60492840000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.973340 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1512321 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 59186880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.952327 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1479672 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 1472894 # number of replacements
system.cpu.l2cache.sampled_refs 1505603 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1478797 # number of replacements
system.cpu.l2cache.sampled_refs 1511517 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31924.878487 # Cycle average of tags in use
system.cpu.l2cache.total_refs 48742 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 31934.894953 # Cycle average of tags in use
system.cpu.l2cache.total_refs 75699 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66101 # number of writebacks
system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4742699432 # number of cpu cycles simulated
system.cpu.numCycles 4739792356 # number of cpu cycles simulated
system.cpu.num_insts 1832675505 # Number of instructions executed
system.cpu.num_refs 908401146 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls

2
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -191,7 +191,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:06
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:19:32
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 104900991500 because target called exit()
Exiting @ tick 104166942500 because target called exit()

287
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 31368 # Simulator instruction rate (inst/s)
host_mem_usage 223704 # Number of bytes of host memory used
host_seconds 2816.26 # Real time elapsed on the host
host_tick_rate 37248320 # Simulator tick rate (ticks/s)
host_inst_rate 58405 # Simulator instruction rate (inst/s)
host_mem_usage 209896 # Number of bytes of host memory used
host_seconds 1512.56 # Real time elapsed on the host
host_tick_rate 68868083 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.104901 # Number of seconds simulated
sim_ticks 104900991500 # Number of ticks simulated
sim_seconds 0.104167 # Number of seconds simulated
sim_ticks 104166942500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits
@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 434959
system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed
system.cpu.RegFile-Manager.regFileAccesses 156429013 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads 103882132 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileAccesses 156429280 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads 103882399 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 2136233 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 84.755939 # Percentage of cycles cpu is active
system.cpu.RegFile-Manager.regForwards 2135966 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 85.354290 # Percentage of cycles cpu is active
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.comInts 30457224 # Number of Integer instructions committed
@ -42,28 +42,28 @@ system.cpu.comStores 14844619 # Nu
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.cpi 2.374919 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.374919 # CPI: Total CPI of All Threads
system.cpu.cpi 2.358301 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.358301 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 37505.438897 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34394.916565 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2312217500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2279055500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2123402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2090041500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 8303642500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7862076500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 52898.208639 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49865.139506 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7595019000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7159537000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 51049.814620 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10615860000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 48320.843773 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9874074500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 9985478500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 9249578500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995330 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.871208 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.995297 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.738170 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 51049.814620 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 48320.843773 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34682064 # number of overall hits
system.cpu.dcache.overall_miss_latency 10615860000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
system.cpu.dcache.overall_misses 207951 # number of overall misses
system.cpu.dcache.overall_hits 34685671 # number of overall hits
system.cpu.dcache.overall_miss_latency 9874074500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_misses 204344 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 9985478500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 9249578500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4076.871208 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4076.738170 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 834930000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 149164 # number of writebacks
system.cpu.dcache.warmup_cycle 834588000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161221 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
@ -126,50 +126,50 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 19062.290643 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96943862 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1513736500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_avg_miss_latency 19054.387931 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15836.123818 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96943861 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1513128000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 79410 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1586 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1233073000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 79411 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1587 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1232430500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 800 # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1245.680793 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1245.680780 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 19062.290643 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.demand_hits 96943862 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1513736500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_avg_miss_latency 19054.387931 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency
system.cpu.icache.demand_hits 96943861 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1513128000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses
system.cpu.icache.demand_misses 79410 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1586 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1233073000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 79411 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1587 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1232430500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.914717 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1873.340733 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.914428 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1872.748134 # Average occupied blocks per context
system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 19062.290643 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 19054.387931 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 96943862 # number of overall hits
system.cpu.icache.overall_miss_latency 1513736500 # number of overall miss cycles
system.cpu.icache.overall_hits 96943861 # number of overall hits
system.cpu.icache.overall_miss_latency 1513128000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses
system.cpu.icache.overall_misses 79410 # number of overall misses
system.cpu.icache.overall_mshr_hits 1586 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1233073000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 79411 # number of overall misses
system.cpu.icache.overall_mshr_hits 1587 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1232430500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 75778 # number of replacements
system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1873.340733 # Cycle average of tags in use
system.cpu.icache.total_refs 96943862 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1872.748134 # Cycle average of tags in use
system.cpu.icache.total_refs 96943861 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 31982342 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.421067 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.421067 # IPC: Total IPC of All Threads
system.cpu.idleCycles 30511976 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.424034 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.424034 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@ -201,105 +201,96 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 7525926000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740992500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_avg_miss_latency 52440.979168 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.144510 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 6894887500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259179000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 95311 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2263590000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.312281 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43279 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1731370500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312281 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43279 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 186907000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144288500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
system.cpu.l2cache.ReadReq_avg_miss_latency 52303.399887 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.932662 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 96118 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2221430000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.306458 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 42472 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1699089500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.306458 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 42472 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161221 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 161221 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.646134 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.718111 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52405.560939 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 95365 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9789516000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.662028 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 186803 # number of demand (read+write) misses
system.cpu.l2cache.demand_avg_miss_latency 52407.387713 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 108217 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9116317500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.616480 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 173951 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 7472363000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.662028 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 186803 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 6958268500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.616480 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 173951 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.089575 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.471967 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2935.193659 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15465.399858 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.086814 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.481065 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2844.720641 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15763.536508 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52405.560939 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 52407.387713 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 95365 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9789516000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.662028 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 186803 # number of overall misses
system.cpu.l2cache.overall_hits 108217 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9116317500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.616480 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 173951 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 7472363000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.662028 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 186803 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 6958268500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.616480 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 173951 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 147725 # number of replacements
system.cpu.l2cache.sampled_refs 173054 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 147575 # number of replacements
system.cpu.l2cache.sampled_refs 172919 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18400.593517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 111816 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18608.257148 # Cycle average of tags in use
system.cpu.l2cache.total_refs 124175 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120606 # number of writebacks
system.cpu.numCycles 209801984 # number of cpu cycles simulated
system.cpu.runCycles 177819642 # Number of cycles cpu stages are processed.
system.cpu.l2cache.writebacks 120508 # number of writebacks
system.cpu.numCycles 208333886 # number of cpu cycles simulated
system.cpu.runCycles 177821910 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.stage-0.idleCycles 112774700 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.idleCycles 111306602 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed.
system.cpu.stage-0.utilization 46.247076 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles 121437923 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 88364061 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 42.117839 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 119986198 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.utilization 46.572973 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles 119969888 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 88363998 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 42.414607 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 118518100 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 42.809789 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 174570714 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.utilization 43.111463 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 173102616 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 16.792630 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 121461311 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.utilization 16.910965 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 119993213 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization 42.106691 # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles 209801984 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.stage-4.utilization 42.403411 # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles 208333886 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:53:46
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:41:46
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 27109454000 because target called exit()
Exiting @ tick 27033689000 because target called exit()

661
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 111480 # Simulator instruction rate (inst/s)
host_mem_usage 216720 # Number of bytes of host memory used
host_seconds 713.95 # Real time elapsed on the host
host_tick_rate 37970836 # Simulator tick rate (ticks/s)
host_inst_rate 221900 # Simulator instruction rate (inst/s)
host_mem_usage 202972 # Number of bytes of host memory used
host_seconds 358.68 # Real time elapsed on the host
host_tick_rate 75369122 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027109 # Number of seconds simulated
sim_ticks 27109454000 # Number of ticks simulated
sim_seconds 0.027034 # Number of seconds simulated
sim_ticks 27033689000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 8073345 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 14152511 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 36189 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 458905 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 10574319 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 16281513 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1942543 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 3315405 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 51596234 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.712153 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.330354 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 22410479 43.43% 43.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 11292136 21.89% 65.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5122096 9.93% 75.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3547417 6.88% 82.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2566622 4.97% 87.10% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1508057 2.92% 90.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1006074 1.95% 91.97% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 827948 1.60% 93.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3315405 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 51596234 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 362306 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 8339248 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses
system.cpu.cpi 0.679309 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.679309 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 20462752 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20316340 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4411629000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007155 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 146412 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 84834 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1258305500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61578 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13581378 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 31995900999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.070620 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1031999 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 888502 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 4723892999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009820 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143497 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 165.294463 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 35076129 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30895.443100 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33897718 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 36407529999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.033596 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1178411 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 973336 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5982198499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 205075 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.995480 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4077.485052 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 35076129 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30895.443100 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33873274 # number of overall hits
system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1196678 # number of overall misses
system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses
system.cpu.dcache.overall_hits 33897718 # number of overall hits
system.cpu.dcache.overall_miss_latency 36407529999 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.033596 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1178411 # number of overall misses
system.cpu.dcache.overall_mshr_hits 973336 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5982198499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 205075 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200988 # number of replacements
system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 200979 # number of replacements
system.cpu.dcache.sampled_refs 205075 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use
system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 149251 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 36643462 # DTB accesses
system.cpu.dtb.data_acv 34 # DTB access violations
system.cpu.dtb.data_hits 36467174 # DTB hits
system.cpu.dtb.data_misses 176288 # DTB misses
system.cpu.dcache.tagsinuse 4077.485052 # Cycle average of tags in use
system.cpu.dcache.total_refs 33897762 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 181365000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161485 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3372983 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97431 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3660168 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 101877731 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 28530714 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 19554245 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1300005 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 281200 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 138292 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 36642762 # DTB accesses
system.cpu.dtb.data_acv 38 # DTB access violations
system.cpu.dtb.data_hits 36466941 # DTB hits
system.cpu.dtb.data_misses 175821 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 21569273 # DTB read accesses
system.cpu.dtb.read_acv 32 # DTB read access violations
system.cpu.dtb.read_hits 21411172 # DTB read hits
system.cpu.dtb.read_misses 158101 # DTB read misses
system.cpu.dtb.write_accesses 15074189 # DTB write accesses
system.cpu.dtb.read_accesses 21568925 # DTB read accesses
system.cpu.dtb.read_acv 36 # DTB read access violations
system.cpu.dtb.read_hits 21411469 # DTB read hits
system.cpu.dtb.read_misses 157456 # DTB read misses
system.cpu.dtb.write_accesses 15073837 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_hits 15056002 # DTB write hits
system.cpu.dtb.write_misses 18187 # DTB write misses
system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched
system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 15055472 # DTB write hits
system.cpu.dtb.write_misses 18365 # DTB write misses
system.cpu.fetch.Branches 16281513 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13394440 # Number of cache lines fetched
system.cpu.fetch.Cycles 33285984 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 153835 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103456008 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 576870 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.301134 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13394440 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 10015888 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.913464 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 52896239 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.955829 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.944816 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33031612 62.45% 62.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1863332 3.52% 65.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1548849 2.93% 68.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1858475 3.51% 72.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3937136 7.44% 79.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1852242 3.50% 83.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 690247 1.30% 84.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1146451 2.17% 86.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6967895 13.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 13386326 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6054.988859 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13297330 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006648 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 88996 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 521770500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006437 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86172 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 52896239 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 13394440 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 9549.980865 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6051.228388 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 13305596 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 848458500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006633 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 88844 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 2837 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 520448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006421 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86007 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 154.705439 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 9552.485505 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
system.cpu.icache.demand_hits 13297330 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 850133000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006648 # miss rate for demand accesses
system.cpu.icache.demand_misses 88996 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 2824 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 521770500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006437 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86172 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 13394440 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 9549.980865 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
system.cpu.icache.demand_hits 13305596 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 848458500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006633 # miss rate for demand accesses
system.cpu.icache.demand_misses 88844 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 2837 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 520448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006421 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86007 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1918.688120 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13386326 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9552.485505 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6054.988859 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.936980 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1918.935161 # Average occupied blocks per context
system.cpu.icache.overall_accesses 13394440 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 9549.980865 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 13297330 # number of overall hits
system.cpu.icache.overall_miss_latency 850133000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006648 # miss rate for overall accesses
system.cpu.icache.overall_misses 88996 # number of overall misses
system.cpu.icache.overall_mshr_hits 2824 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 521770500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006437 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86172 # number of overall MSHR misses
system.cpu.icache.overall_hits 13305596 # number of overall hits
system.cpu.icache.overall_miss_latency 848458500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006633 # miss rate for overall accesses
system.cpu.icache.overall_misses 88844 # number of overall misses
system.cpu.icache.overall_mshr_hits 2837 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 520448000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006421 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86007 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 84124 # number of replacements
system.cpu.icache.sampled_refs 86171 # Sample count of references to valid blocks.
system.cpu.icache.replacements 83959 # number of replacements
system.cpu.icache.sampled_refs 86006 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1918.688120 # Cycle average of tags in use
system.cpu.icache.total_refs 13297330 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1918.935161 # Cycle average of tags in use
system.cpu.icache.total_refs 13305596 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1204946 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14764091 # Number of branches executed
system.cpu.iew.EXEC:nop 9400465 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.566510 # Inst execution rate
system.cpu.iew.EXEC:refs 36986360 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15307304 # Number of stores executed
system.cpu.idleCycles 1171140 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14765953 # Number of branches executed
system.cpu.iew.EXEC:nop 9399098 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.570651 # Inst execution rate
system.cpu.iew.EXEC:refs 36985556 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15306955 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 42224308 # num instructions consuming a value
system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765793 # average fanout of values written-back
system.cpu.iew.WB:consumers 42195611 # num instructions consuming a value
system.cpu.iew.WB:count 84441959 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765718 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32335073 # num instructions producing a value
system.cpu.iew.WB:rate 1.557690 # insts written-back per cycle
system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 401805 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 605778 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 23014883 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5009 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 349401 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16347988 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 99082046 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21679056 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539226 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84934458 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 11054 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 32309953 # num instructions producing a value
system.cpu.iew.WB:rate 1.561791 # insts written-back per cycle
system.cpu.iew.WB:sent 84679067 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 403539 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 558736 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 23014663 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 344896 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 16344120 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 99062445 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21678601 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539249 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 84921008 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 9867 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 8786 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1300005 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 41358 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 953186 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 947297 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 703 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 20710 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1355 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2635484 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1503369 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 20710 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 131758 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270047 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.467970 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 20504 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1356 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 2635264 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1499501 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 20504 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 133144 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 270395 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.472085 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.472085 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47968991 56.12% 56.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 42906 0.05% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47958643 56.12% 56.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 42972 0.05% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122147 0.14% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122098 0.14% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122353 0.14% 56.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38520 0.05% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122222 0.14% 56.45% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.45% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38519 0.05% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 21790369 25.49% 82.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388261 18.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 21787306 25.49% 81.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388360 18.01% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 85473684 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 995540 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011647 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 85460257 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 970619 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011358 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 102737 10.32% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 453943 45.60% 55.92% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 438860 44.08% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 98326 10.13% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.13% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 436344 44.96% 55.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 435949 44.91% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 53013963 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.612286 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.719350 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 52896239 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.615621 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720411 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 17564950 33.13% 33.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 14012876 26.43% 59.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 8103290 15.29% 74.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4796735 9.05% 83.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 4597424 8.67% 92.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2085134 3.93% 96.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1155738 2.18% 98.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 468299 0.88% 99.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 229517 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 17480622 33.05% 33.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 13990970 26.45% 59.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 8059116 15.24% 74.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4840128 9.15% 83.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 4581404 8.66% 92.54% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2086569 3.94% 96.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1156021 2.19% 98.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 475188 0.90% 99.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 226221 0.43% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 53013963 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate
system.cpu.iq.iqInstsAdded 89676572 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85473684 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5009 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9869392 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 46778 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 52896239 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.580625 # Inst issue rate
system.cpu.iq.iqInstsAdded 89658342 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 85460257 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 9847468 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 48230 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 6786581 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 13413339 # ITB accesses
system.cpu.itb.fetch_accesses 13421357 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 13386326 # ITB hits
system.cpu.itb.fetch_misses 27013 # ITB misses
system.cpu.itb.fetch_hits 13394440 # ITB hits
system.cpu.itb.fetch_misses 26917 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -343,107 +343,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits
system.cpu.l2cache.ReadExReq_accesses 143498 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 12072 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 4509238000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915873 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131426 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4101673500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915873 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131426 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147584 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 103938 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1489830500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.295737 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43646 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1354463000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295737 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43646 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161485 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 161485 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.759972 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 291082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34266.293296 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 116010 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5999068500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.601453 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 5456136500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.601453 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.094631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.481096 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3100.873906 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15764.562961 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 291082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34266.293296 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 103332 # number of overall hits
system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 187924 # number of overall misses
system.cpu.l2cache.overall_hits 116010 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5999068500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.601453 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 175072 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 5456136500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.601453 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 148884 # number of replacements
system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 148714 # number of replacements
system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use
system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18865.436867 # Cycle average of tags in use
system.cpu.l2cache.total_refs 132289 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120621 # number of writebacks
system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 54218909 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking
system.cpu.l2cache.writebacks 120514 # number of writebacks
system.cpu.memDep0.conflictingLoads 12522416 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11202183 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 23014663 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16344120 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 54067379 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1899423 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed
system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 50756 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 28921656 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1270692 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 121761220 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 101056260 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 60792051 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 19304913 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1300005 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1392613 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 8245170 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 77629 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5282 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2690297 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5280 # count of temporary serializing insts renamed
system.cpu.timesIdled 40629 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:57:42
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:47:45
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 135015129000 because target called exit()
Exiting @ tick 134276988000 because target called exit()

205
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1159310 # Simulator instruction rate (inst/s)
host_mem_usage 215356 # Number of bytes of host memory used
host_seconds 76.20 # Real time elapsed on the host
host_tick_rate 1771821789 # Simulator tick rate (ticks/s)
host_inst_rate 1350777 # Simulator instruction rate (inst/s)
host_mem_usage 201544 # Number of bytes of host memory used
host_seconds 65.40 # Real time elapsed on the host
host_tick_rate 2053162286 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135015 # Number of seconds simulated
sim_ticks 135015129000 # Number of ticks simulated
sim_seconds 0.134277 # Number of seconds simulated
sim_ticks 134276988000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2294180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2111882000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 8240064000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7798509000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 50657.337546 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10534244000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 9910391000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995838 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4078.950714 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.995815 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50657.337546 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47657.337546 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34682064 # number of overall hits
system.cpu.dcache.overall_miss_latency 10534244000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
system.cpu.dcache.overall_misses 207951 # number of overall misses
system.cpu.dcache.overall_hits 34685671 # number of overall hits
system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_misses 204344 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 9910391000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4078.950714 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 943578000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 149164 # number of writebacks
system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 161222 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
@ -90,13 +90,13 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 18802.449108 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15802.449108 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1437184000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 1207876000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -108,31 +108,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 18802.449108 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1437184000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1207876000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.913991 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1871.853872 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.913772 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 18802.449108 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15802.449108 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88361638 # number of overall hits
system.cpu.icache.overall_miss_latency 1437184000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1207876000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1871.853872 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,37 +164,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 7463248000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 94094 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2241616000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.314194 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 43108 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1724320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314194 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 43108 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51596.340449 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 186108000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.639727 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 94148 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9704864000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.664691 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 186632 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 7465280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.664691 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 186632 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.088307 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.473299 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2893.659899 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15509.045444 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.085649 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.482430 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 94148 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9704864000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.664691 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 186632 # number of overall misses
system.cpu.l2cache.overall_hits 107000 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 173780 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 7465280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.664691 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 186632 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 147555 # number of replacements
system.cpu.l2cache.sampled_refs 172883 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 147405 # number of replacements
system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18402.705343 # Cycle average of tags in use
system.cpu.l2cache.total_refs 110598 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120604 # number of writebacks
system.cpu.l2cache.writebacks 120506 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 270030258 # number of cpu cycles simulated
system.cpu.numCycles 268553976 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls

2
tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:53:04
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:54
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 133464153000 because target called exit()
Exiting @ tick 133078695000 because target called exit()

205
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1245224 # Simulator instruction rate (inst/s)
host_mem_usage 218772 # Number of bytes of host memory used
host_seconds 78.70 # Real time elapsed on the host
host_tick_rate 1695886374 # Simulator tick rate (ticks/s)
host_inst_rate 1323688 # Simulator instruction rate (inst/s)
host_mem_usage 204612 # Number of bytes of host memory used
host_seconds 74.03 # Real time elapsed on the host
host_tick_rate 1797531911 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
sim_seconds 0.133464 # Number of seconds simulated
sim_ticks 133464153000 # Number of ticks simulated
sim_seconds 0.133079 # Number of seconds simulated
sim_ticks 133078695000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 35865.411818 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32865.411818 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 35146.149639 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32146.149639 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1901620000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 1863484000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 53021 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1742557000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1704421000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 53021 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55969.020638 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52969.020638 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 19755779 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6158887000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005539 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 110041 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5828764000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005539 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 110041 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 54270.699030 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51270.699030 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 19758786 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5808810000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005388 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 107034 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5487708000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005388 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 107034 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 292.838112 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 47030259 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 49432.160773 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
system.cpu.dcache.demand_hits 46867197 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 8060507000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003467 # miss rate for demand accesses
system.cpu.dcache.demand_misses 163062 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 47935.359720 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 44935.359720 # average overall mshr miss latency
system.cpu.dcache.demand_hits 46870204 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 7672294000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003403 # miss rate for demand accesses
system.cpu.dcache.demand_misses 160055 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7571321000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003467 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 163062 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 7192129000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003403 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 160055 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995361 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.997954 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.995347 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.942972 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 47030259 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 49432.160773 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 46432.160773 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 47935.359720 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 44935.359720 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 46867197 # number of overall hits
system.cpu.dcache.overall_miss_latency 8060507000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003467 # miss rate for overall accesses
system.cpu.dcache.overall_misses 163062 # number of overall misses
system.cpu.dcache.overall_hits 46870204 # number of overall hits
system.cpu.dcache.overall_miss_latency 7672294000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003403 # miss rate for overall accesses
system.cpu.dcache.overall_misses 160055 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7571321000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003467 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 163062 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 7192129000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003403 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 160055 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 155959 # number of replacements
system.cpu.dcache.sampled_refs 160055 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4076.997954 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4076.942972 # Cycle average of tags in use
system.cpu.dcache.total_refs 46870204 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1079446000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 110614 # number of writebacks
system.cpu.dcache.warmup_cycle 1079223000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 122819 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.icache.ReadReq_accesses 78097320 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24224.561032 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21224.561032 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 78078412 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 458038000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 401314000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 78097320 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24224.561032 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
system.cpu.icache.demand_hits 78078412 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 458038000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 401314000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.847896 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1736.491216 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.847769 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1736.230096 # Average occupied blocks per context
system.cpu.icache.overall_accesses 78097320 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24224.561032 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21224.561032 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 78078412 # number of overall hits
system.cpu.icache.overall_miss_latency 458038000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_misses 18908 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 401314000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 16890 # number of replacements
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1736.491216 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1736.230096 # Cycle average of tags in use
system.cpu.icache.total_refs 78078412 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 81 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 5561556000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999243 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 106953 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4278120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999243 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 106953 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 4407 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.958826 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 102627 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958826 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 71929 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 39723 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1674712000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.447747 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32206 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1288240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.447747 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32206 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 3007 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51878.949119 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 156000000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 3007 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 120280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 110614 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 110614 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 40637 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1627184000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.435040 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 31292 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1251680000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435040 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 31292 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 122819 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 122819 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.368048 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.466930 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 178963 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 39804 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 7236268000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.777585 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 139159 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 45044 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 6963788000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.748306 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 133919 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5566360000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.777585 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 139159 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 5356760000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.748306 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 133919 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.070819 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.476669 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2320.602092 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15619.501011 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.066136 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.489058 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2167.134157 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16025.466133 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 178963 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 39804 # number of overall hits
system.cpu.l2cache.overall_miss_latency 7236268000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.777585 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 139159 # number of overall misses
system.cpu.l2cache.overall_hits 45044 # number of overall hits
system.cpu.l2cache.overall_miss_latency 6963788000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.748306 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 133919 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5566360000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.777585 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 139159 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 5356760000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.748306 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 133919 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 114078 # number of replacements
system.cpu.l2cache.sampled_refs 132866 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 113661 # number of replacements
system.cpu.l2cache.sampled_refs 132491 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17940.103104 # Cycle average of tags in use
system.cpu.l2cache.total_refs 48901 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18192.600290 # Cycle average of tags in use
system.cpu.l2cache.total_refs 61864 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 88549 # number of writebacks
system.cpu.l2cache.writebacks 88450 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 266928306 # number of cpu cycles simulated
system.cpu.numCycles 266157390 # number of cpu cycles simulated
system.cpu.num_insts 97997303 # Number of instructions executed
system.cpu.num_refs 47871034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

2
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864

12
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:03:41
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:06:02
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 16:35:02
M5 executing on phenom
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 203281649000 because target called exit()
Exiting @ tick 202941992000 because target called exit()

225
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1039608 # Simulator instruction rate (inst/s)
host_mem_usage 220432 # Number of bytes of host memory used
host_seconds 130.95 # Real time elapsed on the host
host_tick_rate 1552328099 # Simulator tick rate (ticks/s)
host_inst_rate 1222037 # Simulator instruction rate (inst/s)
host_mem_usage 206136 # Number of bytes of host memory used
host_seconds 111.40 # Real time elapsed on the host
host_tick_rate 1821674437 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.203282 # Number of seconds simulated
sim_ticks 203281649000 # Number of ticks simulated
sim_seconds 0.202942 # Number of seconds simulated
sim_ticks 202941992000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 38539.616255 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35539.616255 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1753514000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 1709246000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1617017000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1572749000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15879 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 2072000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.002325 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 37 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 1961000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002325 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 37 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 30800 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 27800 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 462000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 417000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55967.131927 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52967.131927 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20756479 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6034656000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005168 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 107825 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5711181000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005168 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 107825 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20759140 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5738404000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105164 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5422912000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105164 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 50795.504944 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57942281 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 7788170000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002639 # miss rate for demand accesses
system.cpu.dcache.demand_misses 153324 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 49432.508313 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 7447650000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7328198000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002639 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 153324 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 6995661000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997956 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4087.629454 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.997953 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 50795.504944 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 57942281 # number of overall hits
system.cpu.dcache.overall_miss_latency 7788170000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002639 # miss rate for overall accesses
system.cpu.dcache.overall_misses 153324 # number of overall misses
system.cpu.dcache.overall_hits 57944942 # number of overall hits
system.cpu.dcache.overall_miss_latency 7447650000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_misses 150663 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7328198000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002639 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 153324 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 6995661000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4087.629454 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 776960000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 108328 # number of writebacks
system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 118818 # number of writebacks
system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 16931.987339 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13931.987339 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 16930.864488 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3166688000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 3166478000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2605616000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 2605406000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 16931.987339 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 16930.864488 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency
system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3166688000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 3166478000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2605616000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 2605406000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.978873 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 2004.731937 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.978868 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context
system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16931.987339 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 134366560 # number of overall hits
system.cpu.icache.overall_miss_latency 3166688000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 3166478000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2605616000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 2605406000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -134,45 +134,36 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 2004.731937 # Cycle average of tags in use
system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use
system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 144738462000 # Cycle when the warmup percentage was hit.
system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 84 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 5464940000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.999201 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 105095 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4203800000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999201 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 105095 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 3599 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 5282160000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.965782 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 101580 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4063200000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.965782 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 101580 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 192883 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2061280000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.170478 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 39640 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1585600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170478 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 39640 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2683 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51689.899366 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 138684000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2683 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 107320000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2683 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 108328 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 108328 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 193942 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2006212000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.165923 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 38581 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1543240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165923 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 38581 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 118818 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 118818 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.441131 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 192967 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 7526220000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.428588 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 144735 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 197541 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 7288372000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.415043 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 140161 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 5789400000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.428588 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 144735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 5606440000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.415043 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 140161 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.127128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.467489 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 4165.731733 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15318.691405 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.121030 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.481204 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 192967 # number of overall hits
system.cpu.l2cache.overall_miss_latency 7526220000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.428588 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 144735 # number of overall misses
system.cpu.l2cache.overall_hits 197541 # number of overall hits
system.cpu.l2cache.overall_miss_latency 7288372000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.415043 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 140161 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 5789400000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.428588 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 144735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 5606440000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.415043 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 140161 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 120481 # number of replacements
system.cpu.l2cache.sampled_refs 139283 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 120138 # number of replacements
system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 19484.423138 # Cycle average of tags in use
system.cpu.l2cache.total_refs 200725 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use
system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 87388 # number of writebacks
system.cpu.l2cache.writebacks 87265 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 406563298 # number of cpu cycles simulated
system.cpu.numCycles 405883984 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

2
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

12
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:05:40
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +28,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 732922365000 because target called exit()
Exiting @ tick 725600064000 because target called exit()

663
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 115207 # Simulator instruction rate (inst/s)
host_mem_usage 207548 # Number of bytes of host memory used
host_seconds 15068.91 # Real time elapsed on the host
host_tick_rate 48638035 # Simulator tick rate (ticks/s)
host_inst_rate 201279 # Simulator instruction rate (inst/s)
host_mem_usage 193732 # Number of bytes of host memory used
host_seconds 8625.07 # Real time elapsed on the host
host_tick_rate 84126874 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.732922 # Number of seconds simulated
sim_ticks 732922365000 # Number of ticks simulated
sim_seconds 0.725600 # Number of seconds simulated
sim_ticks 725600064000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 297651815 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 304473054 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 146 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19905340 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 266187209 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 345286425 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23890708 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.BTBHits 297121632 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 303782824 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 142 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 19928405 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 265297852 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 344822488 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 23968882 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 63402454 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 61479856 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1362326064 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.335789 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.108307 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1350419468 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.347567 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.103580 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 722221726 53.01% 53.01% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 260663635 19.13% 72.15% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 126275090 9.27% 81.42% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 73614843 5.40% 86.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 49214339 3.61% 90.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 31342415 2.30% 92.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 24208215 1.78% 94.51% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 11383347 0.84% 95.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 63402454 4.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 709166800 52.51% 52.51% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 257980850 19.10% 71.62% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 128756395 9.53% 81.15% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 75319653 5.58% 86.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 50577217 3.75% 90.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 29303662 2.17% 92.65% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 27183744 2.01% 94.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10651291 0.79% 95.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 61479856 4.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1362326064 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1350419468 # Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19904825 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 19927893 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 616386841 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 598409142 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.844359 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.844359 # CPI: Total CPI of All Threads
system.cpu.cpi 0.835924 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.835924 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
@ -59,292 +59,290 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 521630579 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16446.832647 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11014.947389 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 511650921 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 164133765000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019132 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 9979658 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2703270 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 80149031000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013949 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276388 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_accesses 522152433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16274.867726 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10956.764593 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 512203202 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 161922418500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.019054 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 9949231 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 2672880 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 79725265000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013935 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7276351 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32545.971387 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34322.334946 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155766779 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 161484094789 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.030870 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4961723 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2963011 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 68600462724 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.012435 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1998712 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5974.555782 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 30410.724976 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 72.882698 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 121015 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65147 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 723010868 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1981167500 # number of cycles access was blocked
system.cpu.dcache.WriteReq_avg_miss_latency 26917.452067 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20483.226007 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 155989745 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 127555264405 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.029483 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 4738757 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 2853938 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 38607173559 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011727 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1884819 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.492044 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 72.937504 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 37706 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65110 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 118943277 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1980503500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 682359081 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 21793.023000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
system.cpu.dcache.demand_hits 667417700 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 325617859789 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14941381 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5666281 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 148749493724 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9275100 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 682880935 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19708.464012 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668192947 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 289477682905 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.021509 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14687988 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5526818 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 118332438559 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013415 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9161170 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997469 # Average percentage of cache occupancy
system.cpu.dcache.occ_%::1 -0.002947 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.632664 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::1 -12.069593 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 682359081 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 21793.023000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.997445 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4085.532750 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 682880935 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19708.464012 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 667417700 # number of overall hits
system.cpu.dcache.overall_miss_latency 325617859789 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14941381 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5666281 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 148749493724 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9275100 # number of overall MSHR misses
system.cpu.dcache.overall_hits 668192947 # number of overall hits
system.cpu.dcache.overall_miss_latency 289477682905 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.021509 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14687988 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5526818 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 118332438559 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013415 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9161170 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9156983 # number of replacements
system.cpu.dcache.sampled_refs 9161079 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 9157075 # number of replacements
system.cpu.dcache.sampled_refs 9161171 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.597867 # Cycle average of tags in use
system.cpu.dcache.total_refs 667684156 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7084801000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2367711 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 93349702 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 598 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54504022 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2803113220 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 722066213 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 542175542 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 91814713 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1721 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 4734607 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 769403639 # DTB accesses
system.cpu.dcache.tagsinuse 4085.532750 # Cycle average of tags in use
system.cpu.dcache.total_refs 668192949 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7084076000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3077872 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 79445863 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 739 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 54863160 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2804005174 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 723465377 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 543368654 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 89450574 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1719 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 4139574 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 765936230 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 753449541 # DTB hits
system.cpu.dtb.data_misses 15954098 # DTB misses
system.cpu.dtb.data_hits 750636298 # DTB hits
system.cpu.dtb.data_misses 15299932 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 567301584 # DTB read accesses
system.cpu.dtb.read_accesses 565223455 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 558063709 # DTB read hits
system.cpu.dtb.read_misses 9237875 # DTB read misses
system.cpu.dtb.write_accesses 202102055 # DTB write accesses
system.cpu.dtb.read_hits 556102001 # DTB read hits
system.cpu.dtb.read_misses 9121454 # DTB read misses
system.cpu.dtb.write_accesses 200712775 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 195385832 # DTB write hits
system.cpu.dtb.write_misses 6716223 # DTB write misses
system.cpu.fetch.Branches 345286425 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 353801341 # Number of cache lines fetched
system.cpu.fetch.Cycles 911477048 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8513687 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2856997588 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28043242 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.235555 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 353801341 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 321542523 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.949045 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1454140777 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.964732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.867668 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_hits 194534297 # DTB write hits
system.cpu.dtb.write_misses 6178478 # DTB write misses
system.cpu.fetch.Branches 344822488 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355034186 # Number of cache lines fetched
system.cpu.fetch.Cycles 913253672 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8462729 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2857790040 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28218175 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.237612 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355034186 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 321090514 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.969260 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1439870042 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.984756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.874458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 896465106 61.65% 61.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48268270 3.32% 64.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30594278 2.10% 67.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 50900501 3.50% 70.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 123419810 8.49% 79.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 68033881 4.68% 83.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 46960603 3.23% 86.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36759628 2.53% 89.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 152738700 10.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 881650589 61.23% 61.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48391639 3.36% 64.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30824264 2.14% 66.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 51186075 3.55% 70.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 123166257 8.55% 78.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 68161636 4.73% 83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 47264733 3.28% 86.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36668750 2.55% 89.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 152556099 10.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1454140777 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 353801341 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35355.537721 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35450.495050 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 353800095 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44053000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 1439870042 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 355034186 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35334.265176 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35459.890110 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355032934 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 44238500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1246 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32224500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1252 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 342 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32268500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 389219.026403 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 390146.081319 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 353801341 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35355.537721 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
system.cpu.icache.demand_hits 353800095 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44053000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 355034186 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35334.265176 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency
system.cpu.icache.demand_hits 355032934 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 44238500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1246 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32224500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1252 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 342 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32268500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.349132 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 715.022199 # Average occupied blocks per context
system.cpu.icache.overall_accesses 353801341 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35355.537721 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.349698 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 716.180731 # Average occupied blocks per context
system.cpu.icache.overall_accesses 355034186 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35334.265176 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 353800095 # number of overall hits
system.cpu.icache.overall_miss_latency 44053000 # number of overall miss cycles
system.cpu.icache.overall_hits 355032934 # number of overall hits
system.cpu.icache.overall_miss_latency 44238500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1246 # number of overall misses
system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32224500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1252 # number of overall misses
system.cpu.icache.overall_mshr_hits 342 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32268500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 715.022199 # Cycle average of tags in use
system.cpu.icache.total_refs 353800095 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 716.180731 # Cycle average of tags in use
system.cpu.icache.total_refs 355032934 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 11703954 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 281582966 # Number of branches executed
system.cpu.iew.EXEC:nop 129524501 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.553744 # Inst execution rate
system.cpu.iew.EXEC:refs 770699454 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 202312987 # Number of stores executed
system.cpu.idleCycles 11330087 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 280332781 # Number of branches executed
system.cpu.iew.EXEC:nop 129121920 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.560467 # Inst execution rate
system.cpu.iew.EXEC:refs 767231280 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 200922716 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1532271545 # num instructions consuming a value
system.cpu.iew.WB:count 2239351820 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811403 # average fanout of values written-back
system.cpu.iew.WB:consumers 1522686548 # num instructions consuming a value
system.cpu.iew.WB:count 2225893734 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811633 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1243290213 # num instructions producing a value
system.cpu.iew.WB:rate 1.527687 # insts written-back per cycle
system.cpu.iew.WB:sent 2260914368 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21706879 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 16198055 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 619677157 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 21613314 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 233108974 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2613111960 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 568386467 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37669869 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2277546807 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 471616 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1235862105 # num instructions producing a value
system.cpu.iew.WB:rate 1.533830 # insts written-back per cycle
system.cpu.iew.WB:sent 2246790117 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21706516 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 15735224 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 619699188 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 21567119 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 233370796 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2608680423 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 566308564 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37529963 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2264549792 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 297607 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 28495 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 91814713 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 777432 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 27486 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 89450574 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 675659 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 285764 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 36261369 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 212351 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 161623 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 33872925 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 214320 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 2343036 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 174010796 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 72203992 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2343036 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3386842 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18320037 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.184330 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.184330 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 2995791 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 17 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 174032827 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 72465814 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2995791 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3378494 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18328022 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.196281 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.196281 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1530874605 66.12% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 578961528 25.01% 91.13% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 205380015 8.87% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1521321100 66.08% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 232 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 576616052 25.05% 91.13% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 204142076 8.87% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2315216676 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 13456867 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005812 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 2302079755 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12945104 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005623 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2756939 20.49% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.49% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 8882759 66.01% 86.50% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1817169 13.50% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 2890284 22.33% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 22.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 8361572 64.59% 86.92% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1693248 13.08% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1454140777 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.592154 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.762923 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1439870042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.598811 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.750982 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 566783737 38.98% 38.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 267408405 18.39% 57.37% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 245316156 16.87% 74.24% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 135509048 9.32% 83.56% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 112013237 7.70% 91.26% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 72675996 5.00% 96.26% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 44106984 3.03% 99.29% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 8043729 0.55% 99.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2283485 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 553825571 38.46% 38.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 266666629 18.52% 56.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 241255351 16.76% 73.74% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 143700504 9.98% 83.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 114580764 7.96% 91.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 70398755 4.89% 96.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 36702113 2.55% 99.12% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10651437 0.74% 99.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 2088918 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1454140777 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.579442 # Inst issue rate
system.cpu.iq.iqInstsAdded 2483587414 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2315216676 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 728311196 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1117432 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 316872766 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 1439870042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.586328 # Inst issue rate
system.cpu.iq.iqInstsAdded 2479558460 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2302079755 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 726499267 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 996261 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 330157127 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 353801377 # ITB accesses
system.cpu.itb.fetch_accesses 355034219 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 353801341 # ITB hits
system.cpu.itb.fetch_misses 36 # ITB misses
system.cpu.itb.fetch_hits 355034186 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -353,107 +351,98 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1884690 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.794335 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31398.574681 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 174907 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 59072651008 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.907196 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1709783 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53684749213 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.907196 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1709783 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277298 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34312.855500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31137.095153 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5437284 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 63136134500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.252843 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1840014 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 57292691000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252843 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1840014 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 114023 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34289.699008 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31224.543680 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 3909814350 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 114023 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3560316144 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 114023 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2367711 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2367711 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11849.162556 # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_accesses 1884821 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34451.716970 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31263.065922 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 1001550 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 30430202500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.468623 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27613759500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468623 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7277260 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34300.261562 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.501409 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5456659 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 62447090500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250177 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1820601 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685325000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250177 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1820601 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3077872 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3077872 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10336.866902 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.526283 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 27449 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 2.807813 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 1698 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 325247663 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 17552000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9161988 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34426.978644 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5612191 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 122208785508 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.387448 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3549797 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 9162081 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34349.737340 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6458209 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 92877293000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.295115 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2703872 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 110977440213 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.387448 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3549797 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 84299084500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.295115 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2703872 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.481343 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.322273 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15772.655639 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10560.226030 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9161988 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34426.978644 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.038482 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.484528 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.327269 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15877.018497 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10723.955560 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9162081 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34349.737340 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5612191 # number of overall hits
system.cpu.l2cache.overall_miss_latency 122208785508 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.387448 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3549797 # number of overall misses
system.cpu.l2cache.overall_hits 6458209 # number of overall hits
system.cpu.l2cache.overall_miss_latency 92877293000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.295115 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2703872 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 110977440213 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.387448 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3549797 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 84299084500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.295115 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2703872 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2708907 # number of replacements
system.cpu.l2cache.sampled_refs 2733538 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2693288 # number of replacements
system.cpu.l2cache.sampled_refs 2717930 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26332.881669 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6905691 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 152081139500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1176798 # number of writebacks
system.cpu.memDep0.conflictingLoads 124506463 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 62743482 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 619677157 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 233108974 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1465844731 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 63989148 # Number of cycles rename is blocking
system.cpu.l2cache.tagsinuse 26600.974057 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7631439 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 148178401500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1171803 # number of writebacks
system.cpu.memDep0.conflictingLoads 134698193 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 69978801 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 619699188 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 233370796 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1451200129 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 52056982 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5522165 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 740664434 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 19930963 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1000685 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3545348406 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2741098331 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2053584906 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 528288951 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 91814713 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 29382701 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 677381943 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 830 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:IQFullEvents 6212885 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 741942603 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 18353930 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 492222 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3542299573 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2739870490 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2052189295 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 529159748 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 89450574 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 27259412 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 675986332 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 723 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 59537135 # count of insts added to the skid buffer
system.cpu.rename.RENAME:skidInsts 54988572 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
system.cpu.timesIdled 436319 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.timesIdled 434261 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

12
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:06:37
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:33:53
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +28,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2705279137000 because target called exit()
Exiting @ tick 2663443716000 because target called exit()

183
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1235575 # Simulator instruction rate (inst/s)
host_mem_usage 206704 # Number of bytes of host memory used
host_seconds 1472.82 # Real time elapsed on the host
host_tick_rate 1836801554 # Simulator tick rate (ticks/s)
host_inst_rate 1370976 # Simulator instruction rate (inst/s)
host_mem_usage 192892 # Number of bytes of host memory used
host_seconds 1327.36 # Real time elapsed on the host
host_tick_rate 2006569980 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.705279 # Number of seconds simulated
sim_ticks 2705279137000 # Number of ticks simulated
sim_seconds 2.663444 # Number of seconds simulated
sim_ticks 2663443716000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.995973 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 596101072 # number of overall hits
system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9223093 # number of overall misses
system.cpu.dcache.overall_hits 596212431 # number of overall hits
system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9111734 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2365949 # number of writebacks
system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3058802 # number of writebacks
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 605324165 # DTB hits
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 802 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.299002 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use
system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,37 +164,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.515193 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5565183 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 184462356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.389283 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3547353 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 141894120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3547353 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.466649 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.320836 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15291.153152 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.467301 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.327380 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5565183 # number of overall hits
system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.389283 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3547353 # number of overall misses
system.cpu.l2cache.overall_hits 6415439 # number of overall hits
system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2697097 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3547353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2701645 # number of replacements
system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2686269 # number of replacements
system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1175830 # number of writebacks
system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1170923 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5410558274 # number of cpu cycles simulated
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls

2
tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

12
tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 14:05:19
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:06:16
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -31,4 +29,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2473217439000 because target called exit()
Exiting @ tick 2431420115000 because target called exit()

183
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1470110 # Simulator instruction rate (inst/s)
host_mem_usage 211484 # Number of bytes of host memory used
host_seconds 1158.83 # Real time elapsed on the host
host_tick_rate 2134239180 # Simulator tick rate (ticks/s)
host_inst_rate 1373516 # Simulator instruction rate (inst/s)
host_mem_usage 197324 # Number of bytes of host memory used
host_seconds 1240.32 # Real time elapsed on the host
host_tick_rate 1960310324 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1703605163 # Number of instructions simulated
sim_seconds 2.473217 # Number of seconds simulated
sim_ticks 2473217439000 # Number of ticks simulated
sim_seconds 2.431420 # Number of seconds simulated
sim_ticks 2431420115000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24630.043664 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21630.043664 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24514.094748 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.094748 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 177979060000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 177141202000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 156300772000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 155462914000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 52467.599202 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49467.599202 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 170586898 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 104893749000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011584 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1999210 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 98896119000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011584 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1999210 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 170696959 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 58156775000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889149 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30662.702029 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency
system.cpu.dcache.demand_hits 645745050 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 282872809000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.014085 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9225306 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 26435.430315 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23435.430315 # average overall mshr miss latency
system.cpu.dcache.demand_hits 645855111 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 240965424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9115245 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 255196891000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.014085 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9225306 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 213619689000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.013917 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9115245 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997054 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4083.932190 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.997003 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4083.724785 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30662.702029 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 27662.702029 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 26435.430315 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23435.430315 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 645745050 # number of overall hits
system.cpu.dcache.overall_miss_latency 282872809000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.014085 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9225306 # number of overall misses
system.cpu.dcache.overall_hits 645855111 # number of overall hits
system.cpu.dcache.overall_miss_latency 240965424000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9115245 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 255196891000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.014085 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9225306 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 213619689000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.013917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9115245 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9111149 # number of replacements
system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4083.932190 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4083.724785 # Cycle average of tags in use
system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 25923011000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2365751 # number of writebacks
system.cpu.dcache.warmup_cycle 25922969000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3061986 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 638 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.251186 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 514.428387 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.251403 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 514.872908 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 514.428387 # Cycle average of tags in use
system.cpu.icache.tagsinuse 514.872908 # Cycle average of tags in use
system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 168141 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89492416000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.910996 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1721008 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68840320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910996 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1721008 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 999241 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 46275216000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.471063 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 889908 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35596320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471063 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 889908 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5397220 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 95134728000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.253159 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1829514 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 73180560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.253159 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1829514 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 110061 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51957.950591 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 5718544000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 110061 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4402440000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 110061 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2365751 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2365751 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 5417169 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 94097380000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.250399 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1809565 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 72382600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250399 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1809565 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3061986 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3061986 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.511929 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.788539 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 9115883 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5565361 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 184627144000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.389487 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3550522 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 6416410 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 140372596000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.296129 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2699473 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 142020880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.389487 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3550522 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 107978920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.296129 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2699473 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.457042 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.333046 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 14976.359071 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10913.242343 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.458608 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.338955 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15027.674424 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11106.876723 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9115883 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5565361 # number of overall hits
system.cpu.l2cache.overall_miss_latency 184627144000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.389487 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3550522 # number of overall misses
system.cpu.l2cache.overall_hits 6416410 # number of overall hits
system.cpu.l2cache.overall_miss_latency 140372596000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.296129 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2699473 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 142020880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.389487 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3550522 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 107978920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.296129 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2699473 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2702712 # number of replacements
system.cpu.l2cache.sampled_refs 2729930 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2687070 # number of replacements
system.cpu.l2cache.sampled_refs 2714388 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25889.601414 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6857391 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 555158623000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1177576 # number of writebacks
system.cpu.l2cache.tagsinuse 26134.551147 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7569176 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 538044067000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1171981 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4946434878 # number of cpu cycles simulated
system.cpu.numCycles 4862840230 # number of cpu cycles simulated
system.cpu.num_insts 1703605163 # Number of instructions executed
system.cpu.num_refs 660773876 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls

2
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

12
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:20:12
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:20:23
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:23:28
M5 executing on phenom
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -31,4 +29,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 5965358694000 because target called exit()
Exiting @ tick 5923548078000 because target called exit()

183
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 828534 # Simulator instruction rate (inst/s)
host_mem_usage 210088 # Number of bytes of host memory used
host_seconds 5616.34 # Real time elapsed on the host
host_tick_rate 1062144168 # Simulator tick rate (ticks/s)
host_inst_rate 1201976 # Simulator instruction rate (inst/s)
host_mem_usage 195452 # Number of bytes of host memory used
host_seconds 3871.40 # Real time elapsed on the host
host_tick_rate 1530079593 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653327945 # Number of instructions simulated
sim_seconds 5.965359 # Number of seconds simulated
sim_ticks 5965358694000 # Number of ticks simulated
sim_seconds 5.923548 # Number of seconds simulated
sim_ticks 5923548078000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24735.540403 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21735.540403 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 178661098000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 156992548000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 52475.088886 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49475.088886 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 436528587 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 104937059000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004560 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1999750 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 98937809000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1999750 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30750.347733 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 27750.347733 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1668490486 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 283598157000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005497 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9222600 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 255930357000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005497 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9222600 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997251 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4084.741632 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.997232 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30750.347733 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 27750.347733 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1668490486 # number of overall hits
system.cpu.dcache.overall_miss_latency 283598157000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005497 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9222600 # number of overall misses
system.cpu.dcache.overall_hits 1668600409 # number of overall hits
system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9112677 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 255930357000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005497 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9222600 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4084.741632 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58862918000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2365669 # number of writebacks
system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 3053391 # number of writebacks
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 675 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.271287 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 555.595041 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.271344 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 555.595041 # Cycle average of tags in use
system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -132,37 +132,28 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 167830 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89543844000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.911193 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1721997 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68879880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911193 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1721997 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5376631 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 96038488000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.255678 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1846894 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 73875760000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.255678 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1846894 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 109923 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51961.682268 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 5711784000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 109923 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4396920000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 109923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2365669 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2365669 # number of Writeback hits
system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.486980 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5544461 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 185582332000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.391611 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3568891 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 142755640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.391611 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3568891 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.472057 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.330298 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15468.376741 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10823.217602 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.472376 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.336564 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5544461 # number of overall hits
system.cpu.l2cache.overall_miss_latency 185582332000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.391611 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3568891 # number of overall misses
system.cpu.l2cache.overall_hits 6396007 # number of overall hits
system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2717345 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 142755640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.391611 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3568891 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 2721965 # number of replacements
system.cpu.l2cache.sampled_refs 2748168 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2706631 # number of replacements
system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26291.594343 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6834640 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1346606710000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1180493 # number of writebacks
system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1174631 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 11930717388 # number of cpu cycles simulated
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
system.cpu.num_insts 4653327945 # Number of instructions executed
system.cpu.num_refs 1677713086 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls

2
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -191,7 +191,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

13
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:18:42
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:52:34
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 98337080000 because target called exit()
122 123 124 Exiting @ tick 98335161000 because target called exit()

256
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 33745 # Simulator instruction rate (inst/s)
host_mem_usage 211108 # Number of bytes of host memory used
host_seconds 2723.45 # Real time elapsed on the host
host_tick_rate 36107563 # Simulator tick rate (ticks/s)
host_inst_rate 54763 # Simulator instruction rate (inst/s)
host_mem_usage 197304 # Number of bytes of host memory used
host_seconds 1678.20 # Real time elapsed on the host
host_tick_rate 58595727 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.098337 # Number of seconds simulated
sim_ticks 98337080000 # Number of ticks simulated
sim_seconds 0.098335 # Number of seconds simulated
sim_ticks 98335161000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits
@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064
system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed
system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileAccesses 185972268 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 95.460360 # Percentage of cycles cpu is active
system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 95.462227 # Percentage of cycles cpu is active
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.comInts 43625545 # Number of Integer instructions committed
@ -42,28 +42,28 @@ system.cpu.comStores 6502695 # Nu
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads
system.cpu.cpi 2.139976 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total 2.139976 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48524.210526 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 23049000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 55595.537757 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52592.105263 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 97181000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 91931000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 54730.994152 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 121667000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 114980000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.352016 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1441.857733 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54730.994152 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26495062 # number of overall hits
system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles
system.cpu.dcache.overall_hits 26495078 # number of overall hits
system.cpu.dcache.overall_miss_latency 121667000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2239 # number of overall misses
system.cpu.dcache.overall_misses 2223 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 114980000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1441.857733 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 26497301 # DTB hits
@ -126,50 +126,50 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_avg_miss_latency 27216.197508 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.134662 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 101754083 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 235910000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 205719500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 8668 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 91 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 205720500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8577 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 2000 # average number of cycles each access was blocked
system.cpu.icache.avg_refs 11863.598578 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 11863.598344 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_avg_miss_latency 27216.197508 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency
system.cpu.icache.demand_hits 101754083 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 235910000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses
system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 205719500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 8668 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 91 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 205720500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8577 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.697636 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1428.759296 # Average occupied blocks per context
system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 27216.197508 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 101754085 # number of overall hits
system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles
system.cpu.icache.overall_hits 101754083 # number of overall hits
system.cpu.icache.overall_miss_latency 235910000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses
system.cpu.icache.overall_misses 8666 # number of overall misses
system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 205719500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 8668 # number of overall misses
system.cpu.icache.overall_mshr_hits 91 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 205720500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8577 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 6743 # number of replacements
system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use
system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1428.759296 # Cycle average of tags in use
system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads
system.cpu.idleCycles 8924453 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@ -201,104 +201,96 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.318235 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.807201 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89916500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68890000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 52167.972576 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 159790500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 1.916906 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses
system.cpu.l2cache.demand_avg_miss_latency 52185.370951 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6015 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 249707000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.443056 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4785 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.445463 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 191471500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.443056 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4785 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context
system.cpu.l2cache.occ_%::0 0.063286 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2073.767582 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.791341 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 52185.370951 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5989 # number of overall hits
system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4811 # number of overall misses
system.cpu.l2cache.overall_hits 6015 # number of overall hits
system.cpu.l2cache.overall_miss_latency 249707000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.443056 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4785 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.445463 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 191471500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.443056 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4785 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3129 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2091.558923 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5998 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 196674161 # number of cpu cycles simulated
system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed.
system.cpu.numCycles 196670323 # number of cpu cycles simulated
system.cpu.runCycles 187745870 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.idleCycles 94907524 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed.
system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.utilization 51.742834 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles 104509809 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.utilization 46.860407 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 170133192 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.utilization 13.493206 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles 196670323 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -358,7 +358,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

13
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:11:51
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:34:48
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 40700936000 because target called exit()
122 123 124 Exiting @ tick 40701237000 because target called exit()

580
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,295 +1,295 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 126678 # Simulator instruction rate (inst/s)
host_mem_usage 211676 # Number of bytes of host memory used
host_seconds 664.52 # Real time elapsed on the host
host_tick_rate 61249065 # Simulator tick rate (ticks/s)
host_inst_rate 172806 # Simulator instruction rate (inst/s)
host_mem_usage 197872 # Number of bytes of host memory used
host_seconds 487.13 # Real time elapsed on the host
host_tick_rate 83552440 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040701 # Number of seconds simulated
sim_ticks 40700936000 # Number of ticks simulated
sim_ticks 40701237000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 11915731 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15874516 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 11915545 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15874334 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 1889856 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 14601933 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 19578482 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 1889899 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 14602096 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 19578655 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 10240685 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 2865019 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 2864912 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 73200115 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.255504 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.951469 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 73200571 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.255496 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.951465 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 35882998 49.02% 49.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 18421131 25.17% 74.19% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 7399939 10.11% 84.30% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3793003 5.18% 89.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2033143 2.78% 92.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1324637 1.81% 94.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 734587 1.00% 95.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 745658 1.02% 96.09% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2865019 3.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 35883667 49.02% 49.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 18420857 25.16% 74.19% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 7399798 10.11% 84.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 3793136 5.18% 89.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2033346 2.78% 92.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 1324316 1.81% 94.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 734839 1.00% 95.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 745700 1.02% 96.09% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2864912 3.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 73200115 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 73200571 # Number of insts commited each cycle
system.cpu.commit.COM:count 91903055 # Number of instructions committed
system.cpu.commit.COM:loads 20034413 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1876719 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 1876760 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 56257070 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 56257975 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.967001 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.967001 # CPI: Total CPI of All Threads
system.cpu.cpi 0.967008 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.967008 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23361768 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30148.648649 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32165.686275 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23360880 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 26772000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses 23361980 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 30151.634724 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32163.725490 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23361093 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 26744500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 888 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 16404500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 887 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 377 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 16403500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 35665.614165 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35983.686319 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493027 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 288035500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001242 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 8076 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6329 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 62863500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1747 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 35569.269207 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35483.256351 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493098 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 284732000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001231 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 8005 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6273 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 61457000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13315.768510 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 13315.879572 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 29862871 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35119.087461 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29853907 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 314807500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000300 # miss rate for demand accesses
system.cpu.dcache.demand_misses 8964 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6707 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 79268000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2257 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 29863083 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35028.846154 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29854191 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 311476500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
system.cpu.dcache.demand_misses 8892 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6650 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 77860500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.356506 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1460.250343 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 29862871 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35119.087461 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.356508 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1460.254824 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 29863083 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35028.846154 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29853907 # number of overall hits
system.cpu.dcache.overall_miss_latency 314807500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000300 # miss rate for overall accesses
system.cpu.dcache.overall_misses 8964 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6707 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 79268000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2257 # number of overall MSHR misses
system.cpu.dcache.overall_hits 29854191 # number of overall hits
system.cpu.dcache.overall_miss_latency 311476500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
system.cpu.dcache.overall_misses 8892 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6650 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 77860500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 160 # number of replacements
system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1460.250343 # Cycle average of tags in use
system.cpu.dcache.total_refs 29853953 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1460.254824 # Cycle average of tags in use
system.cpu.dcache.total_refs 29854202 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 4195548 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 13275 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3138319 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162326104 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39347421 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29437279 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8092915 # Number of cycles decode is squashing
system.cpu.dcache.writebacks 109 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 4195761 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 13279 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3138343 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162326891 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39347906 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29437041 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8093015 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 219867 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 31798312 # DTB accesses
system.cpu.decode.DECODE:UnblockCycles 219863 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 31798533 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 31419824 # DTB hits
system.cpu.dtb.data_misses 378488 # DTB misses
system.cpu.dtb.data_hits 31420024 # DTB hits
system.cpu.dtb.data_misses 378509 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 24587008 # DTB read accesses
system.cpu.dtb.read_accesses 24587243 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 24209579 # DTB read hits
system.cpu.dtb.read_misses 377429 # DTB read misses
system.cpu.dtb.write_accesses 7211304 # DTB write accesses
system.cpu.dtb.read_hits 24209793 # DTB read hits
system.cpu.dtb.read_misses 377450 # DTB read misses
system.cpu.dtb.write_accesses 7211290 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 7210245 # DTB write hits
system.cpu.dtb.write_hits 7210231 # DTB write hits
system.cpu.dtb.write_misses 1059 # DTB write misses
system.cpu.fetch.Branches 19578482 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19042269 # Number of cache lines fetched
system.cpu.fetch.Cycles 49581999 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 482446 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167417229 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2029251 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240516 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19042269 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13652580 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.056675 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 81293030 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.059429 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.087442 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.Branches 19578655 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19042384 # Number of cache lines fetched
system.cpu.fetch.Cycles 49581925 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 482421 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167418269 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2029286 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240517 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19042384 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13652394 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.056673 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 81293586 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.059428 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.087450 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 50753371 62.43% 62.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3139837 3.86% 66.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1896166 2.33% 68.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3230989 3.97% 72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4381492 5.39% 77.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1498123 1.84% 79.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1855484 2.28% 82.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1657938 2.04% 84.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 12879630 15.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 50754116 62.43% 62.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3139628 3.86% 66.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1895979 2.33% 68.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3231029 3.97% 72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4381369 5.39% 77.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1498108 1.84% 79.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1855702 2.28% 82.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1657872 2.04% 84.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 12879783 15.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 81293030 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 19042269 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15754.189443 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11879.245840 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19031110 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 175801000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 81293586 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 19042384 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15742.896836 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11872.070120 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19031227 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 175643500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 11159 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1002 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120657500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 11157 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120549000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10157 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 10154 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1873.694004 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1874.259110 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 19042269 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15754.189443 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency
system.cpu.icache.demand_hits 19031110 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 175801000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 19042384 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15742.896836 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency
system.cpu.icache.demand_hits 19031227 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 175643500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses
system.cpu.icache.demand_misses 11159 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1002 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120657500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 11157 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120549000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10157 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 10154 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.756087 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1548.466977 # Average occupied blocks per context
system.cpu.icache.overall_accesses 19042269 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15754.189443 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.756089 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1548.470149 # Average occupied blocks per context
system.cpu.icache.overall_accesses 19042384 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15742.896836 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 19031110 # number of overall hits
system.cpu.icache.overall_miss_latency 175801000 # number of overall miss cycles
system.cpu.icache.overall_hits 19031227 # number of overall hits
system.cpu.icache.overall_miss_latency 175643500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses
system.cpu.icache.overall_misses 11159 # number of overall misses
system.cpu.icache.overall_mshr_hits 1002 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120657500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 11157 # number of overall misses
system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120549000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10157 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 10154 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 8241 # number of replacements
system.cpu.icache.sampled_refs 10157 # Sample count of references to valid blocks.
system.cpu.icache.replacements 8238 # number of replacements
system.cpu.icache.sampled_refs 10154 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1548.466977 # Cycle average of tags in use
system.cpu.icache.total_refs 19031110 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1548.470149 # Cycle average of tags in use
system.cpu.icache.total_refs 19031227 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 108843 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12932923 # Number of branches executed
system.cpu.iew.EXEC:nop 12752202 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.252024 # Inst execution rate
system.cpu.iew.EXEC:refs 31851727 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7212953 # Number of stores executed
system.cpu.idleCycles 108889 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12932789 # Number of branches executed
system.cpu.iew.EXEC:nop 12752151 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.252018 # Inst execution rate
system.cpu.iew.EXEC:refs 31851951 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7212939 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 91350917 # num instructions consuming a value
system.cpu.iew.WB:count 100121723 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.722506 # average fanout of values written-back
system.cpu.iew.WB:consumers 91351431 # num instructions consuming a value
system.cpu.iew.WB:count 100121785 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.722504 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 66001625 # num instructions producing a value
system.cpu.iew.WB:rate 1.229968 # insts written-back per cycle
system.cpu.iew.WB:sent 100959925 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2058548 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 308035 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33906352 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 439 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1495689 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10659868 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 148158966 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24638774 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2167496 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101917138 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 147063 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 66001783 # num instructions producing a value
system.cpu.iew.WB:rate 1.229960 # insts written-back per cycle
system.cpu.iew.WB:sent 100960101 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2058583 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 308073 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33906754 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1495766 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10659940 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 148159865 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24639012 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2167407 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101917357 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 147057 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8092915 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 184741 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 229 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8093015 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 184742 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 837967 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2533 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 837974 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2531 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 262394 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9832 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13871939 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4157173 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 262394 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 456488 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1602060 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.034125 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.034125 # IPC: Total IPC of All Threads
system.cpu.iew.lsq.thread.0.memOrderViolation 262379 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9827 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13872341 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4157245 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 262379 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 456408 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1602175 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.034117 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.034117 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580885 62.05% 62.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 474250 0.46% 62.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580956 62.05% 62.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 474234 0.46% 62.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786793 2.68% 65.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786797 2.68% 65.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387015 2.29% 67.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387018 2.29% 67.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 25334190 24.34% 92.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346496 7.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 25334340 24.34% 92.94% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346414 7.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 104084634 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1605159 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.015422 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 104084764 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1605421 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.015424 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 233517 14.55% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 233590 14.55% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available
@ -298,42 +298,42 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # at
system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 750460 46.75% 95.23% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 76517 4.77% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 750644 46.76% 95.23% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 76522 4.77% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 81293030 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280364 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539599 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 81293586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280356 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539590 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 34992329 43.04% 43.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 18915944 23.27% 66.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 11753054 14.46% 80.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6613669 8.14% 88.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 5112903 6.29% 95.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2406334 2.96% 98.16% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1201307 1.48% 99.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 249469 0.31% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 48021 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 34992440 43.04% 43.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 18916491 23.27% 66.31% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 11753286 14.46% 80.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6613191 8.13% 88.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 5113111 6.29% 95.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2406044 2.96% 98.16% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1201508 1.48% 99.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 249704 0.31% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 47811 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 81293030 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.278652 # Inst issue rate
system.cpu.iq.iqInstsAdded 135406325 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 104084634 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 439 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50573904 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 302099 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47258027 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::total 81293586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.278644 # Inst issue rate
system.cpu.iq.iqInstsAdded 135407278 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 104084764 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50574577 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 302079 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47259225 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 19042340 # ITB accesses
system.cpu.itb.fetch_accesses 19042455 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 19042269 # ITB hits
system.cpu.itb.fetch_hits 19042384 # ITB hits
system.cpu.itb.fetch_misses 71 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -344,103 +344,95 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34688.510393 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31520.207852 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 60080500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1732 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 54593000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1732 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10667 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34283.465725 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.788761 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34699.413490 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31528.152493 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 59162500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.984411 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1705 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53755500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10664 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34281.213192 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.566549 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 116529500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.318646 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3399 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105647000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318646 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3399 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34166.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 512500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 465000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
system.cpu.l2cache.ReadReq_miss_latency 116419000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.318455 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3396 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105553000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318455 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3396 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.094427 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.100462 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12399 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34420.190996 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7268 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 176610000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.413824 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5131 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 12396 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34420.995883 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7295 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 175581500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.411504 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5101 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 160240000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.413824 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5131 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 159308500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.411504 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000413 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2302.538330 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13.547355 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 12399 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34420.190996 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency
system.cpu.l2cache.occ_%::1 0.000537 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2302.534301 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.609654 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 12396 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34420.995883 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7268 # number of overall hits
system.cpu.l2cache.overall_miss_latency 176610000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.413824 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5131 # number of overall misses
system.cpu.l2cache.overall_hits 7295 # number of overall hits
system.cpu.l2cache.overall_miss_latency 175581500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.411504 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5101 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 160240000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.413824 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5131 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 159308500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.411504 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3463 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3464 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2316.085685 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7253 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2320.143954 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7276 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 17615087 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5052814 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 33906352 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10659868 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 81401873 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1958439 # Number of cycles rename is blocking
system.cpu.memDep0.conflictingLoads 17616969 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5053323 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 33906754 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10659940 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 81402475 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1958550 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1204670 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40603212 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 943778 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202469078 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157094553 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115390079 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28386104 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8092915 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2247194 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 46962718 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 5166 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 474 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4950472 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed
system.cpu.rename.RENAME:IQFullEvents 1204707 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40603552 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 943829 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202471233 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157096154 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115391431 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28385991 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8093015 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2247276 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 46964070 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 5202 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 471 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4950569 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 460 # count of temporary serializing insts renamed
system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls

2
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:58:58
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:04:52
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -30,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 118742021000 because target called exit()
122 123 124 Exiting @ tick 118740049000 because target called exit()

142
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1269659 # Simulator instruction rate (inst/s)
host_mem_usage 210612 # Number of bytes of host memory used
host_seconds 72.38 # Real time elapsed on the host
host_tick_rate 1640438984 # Simulator tick rate (ticks/s)
host_inst_rate 1097596 # Simulator instruction rate (inst/s)
host_mem_usage 196804 # Number of bytes of host memory used
host_seconds 83.73 # Real time elapsed on the host
host_tick_rate 1418103765 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118742 # Number of seconds simulated
sim_ticks 118742021000 # Number of ticks simulated
sim_seconds 0.118740 # Number of seconds simulated
sim_ticks 118740049000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 #
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 98784000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 93492000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55005.806163 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 123158000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 116441000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.352059 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1442.035674 # Average occupied blocks per context
system.cpu.dcache.occ_%::0 0.352058 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55005.806163 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26495062 # number of overall hits
system.cpu.dcache.overall_miss_latency 123158000 # number of overall miss cycles
system.cpu.dcache.overall_hits 26495078 # number of overall hits
system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2239 # number of overall misses
system.cpu.dcache.overall_misses 2223 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 116441000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1442.035674 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 26497301 # DTB hits
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 8510 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.692403 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1418.041181 # Average occupied blocks per context
system.cpu.icache.occ_%::0 0.692401 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1418.041181 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -164,12 +164,13 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
@ -180,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses 3043 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 832000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 640000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.909179 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2056.260143 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13.724287 # Average occupied blocks per context
system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5942 # number of overall hits
system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4791 # number of overall misses
system.cpu.l2cache.overall_hits 5968 # number of overall hits
system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4765 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3105 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2069.984431 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 237484042 # number of cpu cycles simulated
system.cpu.numCycles 237480098 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls

2
tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/arm/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:52:30
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:54:23
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:05:16
M5 executing on phenom
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -30,4 +26,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 232028062000 because target called exit()
122 123 124 Exiting @ tick 232027671000 because target called exit()

126
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1713926 # Simulator instruction rate (inst/s)
host_mem_usage 214560 # Number of bytes of host memory used
host_seconds 108.72 # Real time elapsed on the host
host_tick_rate 2134224518 # Simulator tick rate (ticks/s)
host_inst_rate 1260082 # Simulator instruction rate (inst/s)
host_mem_usage 200384 # Number of bytes of host memory used
host_seconds 147.87 # Real time elapsed on the host
host_tick_rate 1569082964 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186333855 # Number of instructions simulated
sim_seconds 0.232028 # Number of seconds simulated
sim_ticks 232028062000 # Number of ticks simulated
sim_ticks 232027671000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency
@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 34134000 #
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 690 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 12385593 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 12385594 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 61264000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_misses 1100 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 57964000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1100 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks.
@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 54639.865997 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency
system.cpu.dcache.demand_hits 42025083 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 97860000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 54451.396648 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency
system.cpu.dcache.demand_hits 42025084 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 97468000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1791 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 1790 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 92487000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 92098000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1791 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 1790 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.333155 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1364.601520 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 1364.601667 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54639.865997 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 54451.396648 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51451.396648 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 42025083 # number of overall hits
system.cpu.dcache.overall_miss_latency 97860000 # number of overall miss cycles
system.cpu.dcache.overall_hits 42025084 # number of overall hits
system.cpu.dcache.overall_miss_latency 97468000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1791 # number of overall misses
system.cpu.dcache.overall_misses 1790 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 92487000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 92098000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1791 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 1790 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 40 # number of replacements
system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1364.601520 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1364.601667 # Cycle average of tags in use
system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 16 # number of writebacks
@ -115,7 +115,7 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.560536 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1147.977742 # Average occupied blocks per context
system.cpu.icache.occ_blocks::0 1147.977892 # Average occupied blocks per context
system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1506 # number of replacements
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1147.977742 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1147.977892 # Cycle average of tags in use
system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 57200000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1100 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 44000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1100 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 56784000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1092 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 43680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1092 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 3741 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
@ -166,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses 2361 # nu
system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 52000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 40000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.582348 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -188,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 4841 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1380 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179972000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.714935 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3461 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 1388 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179556000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.713282 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3453 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 138440000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.714935 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3461 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.713282 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.051044 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1672.604273 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2.043764 # Average occupied blocks per context
system.cpu.l2cache.occ_%::1 0.000093 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1672.604511 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3.037968 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1380 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179972000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.714935 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3461 # number of overall misses
system.cpu.l2cache.overall_hits 1388 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179556000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.713282 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3453 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 138440000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.714935 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3461 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.713282 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3453 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 2368 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 1674.648036 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 1675.642479 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 464056124 # number of cpu cycles simulated
system.cpu.numCycles 464055342 # number of cpu cycles simulated
system.cpu.num_insts 186333855 # Number of instructions executed
system.cpu.num_refs 42511846 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls

2
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
View file

@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 13:20:12
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 13:26:25
M5 executing on zizzer
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:26:56
M5 executing on phenom
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -31,4 +27,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 250960757000 because target called exit()
122 123 124 Exiting @ tick 250960631000 because target called exit()

95
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 935562 # Simulator instruction rate (inst/s)
host_mem_usage 217504 # Number of bytes of host memory used
host_seconds 234.54 # Real time elapsed on the host
host_tick_rate 1069990696 # Simulator tick rate (ticks/s)
host_inst_rate 1231791 # Simulator instruction rate (inst/s)
host_mem_usage 202836 # Number of bytes of host memory used
host_seconds 178.14 # Real time elapsed on the host
host_tick_rate 1408783027 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 219431024 # Number of instructions simulated
sim_seconds 0.250961 # Number of seconds simulated
sim_ticks 250960757000 # Number of ticks simulated
sim_ticks 250960631000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 #
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 88368000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 83634000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55846.719160 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 106388000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 100672500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1363.451646 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55846.719160 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 77195833 # number of overall hits
system.cpu.dcache.overall_miss_latency 106388000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1905 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 100672500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -69,7 +69,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 41 # number of replacements
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1363.451646 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 7 # number of writebacks
@ -106,7 +106,7 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1455.289171 # Average occupied blocks per context
system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 2836 # number of replacements
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1455.289171 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@ -132,12 +132,13 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 82056000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1578 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
@ -159,46 +160,46 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52003.271423 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1861 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 246391500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.717988 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4738 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 189520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.717988 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4738 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2058.146657 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 0.021757 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1861 # number of overall hits
system.cpu.l2cache.overall_miss_latency 246391500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.717988 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4738 # number of overall misses
system.cpu.l2cache.overall_hits 1864 # number of overall hits
system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4735 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 189520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.717988 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4738 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2058.168414 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 501921514 # number of cpu cycles simulated
system.cpu.numCycles 501921262 # number of cpu cycles simulated
system.cpu.num_insts 219431024 # Number of instructions executed
system.cpu.num_refs 77165306 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -8,12 +8,12 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/home/stever/m5/m5_system_2.0b3/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -265,7 +265,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@ -285,7 +285,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -411,7 +411,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]

Some files were not shown because too many files have changed in this diff Show more