13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
30 lines
1.3 KiB
Plaintext
Executable file
30 lines
1.3 KiB
Plaintext
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:49
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 15:04:52
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M5 executing on phenom
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
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Standard Cell Placement and Global Routing Program
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Authors: Carl Sechen, Bill Swartz
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Yale University
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61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
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76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
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91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
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106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
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122 123 124 Exiting @ tick 118740049000 because target called exit()
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