13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
16 lines
647 B
Text
Executable file
16 lines
647 B
Text
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:50
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 15:04:54
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M5 executing on phenom
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command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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Exiting @ tick 133078695000 because target called exit()
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