gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Steve Reinhardt 13a15c55a4 stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00

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M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 20 2010 15:04:50
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:17:04
M5 executing on phenom
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 118370500
Exiting @ tick 1900828642500 because m5_exit instruction encountered