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Stats: Update the statistics for rfe patch.

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This commit is contained in:
Ali Saidi 2011-03-17 19:20:20 -05:00
parent 031f396c71
commit 845f791f37
11 changed files with 139 additions and 139 deletions
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2
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -493,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 21 2011 14:34:16
M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
M5 started Feb 21 2011 14:34:24
M5 compiled Feb 22 2011 10:22:27
M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
M5 started Feb 22 2011 10:22:49
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

32
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 84615 # Simulator instruction rate (inst/s)
host_mem_usage 256696 # Number of bytes of host memory used
host_seconds 7097.77 # Real time elapsed on the host
host_tick_rate 30571310 # Simulator tick rate (ticks/s)
host_inst_rate 123576 # Simulator instruction rate (inst/s)
host_mem_usage 255024 # Number of bytes of host memory used
host_seconds 4860.01 # Real time elapsed on the host
host_tick_rate 44647688 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600581343 # Number of instructions simulated
sim_seconds 0.216988 # Number of seconds simulated
@ -119,9 +119,9 @@ system.cpu.dcache.tagsinuse 4094.932523 # Cy
system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394050 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 84141897 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 763381678 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 172755507 # Number of cycles decode is idle
system.cpu.decode.DECODE:BlockedCycles 84141899 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 763381679 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 172755505 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 145178933 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 17467706 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 13550939 # Number of cycles decode is unblocking
@ -165,8 +165,8 @@ system.cpu.fetch.rateDist::0 271374463 62.66% 62.66% # Nu
system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11465885 2.65% 81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12676536 2.93% 84.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total)
@ -492,22 +492,22 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.rename.RENAME:BlockCycles 12394449 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 63310870 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 190431449 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 190431447 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2146129409 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenameLookups 2146129408 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 749361548 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 579635255 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RenamedOperands 579635256 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 140764920 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 17467706 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 71980154 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 110388312 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:UndoneMaps 110388313 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2146129313 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 56304 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:int_rename_lookups 2146129312 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 56306 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 128598458 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
system.cpu.rename.RENAME:tempSerializingInsts 3954 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1130320351 # The number of ROB reads
system.cpu.rob.rob_writes 1461345715 # The number of ROB writes
system.cpu.timesIdled 36569 # Number of times that the entire CPU went into an idle state and unscheduled itself

4
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -493,9 +493,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

10
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 21 2011 14:34:16
M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
M5 started Feb 21 2011 15:43:32
M5 compiled Feb 22 2011 10:22:27
M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
M5 started Feb 22 2011 10:22:49
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -72,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 365986074500 because target called exit()
Exiting @ tick 365986112500 because target called exit()

150
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,29 +1,29 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 77433 # Simulator instruction rate (inst/s)
host_mem_usage 260740 # Number of bytes of host memory used
host_seconds 7232.86 # Real time elapsed on the host
host_tick_rate 50600448 # Simulator tick rate (ticks/s)
host_inst_rate 97202 # Simulator instruction rate (inst/s)
host_mem_usage 259080 # Number of bytes of host memory used
host_seconds 5761.84 # Real time elapsed on the host
host_tick_rate 63518944 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 560059971 # Number of instructions simulated
sim_seconds 0.365986 # Number of seconds simulated
sim_ticks 365986074500 # Number of ticks simulated
sim_ticks 365986112500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 140387936 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 174401300 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 140387928 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 174400171 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 15511612 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 191766015 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 191766015 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 191749151 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 191749151 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 110089780 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3558142 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 662070266 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 662070279 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.847952 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.257926 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 343782937 51.93% 51.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 343782950 51.93% 51.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 194895590 29.44% 81.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 65587700 9.91% 91.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 25120372 3.79% 95.06% # Number of insts commited each cycle
@ -35,7 +35,7 @@ system.cpu.commit.COM:committed_per_cycle::8 3558142 0.54% 100.00%
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 662070266 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 662070279 # Number of insts commited each cycle
system.cpu.commit.COM:count 561403855 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
@ -97,7 +97,7 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.992547 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4065.472807 # Average occupied blocks per context
system.cpu.dcache.occ_blocks::0 4065.472811 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 205633216 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12753.485870 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8794.286111 # average overall mshr miss latency
@ -115,13 +115,13 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 1169307 # number of replacements
system.cpu.dcache.sampled_refs 1173403 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4065.472807 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4065.472811 # Cycle average of tags in use
system.cpu.dcache.total_refs 203333005 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6053772000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1049504 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 23915687 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1082602718 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 296214320 # Number of cycles decode is idle
system.cpu.decode.DECODE:IdleCycles 296214333 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 338871926 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 65446321 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 3068332 # Number of cycles decode is unblocking
@ -146,23 +146,23 @@ system.cpu.dtb.read_misses 0 # DT
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 191766015 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 122748340 # Number of cache lines fetched
system.cpu.fetch.Cycles 351971872 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 3710699 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Branches 191749151 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 122693966 # Number of cache lines fetched
system.cpu.fetch.Cycles 352026246 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 3656325 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 938893733 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 4527385 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 26711690 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.261985 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 122748340 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 140387936 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.282691 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 727516586 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.537241 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.455426 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.261962 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 122693966 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 140387928 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.282690 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 727516599 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.537316 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.455394 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 376259318 51.72% 51.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 167730540 23.06% 74.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 376204957 51.71% 51.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 167784914 23.06% 74.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28515235 3.92% 78.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34553707 4.75% 83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26720758 3.67% 87.12% # Number of instructions fetched each cycle (Total)
@ -173,53 +173,53 @@ system.cpu.fetch.rateDist::8 60208180 8.28% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 727516586 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 727516599 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 122748340 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13369.913613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.346455 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 122731555 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 224414000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses 122693966 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13369.943402 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.377996 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 122677181 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 224414500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 16785 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 933 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 153437000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 153437500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 15852 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 7742.827266 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 7739.396947 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 122748340 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13369.913613 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency
system.cpu.icache.demand_hits 122731555 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 224414000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 122693966 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13369.943402 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 9679.377996 # average overall mshr miss latency
system.cpu.icache.demand_hits 122677181 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 224414500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses
system.cpu.icache.demand_misses 16785 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 933 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 153437000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 153437500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 15852 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.543111 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1112.290548 # Average occupied blocks per context
system.cpu.icache.overall_accesses 122748340 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13369.913613 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.543041 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1112.147272 # Average occupied blocks per context
system.cpu.icache.overall_accesses 122693966 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13369.943402 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 9679.377996 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 122731555 # number of overall hits
system.cpu.icache.overall_miss_latency 224414000 # number of overall miss cycles
system.cpu.icache.overall_hits 122677181 # number of overall hits
system.cpu.icache.overall_miss_latency 224414500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses
system.cpu.icache.overall_misses 16785 # number of overall misses
system.cpu.icache.overall_mshr_hits 933 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 153437000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 153437500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 15852 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -227,11 +227,11 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 14002 # number of replacements
system.cpu.icache.sampled_refs 15851 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1112.290548 # Cycle average of tags in use
system.cpu.icache.total_refs 122731555 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1112.147272 # Cycle average of tags in use
system.cpu.icache.total_refs 122677181 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 4455564 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 4455627 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 125457274 # Number of branches executed
system.cpu.iew.EXEC:nop 13838185 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.981178 # Inst execution rate
@ -349,11 +349,11 @@ system.cpu.iq.ISSUE:fu_full::MemRead 5982996 51.74% 53.07% # at
system.cpu.iq.ISSUE:fu_full::MemWrite 5427500 46.93% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 727516586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 727516599 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.031184 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.359043 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 340760839 46.84% 46.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 340760852 46.84% 46.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 195196887 26.83% 73.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 103112393 14.17% 87.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 43508042 5.98% 93.82% # Number of insts issued each cycle
@ -365,14 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::8 1771379 0.24% 100.00% # Nu
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 727516586 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 727516599 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.024907 # Inst issue rate
system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 761767408 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 2247505915 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 2247505928 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 665966032 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 1323699335 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 946810264 # Number of instructions added to the IQ (excludes non-spec)
@ -414,10 +414,10 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705469500
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343563 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 119513 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 841391 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34185.632593 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 34185.636939 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.780138 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 726325 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3933604000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 3933604500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.136757 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 115066 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits
@ -437,10 +437,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1189254 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34217.201881 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 34217.204012 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 954675 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 8026637000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 8026637500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.197249 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 234579 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits
@ -452,14 +452,14 @@ system.cpu.l2cache.mshr_cap_events 0 # nu
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.185910 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.449873 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6091.890422 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14741.450627 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::0 6091.910767 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14741.440748 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1189254 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34217.201881 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34217.204012 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 954675 # number of overall hits
system.cpu.l2cache.overall_miss_latency 8026637000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 8026637500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.197249 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 234579 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits
@ -471,9 +471,9 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 215449 # number of replacements
system.cpu.l2cache.sampled_refs 235636 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 20833.341048 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 20833.351516 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1493772 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 262779341000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 262779379000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 171632 # number of writebacks
system.cpu.memDep0.conflictingLoads 58798533 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 76400324 # Number of conflicting stores.
@ -481,31 +481,31 @@ system.cpu.memDep0.insertedLoads 199993331 # Nu
system.cpu.memDep0.insertedStores 140409395 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1169227072 # number of misc regfile reads
system.cpu.misc_regfile_writes 344748 # number of misc regfile writes
system.cpu.numCycles 731972150 # number of cpu cycles simulated
system.cpu.numCycles 731972226 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 7146790 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 5207540 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 311739226 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 311739239 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 9258079 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2640447492 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenameLookups 2640393118 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1043812056 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 713532745 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RenamedOperands 713587119 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 325976886 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 65446321 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 15480980 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 278164244 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:UndoneMaps 278218618 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 1939 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2640445553 # Number of integer rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2640391179 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 1726383 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 233275 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 49072391 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 185712 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1619326892 # The number of ROB reads
system.cpu.rob.rob_reads 1619326905 # The number of ROB reads
system.cpu.rob.rob_writes 1987147936 # The number of ROB writes
system.cpu.timesIdled 95874 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.timesIdled 95875 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -493,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

8
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 21 2011 14:34:16
M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
M5 started Feb 21 2011 15:06:31
M5 compiled Feb 22 2011 10:22:27
M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
M5 started Feb 22 2011 10:32:06
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

46
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 80651 # Simulator instruction rate (inst/s)
host_mem_usage 263088 # Number of bytes of host memory used
host_seconds 22860.92 # Real time elapsed on the host
host_tick_rate 48422649 # Simulator tick rate (ticks/s)
host_inst_rate 123409 # Simulator instruction rate (inst/s)
host_mem_usage 261412 # Number of bytes of host memory used
host_seconds 14940.26 # Real time elapsed on the host
host_tick_rate 74094191 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1843755906 # Number of instructions simulated
sim_seconds 1.106986 # Number of seconds simulated
@ -119,10 +119,10 @@ system.cpu.dcache.tagsinuse 4095.125005 # Cy
system.cpu.dcache.total_refs 988465092 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 341948000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106863 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 223702819 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3748475941 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 853302516 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 949015542 # Number of cycles decode is running
system.cpu.decode.DECODE:BlockedCycles 223702822 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3748475939 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 853302514 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 949015541 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 187283447 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
@ -148,9 +148,9 @@ system.cpu.dtb.write_hits 0 # DT
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 562377080 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 400588374 # Number of cache lines fetched
system.cpu.fetch.Cycles 1002800662 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.Cycles 1002800660 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 11586077 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2972268197 # Number of instructions fetch has processed
system.cpu.fetch.Insts 2972268195 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 34317 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 86966870 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle
@ -161,11 +161,11 @@ system.cpu.fetch.rateDist::samples 2213708442 # Nu
system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1213776792 54.83% 54.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 388415260 17.55% 72.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1213776794 54.83% 54.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 388415258 17.55% 72.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 48895921 2.21% 78.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 60943546 2.75% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 48895922 2.21% 78.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 60943545 2.75% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 16173405 0.73% 85.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 35829919 1.62% 87.37% # Number of instructions fetched each cycle (Total)
@ -485,7 +485,7 @@ system.cpu.memDep0.conflictingLoads 48375882 # Nu
system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 976823889 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 487070109 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 4207984132 # number of misc regfile reads
system.cpu.misc_regfile_reads 4207984130 # number of misc regfile reads
system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes
system.cpu.numCycles 2213972592 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@ -493,22 +493,22 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 919120367 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 919120364 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 9255846830 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenameLookups 9255846828 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3353421825 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2685986513 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RenamedOperands 2685986515 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 880460594 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 187283447 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 23975324 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1203659002 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:UndoneMaps 1203659004 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 8769983158 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 185210216 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:int_rename_lookups 8769983156 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 185210219 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 226114383 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed
system.cpu.rename.RENAME:skidInsts 226114384 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 13965392 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 4997592808 # The number of ROB reads
system.cpu.rob.rob_writes 6212468368 # The number of ROB writes
system.cpu.timesIdled 87017 # Number of times that the entire CPU went into an idle state and unscheduled itself

8
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 23 2011 14:37:21
M5 revision bc7f8168ee84 7973 default ext/update_regressions.patch qtip tip
M5 started Feb 23 2011 14:37:24
M5 compiled Feb 22 2011 10:22:27
M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
M5 started Feb 22 2011 11:23:21
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!

8
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 6235 # Simulator instruction rate (inst/s)
host_mem_usage 252896 # Number of bytes of host memory used
host_seconds 0.90 # Real time elapsed on the host
host_tick_rate 11404126 # Simulator tick rate (ticks/s)
host_inst_rate 53641 # Simulator instruction rate (inst/s)
host_mem_usage 251224 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
host_tick_rate 97879368 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5620 # Number of instructions simulated
sim_seconds 0.000010 # Number of seconds simulated