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all: Update stats for memory per master and total fix.

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This commit is contained in:
Ali Saidi 2012-06-05 01:23:16 -04:00
parent e5f0d6016b
commit c49e739352
434 changed files with 9815 additions and 3397 deletions
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9
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -936,9 +936,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=true
@ -998,10 +997,9 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
@ -1057,9 +1055,8 @@ output=true
port=3456
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:37:07
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:31:55
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux

184
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -4,23 +4,50 @@ sim_seconds 1.899401 # Nu
sim_ticks 1899401490000 # Number of ticks simulated
final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 69911 # Simulator instruction rate (inst/s)
host_op_rate 69911 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2348556801 # Simulator tick rate (ticks/s)
host_mem_usage 300512 # Number of bytes of host memory used
host_seconds 808.75 # Real time elapsed on the host
host_inst_rate 124517 # Simulator instruction rate (inst/s)
host_op_rate 124517 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4182952627 # Simulator tick rate (ticks/s)
host_mem_usage 300876 # Number of bytes of host memory used
host_seconds 454.08 # Real time elapsed on the host
sim_insts 56540749 # Number of instructions simulated
sim_ops 56540749 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30421696 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10508736 # Number of bytes written to this memory
system.physmem.num_reads 475339 # Number of read requests responded to by this memory
system.physmem.num_writes 164199 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory
system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory
system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory
system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory
system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 397771 # number of replacements
system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use
system.l2c.total_refs 2469954 # Total number of references to valid blocks.
@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # mi
system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -254,44 +293,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.141914 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.924975 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.885246 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.421493 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.175443 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.175443 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40026.250295 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40002.474567 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40002.777778 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40287.773030 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41698 # number of replacements
system.iocache.tagsinuse 0.205020 # Cycle average of tags in use
@ -327,13 +381,21 @@ system.iocache.demand_accesses::total 41730 # nu
system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked
@ -361,13 +423,21 @@ system.iocache.demand_mshr_miss_latency::total 3570695996
system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@ -751,11 +821,17 @@ system.cpu0.icache.demand_accesses::total 7876403 # n
system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked
@ -785,11 +861,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 11020233999
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1225027 # number of replacements
system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use
@ -849,17 +931,29 @@ system.cpu0.dcache.demand_accesses::total 13473054 # n
system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked
@ -911,20 +1005,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
@ -1265,11 +1374,17 @@ system.cpu1.icache.demand_accesses::total 1679880 # n
system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked
@ -1299,11 +1414,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 2188079500
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 156190 # number of replacements
system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use
@ -1363,17 +1484,29 @@ system.cpu1.dcache.demand_accesses::total 2874738 # n
system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked
@ -1425,20 +1558,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed
@ -1466,6 +1614,7 @@ system.cpu0.kern.ipl_used::21 1 # fr
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed
system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed
system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed
@ -1523,7 +1672,7 @@ system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
@ -1550,6 +1699,7 @@ system.cpu1.kern.ipl_used::0 0.998669 # fr
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed
system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed
system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed
@ -1595,7 +1745,7 @@ system.cpu1.kern.mode_good::idle 169
system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 1.702972 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode

9
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -512,9 +512,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=true
@ -574,10 +573,9 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
@ -633,9 +631,8 @@ output=true
port=3456
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:37:06
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:16:04
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux

131
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -4,23 +4,40 @@ sim_seconds 1.858684 # Nu
sim_ticks 1858684403000 # Number of ticks simulated
final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 73473 # Simulator instruction rate (inst/s)
host_op_rate 73473 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2572309842 # Simulator tick rate (ticks/s)
host_mem_usage 296656 # Number of bytes of host memory used
host_seconds 722.57 # Real time elapsed on the host
host_inst_rate 125153 # Simulator instruction rate (inst/s)
host_op_rate 125153 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4381630644 # Simulator tick rate (ticks/s)
host_mem_usage 297044 # Number of bytes of host memory used
host_seconds 424.20 # Real time elapsed on the host
sim_insts 53089851 # Number of instructions simulated
sim_ops 53089851 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29847552 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10195968 # Number of bytes written to this memory
system.physmem.num_reads 466368 # Number of read requests responded to by this memory
system.physmem.num_writes 159312 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 1082432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 26112576 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652544 # Number of bytes read from this memory
system.physmem.bytes_read::total 29847552 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1082432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1082432 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 10195968 # Number of bytes written to this memory
system.physmem.bytes_written::total 10195968 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 16913 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 408009 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41446 # Number of read requests responded to by this memory
system.physmem.num_reads::total 466368 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 159312 # Number of write requests responded to by this memory
system.physmem.num_writes::total 159312 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 582365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14048956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1427108 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16058429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 582365 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 582365 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5485583 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5485583 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5485583 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 582365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14048956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1427108 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21544012 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 391653 # number of replacements
system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use
system.l2c.total_refs 2427420 # Total number of references to valid blocks.
@ -98,21 +115,32 @@ system.l2c.overall_accesses::cpu.data 1403007 # nu
system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.144884 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.680851 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.389089 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.175120 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.175120 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52055.178139 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13296.875000 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52452.302421 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52164.425310 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52164.425310 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -167,25 +195,40 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998
system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.144884 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.680851 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.389089 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.175120 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.175120 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40034.215681 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41968.750000 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40285.591605 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40103.368272 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.266745 # Cycle average of tags in use
@ -221,13 +264,21 @@ system.iocache.demand_accesses::total 41725 # nu
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 137703.090248 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 137609.989311 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 137609.989311 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
@ -255,13 +306,21 @@ system.iocache.demand_mshr_miss_latency::total 3571928992
system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 85699.532971 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 85606.446783 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@ -645,11 +704,17 @@ system.cpu.icache.demand_accesses::total 9001683 # nu
system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.120654 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.120654 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.120654 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14978.890385 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14978.890385 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14978.890385 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked
@ -679,11 +744,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12299507497
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114017 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.114017 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.114017 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.817785 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.817785 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1402627 # number of replacements
system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use
@ -743,17 +814,29 @@ system.cpu.dcache.demand_accesses::total 15284608 # nu
system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.197665 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.315555 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107789 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000014 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.245154 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.245154 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21564.412465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29908.900809 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14827.843607 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27833.333333 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25891.032108 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25891.032108 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked
@ -805,20 +888,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118919 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048701 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082959 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000014 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.090634 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.090634 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22826.893897 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28446.182850 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11814.556470 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24666.666667 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24043.205344 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed
@ -842,6 +940,7 @@ system.cpu.kern.ipl_used::0 0.981743 # fr
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815921 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
@ -899,7 +998,7 @@ system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.389995 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi
atags_addr=256
boot_loader=/dist/m5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
early_kernel_symbols=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
memories=system.realview.nvmem system.physmem
midr_regval=890224640
num_work_ids=16
readfile=tests/halt.sh
@ -570,9 +571,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -631,10 +631,9 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
@ -1046,9 +1045,8 @@ output=true
port=3456
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 10 2012 12:36:36
gem5 started May 10 2012 12:41:59
gem5 executing on u200540-lin
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:58:44
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2501685689500 because m5_exit instruction encountered

149
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu
sim_ticks 2501685689500 # Number of ticks simulated
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54158 # Simulator instruction rate (inst/s)
host_op_rate 69928 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2274069684 # Simulator tick rate (ticks/s)
host_mem_usage 384504 # Number of bytes of host memory used
host_seconds 1100.09 # Real time elapsed on the host
host_inst_rate 49441 # Simulator instruction rate (inst/s)
host_op_rate 63837 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2075989543 # Simulator tick rate (ticks/s)
host_mem_usage 387400 # Number of bytes of host memory used
host_seconds 1205.06 # Real time elapsed on the host
sim_insts 59579009 # Number of instructions simulated
sim_ops 76926775 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 129658608 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_written 9585736 # Number of bytes written to this memory
system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
system.physmem.num_writes 856669 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 119797 # number of replacements
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -676,11 +734,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
@ -714,13 +778,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 645895 # number of replacements
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
@ -780,17 +852,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
@ -842,20 +926,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
@ -876,7 +975,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview
atags_addr=256
boot_loader=/dist/m5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
early_kernel_symbols=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
@ -953,9 +954,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -1014,10 +1014,9 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
@ -1429,9 +1428,8 @@ output=true
port=3456
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 10 2012 12:36:36
gem5 started May 10 2012 12:41:59
gem5 executing on u200540-lin
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:58:50
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2570833934500 because m5_exit instruction encountered

218
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,32 +4,90 @@ sim_seconds 2.570834 # Nu
sim_ticks 2570833934500 # Number of ticks simulated
final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 63716 # Simulator instruction rate (inst/s)
host_op_rate 82290 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2641493756 # Simulator tick rate (ticks/s)
host_mem_usage 388068 # Number of bytes of host memory used
host_seconds 973.25 # Real time elapsed on the host
host_inst_rate 53678 # Simulator instruction rate (inst/s)
host_op_rate 69325 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2225327298 # Simulator tick rate (ticks/s)
host_mem_usage 390932 # Number of bytes of host memory used
host_seconds 1155.26 # Real time elapsed on the host
sim_insts 62012062 # Number of instructions simulated
sim_ops 80088895 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 131429540 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10175696 # Number of bytes written to this memory
system.physmem.num_reads 15128117 # Number of read requests responded to by this memory
system.physmem.num_writes 868949 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory
system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 130926 # number of replacements
system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use
system.l2c.total_refs 1855308 # Total number of references to valid blocks.
@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses
@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses
@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency
@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency
@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency
@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -381,12 +451,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses
@ -395,6 +469,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses
@ -403,6 +478,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency
@ -411,12 +487,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency
@ -425,6 +505,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency
@ -433,16 +514,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -802,11 +887,17 @@ system.cpu0.icache.demand_accesses::total 3831829 # n
system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked
@ -840,13 +931,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 232498 # number of replacements
system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use
@ -906,17 +1005,29 @@ system.cpu0.dcache.demand_accesses::total 9184667 # n
system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked
@ -968,20 +1079,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
@ -1335,11 +1461,17 @@ system.cpu1.icache.demand_accesses::total 10441732 # n
system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked
@ -1373,13 +1505,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 417022 # number of replacements
system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use
@ -1439,17 +1579,29 @@ system.cpu1.dcache.demand_accesses::total 17145866 # n
system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
@ -1503,21 +1655,37 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
@ -1538,7 +1706,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi
atags_addr=256
boot_loader=/dist/m5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
early_kernel_symbols=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
memories=system.realview.nvmem system.physmem
midr_regval=890224640
num_work_ids=16
readfile=tests/halt.sh
@ -511,9 +512,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -572,10 +572,9 @@ cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
@ -987,9 +986,8 @@ output=true
port=3456
[system.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 10 2012 12:36:36
gem5 started May 10 2012 12:41:59
gem5 executing on u200540-lin
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 18:55:16
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2501685689500 because m5_exit instruction encountered

149
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu
sim_ticks 2501685689500 # Number of ticks simulated
final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 62639 # Simulator instruction rate (inst/s)
host_op_rate 80877 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2630163340 # Simulator tick rate (ticks/s)
host_mem_usage 384244 # Number of bytes of host memory used
host_seconds 951.15 # Real time elapsed on the host
host_inst_rate 57858 # Simulator instruction rate (inst/s)
host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
host_mem_usage 387132 # Number of bytes of host memory used
host_seconds 1029.75 # Real time elapsed on the host
sim_insts 59579009 # Number of instructions simulated
sim_ops 76926775 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 129658608 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_written 9585736 # Number of bytes written to this memory
system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
system.physmem.num_writes 856669 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 119797 # number of replacements
system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
system.l2c.total_refs 1834134 # Total number of references to valid blocks.
@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@ -631,11 +689,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu
system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
@ -669,13 +733,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 645895 # number of replacements
system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
@ -735,17 +807,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu
system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
@ -797,20 +881,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
@ -831,7 +930,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:58
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 17:03:49
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second

149
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

@ -4,23 +4,48 @@ sim_seconds 5.157514 # Nu
sim_ticks 5157514159500 # Number of ticks simulated
final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 128842 # Simulator instruction rate (inst/s)
host_op_rate 253899 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1558019011 # Simulator tick rate (ticks/s)
host_mem_usage 389972 # Number of bytes of host memory used
host_seconds 3310.30 # Real time elapsed on the host
host_inst_rate 123762 # Simulator instruction rate (inst/s)
host_op_rate 243888 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1496586873 # Simulator tick rate (ticks/s)
host_mem_usage 369148 # Number of bytes of host memory used
host_seconds 3446.18 # Real time elapsed on the host
sim_insts 426506235 # Number of instructions simulated
sim_ops 840483958 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 15959488 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 12050112 # Number of bytes written to this memory
system.physmem.num_reads 249367 # Number of read requests responded to by this memory
system.physmem.num_writes 188283 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::pc.south_bridge.ide 2798400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 6720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 1088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1257664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11895616 # Number of bytes read from this memory
system.physmem.bytes_read::total 15959488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1257664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1257664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 12050112 # Number of bytes written to this memory
system.physmem.bytes_written::total 12050112 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 43725 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 105 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 17 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 19651 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 185869 # Number of read requests responded to by this memory
system.physmem.num_reads::total 249367 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 188283 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188283 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 542587 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 243851 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2306463 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3094415 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 243851 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 243851 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2336419 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2336419 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2336419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 542587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 243851 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2306463 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5430833 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 167142 # number of replacements
system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use
system.l2c.total_refs 3843284 # Total number of references to valid blocks.
@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.882394 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.481904 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.071839 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.071839 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52468.724211 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52077.298075 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52201.292100 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52201.292100 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -213,33 +248,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.025337 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.882394 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.481904 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.071838 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.071838 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40085.880200 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47578 # number of replacements
system.iocache.tagsinuse 0.166155 # Cycle average of tags in use
@ -275,13 +323,21 @@ system.iocache.demand_accesses::total 47633 # nu
system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125279.224535 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 136416.955479 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 136203.474314 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 136203.474314 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked
@ -309,13 +365,21 @@ system.iocache.demand_mshr_miss_latency::total 4010524860
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 84196.352529 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@ -635,11 +699,17 @@ system.cpu.icache.demand_accesses::total 9366799 # nu
system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123115 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123115 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123115 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14938.055188 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14938.055188 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked
@ -669,11 +739,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 13093471492
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115814 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.115814 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.115814 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 10825 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use
@ -713,11 +789,17 @@ system.cpu.itb_walker_cache.demand_accesses::total 39097
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.298946 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.298923 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.298923 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -741,11 +823,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.298946 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.298923 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.298923 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9644.861812 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9644.861812 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 116553 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use
@ -781,11 +869,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total 253531
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463730 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463730 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463730 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -809,11 +903,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463730 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463730 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463730 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1673290 # number of replacements
system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use
@ -857,13 +957,21 @@ system.cpu.dcache.demand_accesses::total 21751990 # nu
system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.180567 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037870 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.125479 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.125479 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17127.337761 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17127.337761 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked
@ -905,16 +1013,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103449 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035203 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077103 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077103 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed

9
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@ -995,7 +995,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1015,7 +1015,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
@ -1185,9 +1185,8 @@ zero=false
port=system.piobus.master[0]
[system.piobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=true

34
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
View file

@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: May/21/2012 19:39:45
Real time: Jun/04/2012 17:25:31
Profiler Stats
--------------
Elapsed_time_in_seconds: 1285
Elapsed_time_in_minutes: 21.4167
Elapsed_time_in_hours: 0.356944
Elapsed_time_in_days: 0.0148727
Elapsed_time_in_seconds: 842
Elapsed_time_in_minutes: 14.0333
Elapsed_time_in_hours: 0.233889
Elapsed_time_in_days: 0.00974537
Virtual_time_in_seconds: 1013.41
Virtual_time_in_minutes: 16.8902
Virtual_time_in_hours: 0.281503
Virtual_time_in_days: 0.0117293
Virtual_time_in_seconds: 842.03
Virtual_time_in_minutes: 14.0338
Virtual_time_in_hours: 0.233897
Virtual_time_in_days: 0.00974572
Ruby_current_time: 10609379371
Ruby_start_time: 0
Ruby_cycles: 10609379371
mbytes_resident: 269.652
mbytes_total: 517.469
resident_ratio: 0.521114
mbytes_resident: 268.047
mbytes_total: 470.199
resident_ratio: 0.570071
ruby_cycles_executed: [ 10609379372 10609379372 ]
@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 |
Resource Usage
--------------
page_size: 4096
user_time: 1013
user_time: 841
system_time: 0
page_reclaims: 70791
page_faults: 113
page_reclaims: 69674
page_faults: 18
swaps: 0
block_inputs: 0
block_outputs: 0
block_inputs: 16056
block_outputs: 408
Network Stats
-------------

10
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,15 +1,13 @@
Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 21 2012 19:18:11
gem5 started May 21 2012 19:18:20
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Jun 4 2012 13:44:12
gem5 started Jun 4 2012 17:11:29
gem5 executing on zizzer
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5304689685500 because m5_exit instruction encountered

85
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,23 +4,74 @@ sim_seconds 5.304690 # Nu
sim_ticks 5304689685500 # Number of ticks simulated
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 106822 # Simulator instruction rate (inst/s)
host_op_rate 218222 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4128199893 # Simulator tick rate (ticks/s)
host_mem_usage 529892 # Number of bytes of host memory used
host_seconds 1284.99 # Real time elapsed on the host
host_inst_rate 163049 # Simulator instruction rate (inst/s)
host_op_rate 333085 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6301127704 # Simulator tick rate (ticks/s)
host_mem_usage 481488 # Number of bytes of host memory used
host_seconds 841.86 # Real time elapsed on the host
sim_insts 137264752 # Number of instructions simulated
sim_ops 280412254 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1392025556 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1298120352 # Number of instructions bytes read from this memory
system.physmem.bytes_written 70902832 # Number of bytes written to this memory
system.physmem.num_reads 178001662 # Number of read requests responded to by this memory
system.physmem.num_writes 9866514 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 262414135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 244711836 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13366066 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 275780201 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory
system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory
system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory
system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory
system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
@ -44,7 +95,7 @@ system.cpu0.num_func_calls 0 # nu
system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls
system.cpu0.num_int_insts 168469813 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 517963582 # number of times the integer registers were read
system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read
system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
@ -68,7 +119,7 @@ system.cpu1.num_func_calls 0 # nu
system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls
system.cpu1.num_int_insts 89110416 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 273178552 # number of times the integer registers were read
system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read
system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written

8
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
View file

@ -19,7 +19,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem
memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
@ -140,9 +140,8 @@ type=IntrControl
sys=system
[system.iobus]
type=Bus
type=NoncoherentBus
block_size=64
bus_id=0
clock=2
header_cycles=1
use_default_range=false
@ -151,10 +150,9 @@ master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake
slave=system.bridge.master
[system.membus]
type=Bus
type=CoherentBus
children=badaddr_responder
block_size=64
bus_id=1
clock=2
header_cycles=1
use_default_range=false

1
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
View file

@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting terminal connections
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
hack: be nice to actually delete the event here

6
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:49:20
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 15:02:47
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA

158
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
View file

@ -4,67 +4,107 @@ sim_seconds 1.116889 # Nu
sim_ticks 2233777512 # Number of ticks simulated
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
host_inst_rate 1707325 # Simulator instruction rate (inst/s)
host_op_rate 1707996 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1711534 # Simulator tick rate (ticks/s)
host_mem_usage 511008 # Number of bytes of host memory used
host_seconds 1305.13 # Real time elapsed on the host
host_inst_rate 3140005 # Simulator instruction rate (inst/s)
host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3147745 # Simulator tick rate (ticks/s)
host_mem_usage 511524 # Number of bytes of host memory used
host_seconds 709.64 # Real time elapsed on the host
sim_insts 2228284650 # Number of instructions simulated
sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory
system.hypervisor_desc.num_reads 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.num_writes 0 # Number of write requests responded to by this memory
system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read 284 # Number of bytes read from this memory
system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.nvram.bytes_written 92 # Number of bytes written to this memory
system.nvram.num_reads 284 # Number of read requests responded to by this memory
system.nvram.num_writes 92 # Number of write requests responded to by this memory
system.nvram.num_other 0 # Number of other requests responded to by this memory
system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.partition_desc.bytes_written 0 # Number of bytes written to this memory
system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
system.partition_desc.num_other 0 # Number of other requests responded to by this memory
system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
system.physmem2.num_reads 2403489130 # Number of read requests responded to by this memory
system.physmem2.num_writes 187387796 # Number of write requests responded to by this memory
system.physmem2.num_other 5403067 # Number of other requests responded to by this memory
system.physmem2.bw_read 8786901931 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read 1128688 # Number of bytes read from this memory
system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
system.rom.bytes_written 0 # Number of bytes written to this memory
system.rom.num_reads 195123 # Number of read requests responded to by this memory
system.rom.num_writes 0 # Number of write requests responded to by this memory
system.rom.num_other 0 # Number of other requests responded to by this memory
system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read 709825348 # Number of bytes read from this memory
system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_written 15400223 # Number of bytes written to this memory
system.physmem.num_reads 165224885 # Number of read requests responded to by this memory
system.physmem.num_writes 1927067 # Number of write requests responded to by this memory
system.physmem.num_other 14 # Number of other requests responded to by this memory
system.physmem.bw_read 635538091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

6
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -209,9 +208,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:38:38
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:43:43
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.274300 # Nu
sim_ticks 274300226500 # Number of ticks simulated
final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71153 # Simulator instruction rate (inst/s)
host_op_rate 71153 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32428333 # Simulator tick rate (ticks/s)
host_mem_usage 214868 # Number of bytes of host memory used
host_seconds 8458.66 # Real time elapsed on the host
host_inst_rate 112537 # Simulator instruction rate (inst/s)
host_op_rate 112537 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51289289 # Simulator tick rate (ticks/s)
host_mem_usage 215256 # Number of bytes of host memory used
host_seconds 5348.10 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5894080 # Number of bytes read from this memory
system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3798144 # Number of bytes written to this memory
system.physmem.num_reads 92095 # Number of read requests responded to by this memory
system.physmem.num_writes 59346 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory
system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 25020500 # nu
system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45765000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use
@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked
@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9028960000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73798 # number of replacements
system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use
@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500
system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -507,9 +506,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:36:56
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:45
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

89
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.134621 # Nu
sim_ticks 134621123500 # Number of ticks simulated
final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 99995 # Simulator instruction rate (inst/s)
host_op_rate 99995 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23802311 # Simulator tick rate (ticks/s)
host_mem_usage 215740 # Number of bytes of host memory used
host_seconds 5655.80 # Real time elapsed on the host
host_inst_rate 192359 # Simulator instruction rate (inst/s)
host_op_rate 192359 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45788058 # Simulator tick rate (ticks/s)
host_mem_usage 216172 # Number of bytes of host memory used
host_seconds 2940.09 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5937600 # Number of bytes read from this memory
system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3797952 # Number of bytes written to this memory
system.physmem.num_reads 92775 # Number of read requests responded to by this memory
system.physmem.num_writes 59343 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory
system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory
system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 66483943 # nu
system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35750000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 460743 # number of replacements
system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use
@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 151114481 # nu
system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked
@ -492,13 +527,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4648014495
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 74480 # number of replacements
system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use
@ -560,18 +603,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 464839
system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.155864 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235100 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.199156 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.199156 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked
@ -606,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500
system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -94,9 +94,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

1
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,3 +1,4 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything

6
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:37:40
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 14:03:38
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.300931 # Nu
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2479447 # Simulator instruction rate (inst/s)
host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1239733454 # Simulator tick rate (ticks/s)
host_mem_usage 205680 # Number of bytes of host memory used
host_seconds 242.74 # Real time elapsed on the host
host_inst_rate 3871430 # Simulator instruction rate (inst/s)
host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1935730316 # Simulator tick rate (ticks/s)
host_mem_usage 206040 # Number of bytes of host memory used
host_seconds 155.46 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_written 152669504 # Number of bytes written to this memory
system.physmem.num_reads 716375939 # Number of read requests responded to by this memory
system.physmem.num_writes 39451321 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory
system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory
system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory
system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory
system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv

6
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -176,9 +175,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31
gem5 started May 8 2012 15:37:07
gem5 executing on piton
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:42:36
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.765623 # Nu
sim_ticks 765623032000 # Number of ticks simulated
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 835603 # Simulator instruction rate (inst/s)
host_op_rate 835603 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1062971026 # Simulator tick rate (ticks/s)
host_mem_usage 214568 # Number of bytes of host memory used
host_seconds 720.27 # Real time elapsed on the host
host_inst_rate 1675799 # Simulator instruction rate (inst/s)
host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2131786057 # Simulator tick rate (ticks/s)
host_mem_usage 214908 # Number of bytes of host memory used
host_seconds 359.15 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5889984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3797824 # Number of bytes written to this memory
system.physmem.num_reads 92031 # Number of read requests responded to by this memory
system.physmem.num_writes 59341 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory
system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory
system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 601861898 # nu
system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42135000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8841257000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73734 # number of replacements
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -525,9 +524,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:20:58
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:39
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

92
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.164248 # Nu
sim_ticks 164248292500 # Number of ticks simulated
final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 95192 # Simulator instruction rate (inst/s)
host_op_rate 100587 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27427613 # Simulator tick rate (ticks/s)
host_mem_usage 231504 # Number of bytes of host memory used
host_seconds 5988.43 # Real time elapsed on the host
host_inst_rate 143439 # Simulator instruction rate (inst/s)
host_op_rate 151568 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41328806 # Simulator tick rate (ticks/s)
host_mem_usage 231960 # Number of bytes of host memory used
host_seconds 3974.18 # Real time elapsed on the host
sim_insts 570052728 # Number of instructions simulated
sim_ops 602360935 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5850432 # Number of bytes read from this memory
system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3722112 # Number of bytes written to this memory
system.physmem.num_reads 91413 # Number of read requests responded to by this memory
system.physmem.num_writes 58158 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory
system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory
system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory
system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 67495318 # nu
system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -400,11 +419,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 28616000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34107.270560 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440506 # number of replacements
system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use
@ -460,15 +485,25 @@ system.cpu.dcache.demand_accesses::total 201731606 # nu
system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001884 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022587 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009379 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009008 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009008 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13208.806613 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked
@ -506,13 +541,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4172571513
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8257.093815 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10286.222787 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73212 # number of replacements
system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use
@ -583,19 +626,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 444603
system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166926 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.333333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235994 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.205242 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.205242 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34299.915423 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34319.932438 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34312.683898 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34312.683898 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked
@ -643,20 +695,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000
system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166876 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235994 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205220 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205220 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.415277 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31229.898657 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -112,9 +112,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:21:51
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:49
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.301191 # Nu
sim_ticks 301191370000 # Number of ticks simulated
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1201570 # Simulator instruction rate (inst/s)
host_op_rate 1269670 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 634859326 # Simulator tick rate (ticks/s)
host_mem_usage 220780 # Number of bytes of host memory used
host_seconds 474.42 # Real time elapsed on the host
host_inst_rate 2291609 # Simulator instruction rate (inst/s)
host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1210789798 # Simulator tick rate (ticks/s)
host_mem_usage 221260 # Number of bytes of host memory used
host_seconds 248.76 # Real time elapsed on the host
sim_insts 570051644 # Number of instructions simulated
sim_ops 602359851 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_written 236359611 # Number of bytes written to this memory
system.physmem.num_reads 717867713 # Number of read requests responded to by this memory
system.physmem.num_writes 69418858 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory
system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory
system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory
system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory
system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits

6
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -194,9 +193,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:22:17
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:27:51
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.796763 # Nu
sim_ticks 796762926000 # Number of ticks simulated
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 606714 # Simulator instruction rate (inst/s)
host_op_rate 640712 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 850261270 # Simulator tick rate (ticks/s)
host_mem_usage 229976 # Number of bytes of host memory used
host_seconds 937.08 # Real time elapsed on the host
host_inst_rate 1154549 # Simulator instruction rate (inst/s)
host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1618008338 # Simulator tick rate (ticks/s)
host_mem_usage 230404 # Number of bytes of host memory used
host_seconds 492.43 # Real time elapsed on the host
sim_insts 568539343 # Number of instructions simulated
sim_ops 600398281 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3704704 # Number of bytes written to this memory
system.physmem.num_reads 89992 # Number of read requests responded to by this memory
system.physmem.num_writes 57886 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory
system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory
system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory
system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory
system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 570074535 # nu
system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32945000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 217209383 # nu
system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8566996000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 71804 # number of replacements
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 437564
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000
system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -507,9 +506,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:43:17
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:35
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

91
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.388554 # Nu
sim_ticks 388554296500 # Number of ticks simulated
final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 119684 # Simulator instruction rate (inst/s)
host_op_rate 120061 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33188741 # Simulator tick rate (ticks/s)
host_mem_usage 223864 # Number of bytes of host memory used
host_seconds 11707.41 # Real time elapsed on the host
host_inst_rate 160259 # Simulator instruction rate (inst/s)
host_op_rate 160764 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44440455 # Simulator tick rate (ticks/s)
host_mem_usage 224388 # Number of bytes of host memory used
host_seconds 8743.26 # Real time elapsed on the host
sim_insts 1401188958 # Number of instructions simulated
sim_ops 1405604152 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5987456 # Number of bytes read from this memory
system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3788160 # Number of bytes written to this memory
system.physmem.num_reads 93554 # Number of read requests responded to by this memory
system.physmem.num_writes 59190 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory
system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory
system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory
system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 777108594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -324,11 +337,17 @@ system.cpu.icache.demand_accesses::total 162823525 # nu
system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -356,11 +375,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 47023000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 458031 # number of replacements
system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use
@ -412,15 +437,25 @@ system.cpu.dcache.demand_accesses::total 368453310 # nu
system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
@ -460,15 +495,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5156941222
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 75325 # number of replacements
system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use
@ -533,18 +578,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 462127
system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166316 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.229160 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34037.511942 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34411.294082 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34277.465421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34277.465421 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -579,18 +632,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500
system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -94,9 +94,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

1
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
View file

@ -1,2 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

6
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:43:18
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:41
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

44
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,37 @@ sim_seconds 0.744764 # Nu
sim_ticks 744764119000 # Number of ticks simulated
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1723625 # Simulator instruction rate (inst/s)
host_op_rate 1728749 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 864377228 # Simulator tick rate (ticks/s)
host_mem_usage 213676 # Number of bytes of host memory used
host_seconds 861.62 # Real time elapsed on the host
host_inst_rate 3186892 # Simulator instruction rate (inst/s)
host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1598188492 # Simulator tick rate (ticks/s)
host_mem_usage 214172 # Number of bytes of host memory used
host_seconds 466.01 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_written 614672063 # Number of bytes written to this memory
system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory
system.physmem.num_writes 166846816 # Number of write requests responded to by this memory
system.physmem.num_other 1326 # Number of other requests responded to by this memory
system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory
system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory
system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory
system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory
system.physmem.num_other::total 1326 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started

6
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -176,9 +175,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:43:22
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:45
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

91
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 2.064259 # Nu
sim_ticks 2064258667000 # Number of ticks simulated
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 667477 # Simulator instruction rate (inst/s)
host_op_rate 669461 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 927773801 # Simulator tick rate (ticks/s)
host_mem_usage 222564 # Number of bytes of host memory used
host_seconds 2224.96 # Real time elapsed on the host
host_inst_rate 1371910 # Simulator instruction rate (inst/s)
host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1906915769 # Simulator tick rate (ticks/s)
host_mem_usage 223048 # Number of bytes of host memory used
host_seconds 1082.51 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5909952 # Number of bytes read from this memory
system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3778240 # Number of bytes written to this memory
system.physmem.num_reads 92343 # Number of read requests responded to by this memory
system.physmem.num_writes 59035 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory
system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory
system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1485113012 # nu
system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 58503000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 569359660 # nu
system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8817140000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 74112 # number of replacements
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 453221
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000
system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:59
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:07:25
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.636988 # Nu
sim_ticks 636988382500 # Number of ticks simulated
final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71818 # Simulator instruction rate (inst/s)
host_op_rate 132329 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51984066 # Simulator tick rate (ticks/s)
host_mem_usage 250428 # Number of bytes of host memory used
host_seconds 12253.53 # Real time elapsed on the host
host_inst_rate 63436 # Simulator instruction rate (inst/s)
host_op_rate 116883 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45916521 # Simulator tick rate (ticks/s)
host_mem_usage 227532 # Number of bytes of host memory used
host_seconds 13872.75 # Real time elapsed on the host
sim_insts 880025312 # Number of instructions simulated
sim_ops 1621493982 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5834048 # Number of bytes read from this memory
system.physmem.bytes_inst_read 59200 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3731712 # Number of bytes written to this memory
system.physmem.num_reads 91157 # Number of read requests responded to by this memory
system.physmem.num_writes 58308 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 9158798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 92937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 5858367 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 15017166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory
system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory
system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory
system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1273976766 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -322,11 +335,17 @@ system.cpu.icache.demand_accesses::total 186830267 # nu
system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -354,11 +373,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32805000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 445407 # number of replacements
system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use
@ -402,13 +427,21 @@ system.cpu.dcache.demand_accesses::total 453124365 # nu
system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -444,13 +477,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3996172000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 72883 # number of replacements
system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use
@ -519,18 +560,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 449505
system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -565,18 +614,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000
system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:58
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:08:17
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.963993 # Nu
sim_ticks 963992704000 # Number of ticks simulated
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 688761 # Simulator instruction rate (inst/s)
host_op_rate 1269079 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 754478822 # Simulator tick rate (ticks/s)
host_mem_usage 239576 # Number of bytes of host memory used
host_seconds 1277.69 # Real time elapsed on the host
host_inst_rate 1254577 # Simulator instruction rate (inst/s)
host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1374282564 # Simulator tick rate (ticks/s)
host_mem_usage 216676 # Number of bytes of host memory used
host_seconds 701.45 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_written 864451000 # Number of bytes written to this memory
system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory
system.physmem.num_writes 188186057 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started

6
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:59
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:13:02
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 1.803259 # Nu
sim_ticks 1803258587000 # Number of ticks simulated
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 617600 # Simulator instruction rate (inst/s)
host_op_rate 1137962 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1265523884 # Simulator tick rate (ticks/s)
host_mem_usage 248496 # Number of bytes of host memory used
host_seconds 1424.91 # Real time elapsed on the host
host_inst_rate 587265 # Simulator instruction rate (inst/s)
host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1203364849 # Simulator tick rate (ticks/s)
host_mem_usage 225604 # Number of bytes of host memory used
host_seconds 1498.51 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5725952 # Number of bytes read from this memory
system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3712448 # Number of bytes written to this memory
system.physmem.num_reads 89468 # Number of read requests responded to by this memory
system.physmem.num_writes 58007 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory
system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory
system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory
system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1186516740 # nu
system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38266000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 607228182 # nu
system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8589860000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 71208 # number of replacements
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 442048
system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000
system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -525,9 +524,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:22:28
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:32:09
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

89
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.025989 # Nu
sim_ticks 25988864000 # Number of ticks simulated
final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71403 # Simulator instruction rate (inst/s)
host_op_rate 71915 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20482160 # Simulator tick rate (ticks/s)
host_mem_usage 364344 # Number of bytes of host memory used
host_seconds 1268.85 # Real time elapsed on the host
host_inst_rate 141606 # Simulator instruction rate (inst/s)
host_op_rate 142623 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40620332 # Simulator tick rate (ticks/s)
host_mem_usage 364696 # Number of bytes of host memory used
host_seconds 639.80 # Real time elapsed on the host
sim_insts 90599356 # Number of instructions simulated
sim_ops 91249910 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 999040 # Number of bytes read from this memory
system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2048 # Number of bytes written to this memory
system.physmem.num_reads 15610 # Number of read requests responded to by this memory
system.physmem.num_writes 32 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory
system.physmem.bytes_read::total 999040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 14156722 # nu
system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 25625000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943602 # number of replacements
system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use
@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 29605337 # nu
system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked
@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3479231630
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 770 # number of replacements
system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use
@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 947698
system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001202 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.325962 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016469 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016469 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000
system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -112,9 +112,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:24:24
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:36:14
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.054241 # Nu
sim_ticks 54240666000 # Number of ticks simulated
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1203852 # Simulator instruction rate (inst/s)
host_op_rate 1212496 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 720706000 # Simulator tick rate (ticks/s)
host_mem_usage 353596 # Number of bytes of host memory used
host_seconds 75.26 # Real time elapsed on the host
host_inst_rate 2223712 # Simulator instruction rate (inst/s)
host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1331261387 # Simulator tick rate (ticks/s)
host_mem_usage 354056 # Number of bytes of host memory used
host_seconds 40.74 # Real time elapsed on the host
sim_insts 90602415 # Number of instructions simulated
sim_ops 91252969 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_written 18908138 # Number of bytes written to this memory
system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits

6
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -194,9 +193,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:24:48
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:37:05
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.148086 # Nu
sim_ticks 148086239000 # Number of ticks simulated
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 549790 # Simulator instruction rate (inst/s)
host_op_rate 553732 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 898863423 # Simulator tick rate (ticks/s)
host_mem_usage 362780 # Number of bytes of host memory used
host_seconds 164.75 # Real time elapsed on the host
host_inst_rate 1056603 # Simulator instruction rate (inst/s)
host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1727464138 # Simulator tick rate (ticks/s)
host_mem_usage 363220 # Number of bytes of host memory used
host_seconds 85.72 # Real time elapsed on the host
sim_insts 90576869 # Number of instructions simulated
sim_ops 91226321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 986112 # Number of bytes read from this memory
system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2048 # Number of bytes written to this memory
system.physmem.num_reads 15408 # Number of read requests responded to by this memory
system.physmem.num_writes 32 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory
system.physmem.bytes_read::total 986112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 107830780 # nu
system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 30865000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 27284389 # nu
system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 11037638000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 634 # number of replacements
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 946798
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000
system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -94,9 +94,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

1
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
View file

@ -1,2 +1,3 @@
warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here

6
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:43:24
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:53:37
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

44
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,37 @@ sim_seconds 0.122216 # Nu
sim_ticks 122215830000 # Number of ticks simulated
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1503519 # Simulator instruction rate (inst/s)
host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 753629165 # Simulator tick rate (ticks/s)
host_mem_usage 346024 # Number of bytes of host memory used
host_seconds 162.17 # Real time elapsed on the host
host_inst_rate 2951739 # Simulator instruction rate (inst/s)
host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1479540198 # Simulator tick rate (ticks/s)
host_mem_usage 346528 # Number of bytes of host memory used
host_seconds 82.60 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_written 91606089 # Number of bytes written to this memory
system.physmem.num_reads 326641945 # Number of read requests responded to by this memory
system.physmem.num_writes 22901951 # Number of write requests responded to by this memory
system.physmem.num_other 3886 # Number of other requests responded to by this memory
system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started

6
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -176,9 +175,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:05:42
gem5 started May 8 2012 15:44:07
gem5 executing on piton
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:55:10
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

91
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.362431 # Nu
sim_ticks 362430887000 # Number of ticks simulated
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 628265 # Simulator instruction rate (inst/s)
host_op_rate 628291 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 933876298 # Simulator tick rate (ticks/s)
host_mem_usage 354916 # Number of bytes of host memory used
host_seconds 388.09 # Real time elapsed on the host
host_inst_rate 1267775 # Simulator instruction rate (inst/s)
host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
host_mem_usage 355400 # Number of bytes of host memory used
host_seconds 192.33 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2560 # Number of bytes written to this memory
system.physmem.num_reads 15648 # Number of read requests responded to by this memory
system.physmem.num_writes 40 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 244421512 # nu
system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 46620000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 105122385 # nu
system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10955493000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 865 # number of replacements
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 939571
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000
system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:59
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:14:48
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

90
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.067388 # Nu
sim_ticks 67388458000 # Number of ticks simulated
final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 74550 # Simulator instruction rate (inst/s)
host_op_rate 131270 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31798513 # Simulator tick rate (ticks/s)
host_mem_usage 385908 # Number of bytes of host memory used
host_seconds 2119.23 # Real time elapsed on the host
host_inst_rate 84988 # Simulator instruction rate (inst/s)
host_op_rate 149650 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36250631 # Simulator tick rate (ticks/s)
host_mem_usage 363056 # Number of bytes of host memory used
host_seconds 1858.96 # Real time elapsed on the host
sim_insts 157988582 # Number of instructions simulated
sim_ops 278192519 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 3907520 # Number of bytes read from this memory
system.physmem.bytes_inst_read 69248 # Number of instructions bytes read from this memory
system.physmem.bytes_written 897536 # Number of bytes written to this memory
system.physmem.num_reads 61055 # Number of read requests responded to by this memory
system.physmem.num_writes 14024 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 57985004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1027594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13318839 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 71303843 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory
system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory
system.physmem.bytes_written::total 897536 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory
system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory
system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 134776917 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 27278821 # nu
system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35528.308563 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35528.308563 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -355,11 +374,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38330500
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072128 # number of replacements
system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use
@ -403,13 +428,21 @@ system.cpu.dcache.demand_accesses::total 78000448 # nu
system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.049205 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002736 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.030475 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.030475 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 6031.763813 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 6445.578990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 6445.578990 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -445,13 +478,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6755035291
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6755035291 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026618 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026618 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2806.348172 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 33429 # number of replacements
system.cpu.l2cache.tagsinuse 18994.164700 # Cycle average of tags in use
@ -522,19 +563,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 2076226
system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.015807 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358999 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.029391 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.029391 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -573,20 +623,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500
system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015807 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358999 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.029391 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.029391 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:58
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:20:09
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.168950 # Nu
sim_ticks 168950072000 # Number of ticks simulated
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 563497 # Simulator instruction rate (inst/s)
host_op_rate 992227 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 602592819 # Simulator tick rate (ticks/s)
host_mem_usage 374808 # Number of bytes of host memory used
host_seconds 280.37 # Real time elapsed on the host
host_inst_rate 1244063 # Simulator instruction rate (inst/s)
host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1330377575 # Simulator tick rate (ticks/s)
host_mem_usage 351912 # Number of bytes of host memory used
host_seconds 126.99 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 243173115 # Number of bytes written to this memory
system.physmem.num_reads 308475658 # Number of read requests responded to by this memory
system.physmem.num_writes 31439751 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started

6
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:59
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:22:27
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.370011 # Nu
sim_ticks 370010840000 # Number of ticks simulated
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 376379 # Simulator instruction rate (inst/s)
host_op_rate 662743 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 881483751 # Simulator tick rate (ticks/s)
host_mem_usage 383736 # Number of bytes of host memory used
host_seconds 419.76 # Real time elapsed on the host
host_inst_rate 564351 # Simulator instruction rate (inst/s)
host_op_rate 993732 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1321716509 # Simulator tick rate (ticks/s)
host_mem_usage 360832 # Number of bytes of host memory used
host_seconds 279.95 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 4900800 # Number of bytes read from this memory
system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1885440 # Number of bytes written to this memory
system.physmem.num_reads 76575 # Number of read requests responded to by this memory
system.physmem.num_writes 29460 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory
system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory
system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory
system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory
system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 217696209 # nu
system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42824000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 122219201 # nu
system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 25917362500
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 49212 # number of replacements
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2066829
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000
system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -525,9 +524,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

8
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:25:50
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:38:42
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 233090215000 because target called exit()
Exiting @ tick 233057542500 because target called exit()

93
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.233058 # Nu
sim_ticks 233057542500 # Number of ticks simulated
final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 104599 # Simulator instruction rate (inst/s)
host_op_rate 117832 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47897344 # Simulator tick rate (ticks/s)
host_mem_usage 237516 # Number of bytes of host memory used
host_seconds 4865.77 # Real time elapsed on the host
host_inst_rate 102553 # Simulator instruction rate (inst/s)
host_op_rate 115527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46960535 # Simulator tick rate (ticks/s)
host_mem_usage 237172 # Number of bytes of host memory used
host_seconds 4962.84 # Real time elapsed on the host
sim_insts 508954936 # Number of instructions simulated
sim_ops 573341497 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 15214144 # Number of bytes read from this memory
system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10947904 # Number of bytes written to this memory
system.physmem.num_reads 237721 # Number of read requests responded to by this memory
system.physmem.num_writes 171061 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory
system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory
system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory
system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory
system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 126860220 # nu
system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -402,11 +421,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 171640500
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1204809 # number of replacements
system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use
@ -462,15 +487,25 @@ system.cpu.dcache.demand_accesses::total 195622115 # nu
system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -508,13 +543,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10589925497
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 218501 # number of replacements
system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use
@ -587,20 +630,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 1208896
system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -648,20 +701,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000
system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

3
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -112,9 +112,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:27:44
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:42:59
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.290499 # Nu
sim_ticks 290498972000 # Number of ticks simulated
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1142576 # Simulator instruction rate (inst/s)
host_op_rate 1287798 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 655209825 # Simulator tick rate (ticks/s)
host_mem_usage 224168 # Number of bytes of host memory used
host_seconds 443.37 # Real time elapsed on the host
host_inst_rate 2223848 # Simulator instruction rate (inst/s)
host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1275264214 # Simulator tick rate (ticks/s)
host_mem_usage 224628 # Number of bytes of host memory used
host_seconds 227.80 # Real time elapsed on the host
sim_insts 506581615 # Number of instructions simulated
sim_ops 570968176 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
system.physmem.bytes_written 216067624 # Number of bytes written to this memory
system.physmem.num_reads 641840242 # Number of read requests responded to by this memory
system.physmem.num_writes 55727847 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory
system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits

6
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@ -194,9 +193,8 @@ system=system
uid=100
[system.membus]
type=Bus
type=CoherentBus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false

6
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:17:37
gem5 started May 8 2012 16:29:57
gem5 executing on piton
gem5 compiled Jun 4 2012 12:14:06
gem5 started Jun 4 2012 17:46:58
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.722234 # Nu
sim_ticks 722234364000 # Number of ticks simulated
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 593765 # Simulator instruction rate (inst/s)
host_op_rate 669073 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 849204818 # Simulator tick rate (ticks/s)
host_mem_usage 233356 # Number of bytes of host memory used
host_seconds 850.48 # Real time elapsed on the host
host_inst_rate 1114772 # Simulator instruction rate (inst/s)
host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1594352181 # Simulator tick rate (ticks/s)
host_mem_usage 233804 # Number of bytes of host memory used
host_seconds 453.00 # Real time elapsed on the host
sim_insts 504986861 # Number of instructions simulated
sim_ops 569034848 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
system.physmem.bytes_written 11027328 # Number of bytes written to this memory
system.physmem.num_reads 231204 # Number of read requests responded to by this memory
system.physmem.num_writes 172302 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory
system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory
system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory
system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 516611385 # nu
system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 250505000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1134822 # number of replacements
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 177979623 # nu
system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 22114892000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 212089 # number of replacements
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1138918
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000
system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:59
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:27:18
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

91
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 0.459938 # Nu
sim_ticks 459937575500 # Number of ticks simulated
final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 75971 # Simulator instruction rate (inst/s)
host_op_rate 140479 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42257715 # Simulator tick rate (ticks/s)
host_mem_usage 287264 # Number of bytes of host memory used
host_seconds 10884.11 # Real time elapsed on the host
host_inst_rate 70939 # Simulator instruction rate (inst/s)
host_op_rate 131174 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39458742 # Simulator tick rate (ticks/s)
host_mem_usage 264492 # Number of bytes of host memory used
host_seconds 11656.16 # Real time elapsed on the host
sim_insts 826877144 # Number of instructions simulated
sim_ops 1528988756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 37483008 # Number of bytes read from this memory
system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory
system.physmem.bytes_written 26316864 # Number of bytes written to this memory
system.physmem.num_reads 585672 # Number of read requests responded to by this memory
system.physmem.num_writes 411201 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory
system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory
system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory
system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 919875152 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 183482871 # nu
system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -357,11 +376,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 915847000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2527239 # number of replacements
system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use
@ -405,13 +430,21 @@ system.cpu.dcache.demand_accesses::total 418117752 # nu
system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -447,13 +480,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 32037464500
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 574865 # number of replacements
system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use
@ -526,20 +567,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 2531251
system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -578,20 +629,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500
system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:58
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:38:11
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

42
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,23 +4,35 @@ sim_seconds 0.885229 # Nu
sim_ticks 885229360000 # Number of ticks simulated
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 648787 # Simulator instruction rate (inst/s)
host_op_rate 1199679 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 694571010 # Simulator tick rate (ticks/s)
host_mem_usage 243520 # Number of bytes of host memory used
host_seconds 1274.50 # Real time elapsed on the host
host_inst_rate 1285236 # Simulator instruction rate (inst/s)
host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1375933868 # Simulator tick rate (ticks/s)
host_mem_usage 220604 # Number of bytes of host memory used
host_seconds 643.37 # Real time elapsed on the host
sim_insts 826877145 # Number of instructions simulated
sim_ops 1528988757 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
system.physmem.bytes_written 991849460 # Number of bytes written to this memory
system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory
system.physmem.num_writes 149160201 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory
system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started

6
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 3 2012 13:30:44
gem5 started Jun 3 2012 13:30:58
gem5 executing on burrito
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:45:58
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

87
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,23 +4,36 @@ sim_seconds 1.658730 # Nu
sim_ticks 1658729604000 # Number of ticks simulated
final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 478704 # Simulator instruction rate (inst/s)
host_op_rate 885178 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 960288988 # Simulator tick rate (ticks/s)
host_mem_usage 252496 # Number of bytes of host memory used
host_seconds 1727.32 # Real time elapsed on the host
host_inst_rate 615589 # Simulator instruction rate (inst/s)
host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1234881669 # Simulator tick rate (ticks/s)
host_mem_usage 229524 # Number of bytes of host memory used
host_seconds 1343.23 # Real time elapsed on the host
sim_insts 826877145 # Number of instructions simulated
sim_ops 1528988757 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 37094976 # Number of bytes read from this memory
system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory
system.physmem.bytes_written 26349376 # Number of bytes written to this memory
system.physmem.num_reads 579609 # Number of read requests responded to by this memory
system.physmem.num_writes 411709 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory
system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory
system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory
system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory
system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1068347110 # nu
system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 128436000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 533262390 # nu
system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 51949140000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 568906 # number of replacements
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
@ -257,18 +298,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2518458
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -303,18 +352,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000
system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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