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inorder: update regressions for fwd-ing patch

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This commit is contained in:
Korey Sewell 2010-04-11 00:21:49 -04:00
parent b49511ae48
commit c90ee27283
6 changed files with 30 additions and 30 deletions
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6
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 27 2010 01:50:13
M5 revision e00bda288de7 7046 default qtip tip update_regrs
M5 started Mar 27 2010 01:50:14
M5 compiled Apr 10 2010 23:43:53
M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip
M5 started Apr 10 2010 23:43:54
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second

22
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 49066 # Simulator instruction rate (inst/s)
host_mem_usage 166880 # Number of bytes of host memory used
host_seconds 1800.43 # Real time elapsed on the host
host_tick_rate 58870361 # Simulator tick rate (ticks/s)
host_inst_rate 44191 # Simulator instruction rate (inst/s)
host_mem_usage 166876 # Number of bytes of host memory used
host_seconds 1999.07 # Real time elapsed on the host
host_tick_rate 53020649 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.105992 # Number of seconds simulated
@ -30,8 +30,8 @@ system.cpu.Graduation-Unit.instReqsProcessed 88340673
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed.
system.cpu.RegFile-Manager.instReqsProcessed 165553324 # Number of Instructions Requests that completed in this resource.
system.cpu.activity 85.622201 # Percentage of cycles cpu is active
system.cpu.RegFile-Manager.instReqsProcessed 165543786 # Number of Instructions Requests that completed in this resource.
system.cpu.activity 85.618119 # Percentage of cycles cpu is active
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
@ -176,7 +176,7 @@ system.cpu.icache.total_refs 99013611 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache_port.instReqsProcessed 99096235 # Number of Instructions Requests that completed in this resource.
system.cpu.idleCycles 30478636 # Number of cycles cpu's stages were not processed
system.cpu.idleCycles 30487290 # Number of cycles cpu's stages were not processed
system.cpu.ipc 0.416733 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total 0.416733 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
@ -273,7 +273,7 @@ system.cpu.l2cache.total_refs 111144 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120636 # number of writebacks
system.cpu.numCycles 211984025 # number of cpu cycles simulated
system.cpu.runCycles 181505389 # Number of cycles cpu stages are processed.
system.cpu.runCycles 181496735 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
@ -284,9 +284,9 @@ system.cpu.stage-0.utilization 46.748815 # Pe
system.cpu.stage-1.idleCycles 123634464 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 88349561 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 41.677462 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 122158701 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89825324 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 42.373629 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 122168239 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 42.369129 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 176752755 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 16.619776 # Percentage of cycles stage was utilized (processing insts).

6
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 27 2010 01:41:24
M5 revision e00bda288de7 7046 default qtip tip update_regrs
M5 started Mar 27 2010 01:46:24
M5 compiled Apr 10 2010 23:44:54
M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip
M5 started Apr 10 2010 23:44:56
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second

16
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 50762 # Simulator instruction rate (inst/s)
host_mem_usage 156288 # Number of bytes of host memory used
host_seconds 1810.49 # Real time elapsed on the host
host_tick_rate 54563823 # Simulator tick rate (ticks/s)
host_inst_rate 45830 # Simulator instruction rate (inst/s)
host_mem_usage 156280 # Number of bytes of host memory used
host_seconds 2005.28 # Real time elapsed on the host
host_tick_rate 49263361 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.098787 # Number of seconds simulated
@ -30,7 +30,7 @@ system.cpu.Graduation-Unit.instReqsProcessed 91903056
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed.
system.cpu.RegFile-Manager.instReqsProcessed 196150555 # Number of Instructions Requests that completed in this resource.
system.cpu.RegFile-Manager.instReqsProcessed 196150553 # Number of Instructions Requests that completed in this resource.
system.cpu.activity 96.136450 # Percentage of cycles cpu is active
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
@ -284,9 +284,9 @@ system.cpu.stage-0.utilization 52.274318 # Pe
system.cpu.stage-1.idleCycles 105572319 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 92001832 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 46.565723 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 104081665 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 93492486 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 47.320201 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 104081667 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 47.320200 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 171037020 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 13.431479 # Percentage of cycles stage was utilized (processing insts).

6
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 23 2010 00:24:02
M5 revision ba1ff0a71710 7040 default tip
M5 started Mar 23 2010 00:24:03
M5 compiled Apr 10 2010 23:42:32
M5 revision 1633bdfc3b0a 7062 default qtip regression_update tip
M5 started Apr 10 2010 23:42:34
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second

4
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 30611 # Simulator instruction rate (inst/s)
host_inst_rate 30166 # Simulator instruction rate (inst/s)
host_mem_usage 153332 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
host_tick_rate 149038484 # Simulator tick rate (ticks/s)
host_tick_rate 146878557 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000031 # Number of seconds simulated