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Merge with main repository.

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This commit is contained in:
Gabe Black 2012-01-07 02:10:34 -08:00
commit 36a822f08e
155 changed files with 5002 additions and 4251 deletions
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1
SConstruct
View file

@ -487,6 +487,7 @@ if main['GCC']:
# Note CCVERSION doesn't work here because it is run with the CC
# before we override it from the command line
gcc_version = readCommand([main['CXX'], '-dumpversion'], exception=False)
main['GCC_VERSION'] = gcc_version
if not compareVersions(gcc_version, '4.4.1') or \
not compareVersions(gcc_version, '4.4.2'):
print 'Info: Tree vectorizer in GCC 4.4.1 & 4.4.2 is buggy, disabling.'

2
configs/common/FSConfig.py
View file

@ -253,7 +253,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().count('android'):
boot_flags += "init=/init "
boot_flags += " init=/init "
self.boot_osflags = boot_flags
self.physmem.port = self.membus.port

18
configs/example/ruby_fs.py
View file

@ -30,18 +30,18 @@
# Full system configuraiton for ruby
#
import os
import optparse
import os
import sys
from os.path import join as joinpath
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, panic
from m5.util import addToPath, fatal
if not buildEnv['FULL_SYSTEM']:
panic("This script requires full-system mode (*_FS).")
fatal("This script requires full-system mode (*_FS).")
addToPath('../common')
addToPath('../ruby')
@ -60,7 +60,9 @@ config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
parser = optparse.OptionParser()
# System options
parser.add_option("--kernel", action="store", type="string")
parser.add_option("--script", action="store", type="string")
# Benchmark options
parser.add_option("-b", "--benchmark", action="store", type="string",
dest="benchmark",
@ -117,9 +119,15 @@ elif buildEnv['TARGET_ISA'] == "x86":
else:
fatal("incapable of building non-alpha or non-x86 full system!")
Ruby.create_system(options, system, system.piobus, system._dma_devices)
if options.kernel is not None:
system.kernel = binary(options.kernel)
if options.script is not None:
system.readfile = options.script
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_devices)
for (i, cpu) in enumerate(system.cpu):
#

10
configs/ruby/Ruby.py
View file

@ -40,6 +40,8 @@ def define_options(parser):
help="the number of rows in the mesh topology")
parser.add_option("--garnet-network", type="string", default=None,
help="'fixed'|'flexible'")
parser.add_option("--network-fault-model", action="store_true", default=False,
help="enable network fault model: see src/mem/ruby/network/fault_model/")
# ruby mapping options
parser.add_option("--numa-high-bit", type="int", default=0,
@ -109,7 +111,13 @@ def create_system(options, system, piobus = None, dma_devices = []):
print "Error: could not create topology %s" % options.topology
raise
network = NetworkClass(ruby_system = ruby, topology = net_topology)
if options.network_fault_model:
assert(options.garnet_network == "fixed")
fault_model = FaultModel()
network = NetworkClass(ruby_system = ruby, topology = net_topology,\
enable_fault_model=True, fault_model = fault_model)
else:
network = NetworkClass(ruby_system = ruby, topology = net_topology)
#
# Loop through the directory controlers.

117
src/SConscript
View file

@ -51,7 +51,7 @@ Export('env')
build_env = [(opt, env[opt]) for opt in export_vars]
from m5.util import code_formatter
from m5.util import code_formatter, compareVersions
########################################################################
# Code for adding source files of various types
@ -449,7 +449,13 @@ sys.meta_path.remove(importer)
sim_objects = m5.SimObject.allClasses
all_enums = m5.params.allEnums
all_params = {}
# Find param types that need to be explicitly wrapped with swig.
# These will be recognized because the ParamDesc will have a
# swig_decl() method. Most param types are based on types that don't
# need this, either because they're based on native types (like Int)
# or because they're SimObjects (which get swigged independently).
# For now the only things handled here are VectorParam types.
params_to_swig = {}
for name,obj in sorted(sim_objects.iteritems()):
for param in obj._params.local.values():
# load the ptype attribute now because it depends on the
@ -461,8 +467,8 @@ for name,obj in sorted(sim_objects.iteritems()):
if not hasattr(param, 'swig_decl'):
continue
pname = param.ptype_str
if pname not in all_params:
all_params[pname] = param
if pname not in params_to_swig:
params_to_swig[pname] = param
########################################################################
#
@ -523,24 +529,23 @@ PySource('m5', 'python/m5/info.py')
# Create all of the SimObject param headers and enum headers
#
def createSimObjectParam(target, source, env):
def createSimObjectParamStruct(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
obj = sim_objects[name]
code = code_formatter()
obj.cxx_decl(code)
obj.cxx_param_decl(code)
code.write(target[0].abspath)
def createSwigParam(target, source, env):
def createParamSwigWrapper(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
param = all_params[name]
param = params_to_swig[name]
code = code_formatter()
code('%module(package="m5.internal") $0_${name}', param.file_ext)
param.swig_decl(code)
code.write(target[0].abspath)
@ -554,7 +559,7 @@ def createEnumStrings(target, source, env):
obj.cxx_def(code)
code.write(target[0].abspath)
def createEnumParam(target, source, env):
def createEnumDecls(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
@ -564,25 +569,25 @@ def createEnumParam(target, source, env):
obj.cxx_decl(code)
code.write(target[0].abspath)
def createEnumSwig(target, source, env):
def createEnumSwigWrapper(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
obj = all_enums[name]
code = code_formatter()
code('''\
%module(package="m5.internal") enum_$name
%{
#include "enums/$name.hh"
%}
%include "enums/$name.hh"
''')
obj.swig_decl(code)
code.write(target[0].abspath)
# Generate all of the SimObject param struct header files
def createSimObjectSwigWrapper(target, source, env):
name = source[0].get_contents()
obj = sim_objects[name]
code = code_formatter()
obj.swig_decl(code)
code.write(target[0].abspath)
# Generate all of the SimObject param C++ struct header files
params_hh_files = []
for name,simobj in sorted(sim_objects.iteritems()):
py_source = PySource.modules[simobj.__module__]
@ -591,16 +596,16 @@ for name,simobj in sorted(sim_objects.iteritems()):
hh_file = File('params/%s.hh' % name)
params_hh_files.append(hh_file)
env.Command(hh_file, Value(name),
MakeAction(createSimObjectParam, Transform("SO PARAM")))
MakeAction(createSimObjectParamStruct, Transform("SO PARAM")))
env.Depends(hh_file, depends + extra_deps)
# Generate any parameter header files needed
# Generate any needed param SWIG wrapper files
params_i_files = []
for name,param in all_params.iteritems():
i_file = File('python/m5/internal/%s_%s.i' % (param.file_ext, name))
for name,param in params_to_swig.iteritems():
i_file = File('python/m5/internal/%s.i' % (param.swig_module_name()))
params_i_files.append(i_file)
env.Command(i_file, Value(name),
MakeAction(createSwigParam, Transform("SW PARAM")))
MakeAction(createParamSwigWrapper, Transform("SW PARAM")))
env.Depends(i_file, depends)
SwigSource('m5.internal', i_file)
@ -617,54 +622,22 @@ for name,enum in sorted(all_enums.iteritems()):
hh_file = File('enums/%s.hh' % name)
env.Command(hh_file, Value(name),
MakeAction(createEnumParam, Transform("EN PARAM")))
MakeAction(createEnumDecls, Transform("ENUMDECL")))
env.Depends(hh_file, depends + extra_deps)
i_file = File('python/m5/internal/enum_%s.i' % name)
env.Command(i_file, Value(name),
MakeAction(createEnumSwig, Transform("ENUMSWIG")))
MakeAction(createEnumSwigWrapper, Transform("ENUMSWIG")))
env.Depends(i_file, depends + extra_deps)
SwigSource('m5.internal', i_file)
def buildParam(target, source, env):
name = source[0].get_contents()
obj = sim_objects[name]
class_path = obj.cxx_class.split('::')
classname = class_path[-1]
namespaces = class_path[:-1]
params = obj._params.local.values()
code = code_formatter()
code('%module(package="m5.internal") param_$name')
code()
code('%{')
code('#include "params/$obj.hh"')
for param in params:
param.cxx_predecls(code)
code('%}')
code()
for param in params:
param.swig_predecls(code)
code()
if obj._base:
code('%import "python/m5/internal/param_${{obj._base}}.i"')
code()
obj.swig_objdecls(code)
code()
code('%include "params/$obj.hh"')
code.write(target[0].abspath)
# Generate SimObject SWIG wrapper files
for name in sim_objects.iterkeys():
params_file = File('python/m5/internal/param_%s.i' % name)
env.Command(params_file, Value(name),
MakeAction(buildParam, Transform("BLDPARAM")))
env.Depends(params_file, depends)
SwigSource('m5.internal', params_file)
i_file = File('python/m5/internal/param_%s.i' % name)
env.Command(i_file, Value(name),
MakeAction(createSimObjectSwigWrapper, Transform("SO SWIG")))
env.Depends(i_file, depends)
SwigSource('m5.internal', i_file)
# Generate the main swig init file
def makeEmbeddedSwigInit(target, source, env):
@ -687,7 +660,7 @@ for swig in SwigSource.all:
MakeAction('$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
'-o ${TARGETS[0]} $SOURCES', Transform("SWIG")))
cc_file = str(swig.tnode)
init_file = '%s/init_%s.cc' % (dirname(cc_file), basename(cc_file))
init_file = '%s/%s_init.cc' % (dirname(cc_file), basename(cc_file))
env.Command(init_file, Value(swig.module),
MakeAction(makeEmbeddedSwigInit, Transform("EMBED SW")))
Source(init_file, **swig.guards)
@ -878,6 +851,9 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
swig_env.Append(CCFLAGS='-Wno-uninitialized')
swig_env.Append(CCFLAGS='-Wno-sign-compare')
swig_env.Append(CCFLAGS='-Wno-parentheses')
if compareVersions(env['GCC_VERSION'], '4.6.0') != -1:
swig_env.Append(CCFLAGS='-Wno-unused-label')
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')
@ -904,9 +880,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
return obj
sources = Source.get(main=False, skip_lib=False)
static_objs = [ make_obj(s, True) for s in sources ]
shared_objs = [ make_obj(s, False) for s in sources ]
static_objs = \
[ make_obj(s, True) for s in Source.get(main=False, skip_lib=False) ]
shared_objs = \
[ make_obj(s, False) for s in Source.get(main=False, skip_lib=False) ]
static_date = make_obj(date_source, static=True, extra_deps=static_objs)
static_objs.append(static_date)

7
src/arch/alpha/ev5.cc
View file

@ -202,8 +202,6 @@ int break_ipl = -1;
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
if (tc->misspeculating())
return;
@ -255,10 +253,9 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
case IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
if (tc->getKernelStats())
tc->getKernelStats()->context(old, val, tc);
tc->getKernelStats()->context(ipr[idx], val, tc);
ipr[idx] = val;
break;
case IPR_DTB_PTE:

2
src/arch/alpha/isa/mem.isa
View file

@ -388,7 +388,7 @@ def template MiscExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Addr EA M5_VAR_USED;
Fault fault = NoFault;
%(fp_enable_check)s;

1
src/arch/alpha/linux/linux.hh
View file

@ -69,6 +69,7 @@ class AlphaLinux : public Linux
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x10;
static const unsigned TGT_MAP_FIXED = 0x100;
//@{
/// For getsysinfo().

2
src/arch/alpha/process.cc
View file

@ -126,7 +126,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
stack_min = roundDown(stack_min, pageSize);
stack_size = stack_base - stack_min;
// map memory
pTable->allocate(stack_min, roundUp(stack_size, pageSize));
allocateMem(stack_min, roundUp(stack_size, pageSize));
// map out initial stack contents
Addr argv_array_base = stack_min + intSize; // room for argc

1
src/arch/alpha/tru64/tru64.hh
View file

@ -64,6 +64,7 @@ class AlphaTru64 : public Tru64
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x10;
static const unsigned TGT_MAP_FIXED = 0x100;
//@{
/// For getsysinfo().

18
src/arch/arm/isa/formats/fp.isa
View file

@ -561,20 +561,22 @@ let {{
}
}
case 0xa:
if (q)
return new Unknown(machInst);
if (b) {
return decodeNeonUSThreeReg<VpminD, VpminQ>(
q, u, size, machInst, vd, vn, vm);
return decodeNeonUSThreeUSReg<VpminD>(
u, size, machInst, vd, vn, vm);
} else {
return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>(
q, u, size, machInst, vd, vn, vm);
return decodeNeonUSThreeUSReg<VpmaxD>(
u, size, machInst, vd, vn, vm);
}
case 0xb:
if (b) {
if (u) {
if (u || q) {
return new Unknown(machInst);
} else {
return decodeNeonUThreeReg<NVpaddD, NVpaddQ>(
q, size, machInst, vd, vn, vm);
return decodeNeonUThreeUSReg<NVpaddD>(
size, machInst, vd, vn, vm);
}
} else {
if (u) {
@ -1542,7 +1544,7 @@ let {{
else
return new NVswpD<uint64_t>(machInst, vd, vm);
case 0x1:
return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>(
return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>(
q, size, machInst, vd, vm);
case 0x2:
return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>(

4
src/arch/arm/isa/insts/fp.isa
View file

@ -447,7 +447,7 @@ let {{
exec_output = ""
singleSimpleCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
FpDest = %(op)s;
'''
singleCode = singleSimpleCode + '''
@ -457,7 +457,7 @@ let {{
"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
doubleCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
double dest = %(op)s;
FpDestP0_uw = dblLow(dest);
FpDestP1_uw = dblHi(dest);

7
src/arch/arm/isa/insts/macromem.isa
View file

@ -563,15 +563,16 @@ let {{
let {{
exec_output = ''
for type in ('uint8_t', 'uint16_t', 'uint32_t'):
for typeSize in (8, 16, 32):
for sRegs in 1, 2:
for dRegs in range(sRegs, 5):
for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)):
for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
"MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
"MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
Name = format % { "sRegs" : sRegs * 2,
"dRegs" : dRegs * 2 }
substDict = { "class_name" : Name, "targs" : type }
substDict = { "class_name" : Name,
"targs" : "uint%d_t" % typeSize }
exec_output += MicroNeonExecDeclare.subst(substDict)
}};

16
src/arch/arm/isa/insts/neon.isa
View file

@ -1616,10 +1616,8 @@ let {{
threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
2, vaddCode, pairwise=True)
threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
4, vaddCode, pairwise=True)
vaddlwCode = '''
destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
'''
@ -2110,11 +2108,9 @@ let {{
'''
threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
vqdmulhCode = '''
FPSCR fpscr = (FPSCR) FpscrQc;
@ -3137,8 +3133,10 @@ let {{
destReg.elements[i + 1] = mid;
}
'''
twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
smallUnsignedTypes, 2, vtrnCode)
twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
smallUnsignedTypes, 4, vtrnCode)
vuzpCode = '''
Element mid[eCount];

4
src/arch/arm/isa/templates/mem.isa
View file

@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{
(IntRegIndex)_index)
{
%(constructor)s;
bool conditional = false;
bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
bool conditional = false;
bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {

1
src/arch/arm/linux/linux.hh
View file

@ -91,6 +91,7 @@ class ArmLinux : public Linux
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
//@{
/// For getrusage().

2
src/arch/arm/linux/process.cc
View file

@ -503,7 +503,7 @@ void
ArmLinuxProcess::initState()
{
ArmLiveProcess::initState();
pTable->allocate(commPage, PageBytes);
allocateMem(commPage, PageBytes);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
uint8_t swiNeg1[] = {

3
src/arch/arm/process.cc
View file

@ -251,8 +251,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize)
stack_size = stack_base - stack_min;
// map memory
pTable->allocate(roundDown(stack_min, pageSize),
roundUp(stack_size, pageSize));
allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
// map out initial stack contents
uint32_t sentry_base = stack_base - sentry_size;

8
src/arch/mips/isa/decoder.isa
View file

@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: mttc1({{
uint64_t data = xc->readRegOtherThread(RD +
FP_Base_DepTag);
data = insertBits(data, top_bit,
bottom_bit, Rt);
data = insertBits(data, MT_H ? 63 : 31,
MT_H ? 32 : 0, Rt);
xc->setRegOtherThread(RD + FP_Base_DepTag,
data);
}});
@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
panic("FP Control Value (%d) "
"Not Available. Ignoring "
"Access to Floating Control "
"Status Register", FS);
"S""tatus Register", FS);
}
xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
}});
@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() {
bits(pageGrain, pageGrain.esp) == 1) {
SP = 1;
}
IndexReg index = Index;
Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
}});
0x06: tlbwr({{
@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() {
bits(pageGrain, pageGrain.esp) == 1) {
SP = 1;
}
IndexReg index = Index;
Ptr->insertAt(newEntry, Random, SP);
}});

22
src/arch/mips/isa/formats/mt.isa
View file

@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
int64_t data;
int64_t data M5_VAR_USED;
%(op_decl)s;
%(op_rd)s;
@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{
} else if (vpeControl.targTC > mvpConf0.ptc) {
data = -1;
} else {
int top_bit = 0;
int bottom_bit = 0;
if (MT_H == 1) {
top_bit = 63;
bottom_bit = 32;
} else {
top_bit = 31;
bottom_bit = 0;
}
%(code)s;
}
} else {
@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{
flags += ('IsNonSpeculative', )
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
code += 'if (MT_H == 1) {\n'
code += 'data = bits(data, top_bit, bottom_bit);\n'
code += '}\n'
code += 'Rd = data;\n'
code += '''
if (MT_H)
data = bits(data, 63, 32);
Rd = data;
'''
iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)

2
src/arch/mips/isa/includes.isa
View file

@ -52,7 +52,9 @@ output decoder {{
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/loader/symtab.hh"
#include "base/cprintf.hh"

1
src/arch/mips/linux/linux.hh
View file

@ -65,6 +65,7 @@ class MipsLinux : public Linux
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x800;
static const unsigned TGT_MAP_FIXED = 0x10;
//@{
/// For getsysinfo().

2
src/arch/mips/process.cc
View file

@ -136,7 +136,7 @@ MipsLiveProcess::argsInit(int pageSize)
stack_min = roundDown(stack_min, pageSize);
stack_size = stack_base - stack_min;
// map memory
pTable->allocate(stack_min, roundUp(stack_size, pageSize));
allocateMem(stack_min, roundUp(stack_size, pageSize));
// map out initial stack contents
IntType argv_array_base = stack_min + intSize; // room for argc

2
src/arch/mips/tlb.cc
View file

@ -129,7 +129,6 @@ int
TLB::probeEntry(Addr vpn, uint8_t asn) const
{
// assume not found...
PTE *retval = NULL;
int Ind = -1;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
if (((vpn & InvMask) == (VPN & InvMask)) &&
(pte->G || (asn == pte->asid))) {
// We have a VPN + ASID Match
retval = pte;
Ind = index;
break;
}

2
src/arch/power/isa/formats/mem.isa
View file

@ -123,7 +123,7 @@ def template LoadCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Addr M5_VAR_USED EA;
Fault fault = NoFault;
%(op_decl)s;

1
src/arch/power/linux/linux.hh
View file

@ -127,6 +127,7 @@ class PowerLinux : public Linux
/// For mmap().
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
//@{
/// ioctl() command codes.

3
src/arch/power/process.cc
View file

@ -187,8 +187,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize)
stack_size = stack_base - stack_min;
// map memory
pTable->allocate(roundDown(stack_min, pageSize),
roundUp(stack_size, pageSize));
allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
// map out initial stack contents
uint32_t sentry_base = stack_base - sentry_size;

2
src/arch/power/tlb.cc
View file

@ -119,7 +119,6 @@ int
TLB::probeEntry(Addr vpn,uint8_t asn) const
{
// assume not found...
PowerISA::PTE *retval = NULL;
int Ind = -1;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
@ -133,7 +132,6 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const
&& (pte->G || (asn == pte->asid))) {
// We have a VPN + ASID Match
retval = pte;
Ind = index;
break;
}

4
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -326,8 +326,8 @@ let {{
'''
TruncateEA = '''
if (!FullSystem)
EA = Pstate<3:> ? EA<31:0> : EA;
if (!FullSystem)
EA = Pstate<3:> ? EA<31:0> : EA;
'''
}};

1
src/arch/sparc/linux/linux.hh
View file

@ -77,6 +77,7 @@ class SparcLinux : public Linux
static const int NUM_OPEN_FLAGS;
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
typedef struct {
int64_t uptime; /* Seconds since boot */

3
src/arch/sparc/process.cc
View file

@ -316,8 +316,7 @@ SparcLiveProcess::argsInit(int pageSize)
stack_size = stack_base - stack_min;
// Allocate space for the stack
pTable->allocate(roundDown(stack_min, pageSize),
roundUp(stack_size, pageSize));
allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
// map out initial stack contents
IntType sentry_base = stack_base - sentry_size;

1
src/arch/sparc/solaris/solaris.hh
View file

@ -59,6 +59,7 @@ class SparcSolaris : public Solaris
static const int NUM_OPEN_FLAGS;
static const unsigned TGT_MAP_ANONYMOUS = 0x100;
static const unsigned TGT_MAP_FIXED = 0x10;
};
#endif

36
src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
View file

@ -67,18 +67,22 @@ def macroop ADD_P_I
def macroop ADD_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADD_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADD_M_R
@ -98,17 +102,21 @@ def macroop ADD_P_R
def macroop ADD_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADD_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADD_R_M
@ -168,18 +176,22 @@ def macroop SUB_P_I
def macroop SUB_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SUB_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop SUB_M_R
@ -199,17 +211,21 @@ def macroop SUB_P_R
def macroop SUB_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SUB_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_R_R
@ -243,18 +259,22 @@ def macroop ADC_P_I
def macroop ADC_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADC_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_M_R
@ -274,17 +294,21 @@ def macroop ADC_P_R
def macroop ADC_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADC_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_R_M
@ -344,18 +368,22 @@ def macroop SBB_P_I
def macroop SBB_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SBB_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop SBB_M_R
@ -375,17 +403,21 @@ def macroop SBB_P_R
def macroop SBB_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SBB_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop NEG_R
@ -410,16 +442,20 @@ def macroop NEG_P
def macroop NEG_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
stul t1, seg, sib, disp
mfence
};
def macroop NEG_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
stul t1, seg, riprel, disp
mfence
};
'''

8
src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
View file

@ -58,17 +58,21 @@ def macroop INC_P
def macroop INC_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, sib, disp
mfence
};
def macroop INC_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, riprel, disp
mfence
};
def macroop DEC_R
@ -93,16 +97,20 @@ def macroop DEC_P
def macroop DEC_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, sib, disp
mfence
};
def macroop DEC_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, riprel, disp
mfence
};
'''

24
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
View file

@ -114,10 +114,12 @@ def macroop BTC_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTC_LOCKED_P_I {
@ -125,10 +127,12 @@ def macroop BTC_LOCKED_P_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTC_R_R {
@ -168,10 +172,12 @@ def macroop BTC_LOCKED_M_R {
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTC_LOCKED_P_R {
@ -180,10 +186,12 @@ def macroop BTC_LOCKED_P_R {
srai t3, t2, ldsz, dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
stul t1, seg, [dsz, t3, t7], disp
mfence
};
def macroop BTR_R_I {
@ -218,10 +226,12 @@ def macroop BTR_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTR_LOCKED_P_I {
@ -229,10 +239,12 @@ def macroop BTR_LOCKED_P_I {
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTR_R_R {
@ -272,10 +284,12 @@ def macroop BTR_LOCKED_M_R {
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTR_LOCKED_P_R {
@ -284,10 +298,12 @@ def macroop BTR_LOCKED_P_R {
srai t3, t2, ldsz, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
mfence
ldstl t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
stul t1, seg, [dsz, t3, t7], disp
mfence
};
def macroop BTS_R_I {
@ -322,10 +338,12 @@ def macroop BTS_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTS_LOCKED_P_I {
@ -333,10 +351,12 @@ def macroop BTS_LOCKED_P_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTS_R_R {
@ -377,10 +397,12 @@ def macroop BTS_LOCKED_M_R {
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTS_LOCKED_P_R {
@ -390,9 +412,11 @@ def macroop BTS_LOCKED_P_R {
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [1, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
stul t1, seg, [1, t3, t7], disp
mfence
};
'''

12
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
View file

@ -50,46 +50,58 @@ def macroop XCHG_R_R
def macroop XCHG_R_M
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_M_R
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
'''

28
src/arch/x86/isa/insts/general_purpose/logical.py
View file

@ -61,18 +61,22 @@ def macroop OR_P_I
def macroop OR_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop OR_LOCKED_P_I
{
limm t2, imm
rdip t7
mfence
ldstl t1, seg, riprel, disp
or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop OR_M_R
@ -92,17 +96,21 @@ def macroop OR_P_R
def macroop OR_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop OR_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop OR_R_M
@ -155,18 +163,22 @@ def macroop XOR_P_I
def macroop XOR_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop XOR_LOCKED_P_I
{
limm t2, imm
rdip t7
mfence
ldstl t1, seg, riprel, disp
xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop XOR_M_R
@ -186,17 +198,21 @@ def macroop XOR_P_R
def macroop XOR_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop XOR_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop XOR_R_M
@ -255,19 +271,23 @@ def macroop AND_P_I
def macroop AND_LOCKED_M_I
{
mfence
ldstl t2, seg, sib, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
stul t2, seg, sib, disp
mfence
};
def macroop AND_LOCKED_P_I
{
rdip t7
mfence
ldstl t2, seg, riprel, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
stul t2, seg, riprel, disp
mfence
};
def macroop AND_M_R
@ -287,17 +307,21 @@ def macroop AND_P_R
def macroop AND_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop AND_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop NOT_R
@ -326,17 +350,21 @@ def macroop NOT_P
def macroop NOT_LOCKED_M
{
limm t1, -1
mfence
ldstl t2, seg, sib, disp
xor t2, t2, t1
stul t2, seg, sib, disp
mfence
};
def macroop NOT_LOCKED_P
{
limm t1, -1
rdip t7
mfence
ldstl t2, seg, riprel, disp
xor t2, t2, t1
stul t2, seg, riprel, disp
mfence
};
'''

8
src/arch/x86/isa/insts/general_purpose/semaphores.py
View file

@ -62,21 +62,25 @@ def macroop CMPXCHG_P_R {
};
def macroop CMPXCHG_LOCKED_M_R {
mfence
ldstl t1, seg, sib, disp
sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
mov t1, t1, reg, flags=(CZF,)
stul t1, seg, sib, disp
mfence
mov rax, rax, t1, flags=(nCZF,)
};
def macroop CMPXCHG_LOCKED_P_R {
rdip t7
mfence
ldstl t1, seg, riprel, disp
sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
mov t1, t1, reg, flags=(CZF,)
stul t1, seg, riprel, disp
mfence
mov rax, rax, t1, flags=(nCZF,)
};
@ -96,17 +100,21 @@ def macroop XADD_P_R {
};
def macroop XADD_LOCKED_M_R {
mfence
ldstl t1, seg, sib, disp
add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t2, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XADD_LOCKED_P_R {
rdip t7
mfence
ldstl t1, seg, riprel, disp
add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t2, seg, riprel, disp
mfence
mov reg, reg, t1
};

3
src/arch/x86/isa/microops/base.isa
View file

@ -59,7 +59,8 @@ let {{
''' + generatorNameTemplate + '''(StaticInstPtr curMacroop)
{
static const char *macrocodeBlock = romMnemonic;
static const ExtMachInst dummyExtMachInst;
static const ExtMachInst dummyExtMachInst = \
X86ISA::NoopMachInst;
static const EmulEnv dummyEmulEnv(0, 0, 1, 1, 1);
Macroop * macroop = dynamic_cast<Macroop *>(curMacroop.get());

53
src/arch/x86/isa/microops/specop.isa
View file

@ -1,4 +1,5 @@
// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// Copyright (c) 2011 Mark D. Hill and David A. Wood
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
@ -203,3 +204,55 @@ let {{
microopClasses["halt"] = Halt
}};
def template MicroFenceOpDeclare {{
class %(class_name)s : public X86ISA::X86MicroopBase
{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
uint64_t setFlags);
%(BasicExecDeclare)s
};
}};
def template MicroFenceOpConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem, uint64_t setFlags) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
setFlags, %(op_class)s)
{
%(constructor)s;
}
}};
let {{
class MfenceOp(X86Microop):
def __init__(self):
self.className = "Mfence"
self.mnemonic = "mfence"
self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)"
def getAllocator(self, microFlags):
allocString = '''
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s))
'''
allocator = allocString % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
"flags" : self.microFlagsText(microFlags) + self.instFlags}
return allocator
microopClasses["mfence"] = MfenceOp
}};
let {{
# Build up the all register version of this micro op
iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase',
{"code" : ""})
header_output += MicroFenceOpDeclare.subst(iop)
decoder_output += MicroFenceOpConstructor.subst(iop)
exec_output += BasicExecute.subst(iop)
}};

2
src/arch/x86/linux/linux.hh
View file

@ -88,6 +88,7 @@ class X86Linux64 : public Linux
static const int NUM_OPEN_FLAGS;
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
typedef struct {
uint64_t iov_base; // void *
@ -158,6 +159,7 @@ class X86Linux32 : public Linux
static const int NUM_OPEN_FLAGS;
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
typedef struct {
int32_t uptime; /* Seconds since boot */

9
src/arch/x86/process.cc
View file

@ -167,7 +167,7 @@ X86_64LiveProcess::initState()
argsInit(sizeof(uint64_t), VMPageSize);
// Set up the vsyscall page for this process.
pTable->allocate(vsyscallPage.base, vsyscallPage.size);
allocateMem(vsyscallPage.base, vsyscallPage.size);
uint8_t vtimeBlob[] = {
0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
0x0f,0x05, // syscall
@ -265,7 +265,7 @@ I386LiveProcess::initState()
* Set up a GDT for this process. The whole GDT wouldn't really be for
* this process, but the only parts we care about are.
*/
pTable->allocate(_gdtStart, _gdtSize);
allocateMem(_gdtStart, _gdtSize);
uint64_t zero = 0;
assert(_gdtSize % sizeof(zero) == 0);
for (Addr gdtCurrent = _gdtStart;
@ -274,7 +274,7 @@ I386LiveProcess::initState()
}
// Set up the vsyscall page for this process.
pTable->allocate(vsyscallPage.base, vsyscallPage.size);
allocateMem(vsyscallPage.base, vsyscallPage.size);
uint8_t vsyscallBlob[] = {
0x51, // push %ecx
0x52, // push %edp
@ -577,8 +577,7 @@ X86LiveProcess::argsInit(int pageSize,
stack_size = stack_base - stack_min;
// map memory
pTable->allocate(roundDown(stack_min, pageSize),
roundUp(stack_size, pageSize));
allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
// map out initial stack contents
IntType sentry_base = stack_base - sentry_size;

1
src/base/inet.cc
View file

@ -30,6 +30,7 @@
* Gabe Black
*/
#include <cstddef>
#include <cstdio>
#include <sstream>
#include <string>

3
src/cpu/base.cc
View file

@ -234,8 +234,7 @@ BaseCPU::startup()
if (params()->progress_interval) {
Tick num_ticks = ticks(params()->progress_interval);
Event *event;
event = new CPUProgressEvent(this, num_ticks);
new CPUProgressEvent(this, num_ticks);
}
}

3
src/cpu/inorder/cpu.cc
View file

@ -206,7 +206,6 @@ InOrderCPU::InOrderCPU(Params *params)
lastRunningCycle(0),
instsPerSwitch(0)
{
ThreadID active_threads;
cpu_params = params;
resPool = new ResourcePool(this, params);
@ -214,6 +213,7 @@ InOrderCPU::InOrderCPU(Params *params)
// Resize for Multithreading CPUs
thread.resize(numThreads);
ThreadID active_threads = params->workload.size();
if (FullSystem) {
active_threads = 1;
} else {
@ -1110,7 +1110,6 @@ InOrderCPU::updateThreadPriority()
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;

2
src/cpu/legiontrace.cc
View file

@ -158,7 +158,7 @@ Trace::LegionTraceRecord::dump()
bool diffTnpc = false;
bool diffTstate = false;
bool diffTt = false;
bool diffTba = false;
bool diffTba M5_VAR_USED = false;
bool diffHpstate = false;
bool diffHtstate = false;
bool diffHtba = false;

1
src/cpu/o3/cpu.cc
View file

@ -1639,7 +1639,6 @@ FullO3CPU<Impl>::updateThreadPriority()
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;

16
src/cpu/o3/rename_impl.hh
View file

@ -1214,24 +1214,16 @@ template <class Impl>
void
DefaultRename<Impl>::readFreeEntries(ThreadID tid)
{
bool updated = false;
if (fromIEW->iewInfo[tid].usedIQ) {
freeEntries[tid].iqEntries =
fromIEW->iewInfo[tid].freeIQEntries;
updated = true;
}
if (fromIEW->iewInfo[tid].usedIQ)
freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
if (fromIEW->iewInfo[tid].usedLSQ) {
freeEntries[tid].lsqEntries =
fromIEW->iewInfo[tid].freeLSQEntries;
updated = true;
}
if (fromIEW->iewInfo[tid].usedLSQ)
freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
if (fromCommit->commitInfo[tid].usedROB) {
freeEntries[tid].robEntries =
fromCommit->commitInfo[tid].freeROBEntries;
emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
updated = true;
}
DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",

1
src/cpu/testers/rubytest/Check.hh
View file

@ -37,7 +37,6 @@
#include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
class SubBlock;

28
src/dev/io_device.cc
View file

@ -75,6 +75,18 @@ PioDevice::init()
pioPort->sendStatusChange(Port::RangeChange);
}
Port *
PioDevice::getPort(const std::string &if_name, int idx)
{
if (if_name == "pio") {
if (pioPort != NULL)
fatal("%s: pio port already connected to %s",
name(), pioPort->getPeer()->name());
pioPort = new PioPort(this, sys);
return pioPort;
}
return NULL;
}
unsigned int
PioDevice::drain(Event *de)
@ -349,3 +361,19 @@ DmaDevice::~DmaDevice()
if (dmaPort)
delete dmaPort;
}
Port *
DmaDevice::getPort(const std::string &if_name, int idx)
{
if (if_name == "dma") {
if (dmaPort != NULL)
fatal("%s: dma port already connected to %s",
name(), dmaPort->getPeer()->name());
dmaPort = new DmaPort(this, sys, params()->min_backoff_delay,
params()->max_backoff_delay);
return dmaPort;
}
return PioDevice::getPort(if_name, idx);
}

32
src/dev/io_device.hh
View file

@ -209,17 +209,8 @@ class PioDevice : public MemObject
virtual unsigned int drain(Event *de);
virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
fatal("%s: pio port already connected to %s",
name(), pioPort->getPeer()->name());
pioPort = new PioPort(this, sys);
return pioPort;
} else
return NULL;
}
virtual Port *getPort(const std::string &if_name, int idx = -1);
friend class PioPort;
};
@ -285,24 +276,7 @@ class DmaDevice : public PioDevice
unsigned cacheBlockSize() const { return dmaPort->cacheBlockSize(); }
virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
fatal("%s: pio port already connected to %s",
name(), pioPort->getPeer()->name());
pioPort = new PioPort(this, sys);
return pioPort;
} else if (if_name == "dma") {
if (dmaPort != NULL)
fatal("%s: dma port already connected to %s",
name(), dmaPort->getPeer()->name());
dmaPort = new DmaPort(this, sys, params()->min_backoff_delay,
params()->max_backoff_delay);
return dmaPort;
} else
return NULL;
}
virtual Port *getPort(const std::string &if_name, int idx = -1);
friend class DmaPort;
};

2
src/dev/mc146818.cc
View file

@ -217,7 +217,7 @@ MC146818::serialize(const string &base, ostream &os)
//
Tick rtcTimerInterruptTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
Tick rtcClockTickOffset = event.when() - curTick();
Tick rtcClockTickOffset = tickEvent.when() - curTick();
SERIALIZE_SCALAR(rtcClockTickOffset);
}

4
src/kern/tru64/tru64.hh
View file

@ -557,7 +557,7 @@ class Tru64 : public OperatingSystem
stack_base, stack_size);
// map memory
process->pTable->allocate(rounded_stack_base, rounded_stack_size);
process->allocateMem(rounded_stack_base, rounded_stack_size);
argp->address = gtoh(rounded_stack_base);
argp.copyOut(tc->getMemPort());
@ -676,7 +676,7 @@ class Tru64 : public OperatingSystem
// Register this as a valid address range with the process
base_addr = roundDown(base_addr, VMPageSize);
int size = cur_addr - base_addr;
process->pTable->allocate(base_addr, roundUp(size, VMPageSize));
process->allocateMem(base_addr, roundUp(size, VMPageSize));
config.copyOut(tc->getMemPort());
slot_state.copyOut(tc->getMemPort());

5
src/mem/SConscript
View file

@ -65,10 +65,11 @@ DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubyStorebuffer')
DebugFlag('RubyTester')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
'RubyMemory', 'RubyDma', 'RubyPort'])
'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer'])

2
src/mem/cache/tags/iic.cc vendored
View file

@ -393,10 +393,8 @@ IIC::freeReplacementBlock(PacketList & writebacks)
unsigned long
IIC::getFreeDataBlock(PacketList & writebacks)
{
struct IICTag *tag_ptr;
unsigned long data_ptr;
tag_ptr = NULL;
/* find data block */
while (blkFreelist.empty()) {
freeReplacementBlock(writebacks);

45
src/mem/page_table.cc
View file

@ -45,16 +45,14 @@
#include "debug/MMU.hh"
#include "mem/page_table.hh"
#include "sim/faults.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
PageTable::PageTable(Process *_process, Addr _pageSize)
PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
process(_process)
pid(_pid), _name(__name)
{
assert(isPowerOf2(pageSize));
pTableCache[0].vaddr = 0;
@ -67,24 +65,20 @@ PageTable::~PageTable()
}
void
PageTable::allocate(Addr vaddr, int64_t size)
PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
{
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
PTableItr iter = pTable.find(vaddr);
if (iter != pTable.end()) {
for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
if (!clobber && (pTable.find(vaddr) != pTable.end())) {
// already mapped
fatal("PageTable::allocate: address 0x%x already mapped",
vaddr);
fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
}
pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
process->system->new_page());
pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
updateCache(vaddr, pTable[vaddr]);
}
}
@ -111,11 +105,11 @@ PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
}
void
PageTable::deallocate(Addr vaddr, int64_t size)
PageTable::unmap(Addr vaddr, int64_t size)
{
assert(pageOffset(vaddr) == 0);
DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
PTableItr iter = pTable.find(vaddr);
@ -127,6 +121,21 @@ PageTable::deallocate(Addr vaddr, int64_t size)
}
bool
PageTable::isUnmapped(Addr vaddr, int64_t size)
{
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
if (pTable.find(vaddr) != pTable.end()) {
return false;
}
}
return true;
}
bool
PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
{
@ -196,7 +205,7 @@ PageTable::serialize(std::ostream &os)
PTableItr iter = pTable.begin();
PTableItr end = pTable.end();
while (iter != end) {
os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
paramOut(os, "vaddr", iter->first);
iter->second.serialize(os);
@ -219,9 +228,9 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
TheISA::TlbEntry *entry;
Addr vaddr;
paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
entry = new TheISA::TlbEntry();
entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
pTable[vaddr] = *entry;
++i;
}

23
src/mem/page_table.hh
View file

@ -46,8 +46,6 @@
#include "mem/request.hh"
#include "sim/serialize.hh"
class Process;
/**
* Page Table Declaration.
*/
@ -68,20 +66,33 @@ class PageTable
const Addr pageSize;
const Addr offsetMask;
Process *process;
const uint64_t pid;
const std::string _name;
public:
PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
PageTable(const std::string &__name, uint64_t _pid,
Addr _pageSize = TheISA::VMPageSize);
~PageTable();
// for DPRINTF compatibility
const std::string name() const { return _name; }
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
Addr pageOffset(Addr a) { return (a & offsetMask); }
void allocate(Addr vaddr, int64_t size);
void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
void remap(Addr vaddr, int64_t size, Addr new_vaddr);
void deallocate(Addr vaddr, int64_t size);
void unmap(Addr vaddr, int64_t size);
/**
* Check if any pages in a region are already allocated
* @param vaddr The starting virtual address of the region.
* @param size The length of the region.
* @return True if no pages in the region are mapped.
*/
bool isUnmapped(Addr vaddr, int64_t size);
/**
* Lookup function

15
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View file

@ -679,6 +679,17 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
mandatoryQueue_in.recycle();
}
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
peek(mandatoryQueue_in, RubyRequest) {
L1IcacheMemory.profileMiss(in_msg);
}
}
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
peek(mandatoryQueue_in, RubyRequest) {
L1DcacheMemory.profileMiss(in_msg);
}
}
//*****************************************************
// TRANSITIONS
@ -698,6 +709,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
oo_allocateL1DCacheBlock;
i_allocateTBE;
a_issueGETS;
uu_profileDataMiss;
k_popMandatoryQueue;
}
@ -705,6 +717,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
pp_allocateL1ICacheBlock;
i_allocateTBE;
ai_issueGETINSTR;
uu_profileInstMiss;
k_popMandatoryQueue;
}
@ -712,6 +725,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
oo_allocateL1DCacheBlock;
i_allocateTBE;
b_issueGETX;
uu_profileDataMiss;
k_popMandatoryQueue;
}
@ -729,6 +743,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
transition(S, Store, SM) {
i_allocateTBE;
c_issueUPGRADE;
uu_profileDataMiss;
k_popMandatoryQueue;
}

18
src/mem/protocol/MESI_CMP_directory-L2cache.sm
View file

@ -716,9 +716,25 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
}
}
GenericRequestType convertToGenericType(CoherenceRequestType type) {
if(type == CoherenceRequestType:GETS) {
return GenericRequestType:GETS;
} else if(type == CoherenceRequestType:GETX) {
return GenericRequestType:GETX;
} else if(type == CoherenceRequestType:GET_INSTR) {
return GenericRequestType:GET_INSTR;
} else if(type == CoherenceRequestType:UPGRADE) {
return GenericRequestType:UPGRADE;
} else {
DPRINTF(RubySlicc, "%s\n", type);
error("Invalid CoherenceRequestType\n");
}
}
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
//profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor));
L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
in_msg.AccessMode, in_msg.Prefetch);
}
}

1
src/mem/protocol/MESI_CMP_directory.slicc
View file

@ -5,4 +5,3 @@ include "MESI_CMP_directory-L1cache.sm";
include "MESI_CMP_directory-L2cache.sm";
include "MESI_CMP_directory-dir.sm";
include "MESI_CMP_directory-dma.sm";
include "standard_CMP-protocol.sm";

1
src/mem/protocol/MI_example.slicc
View file

@ -4,4 +4,3 @@ include "MI_example-msg.sm";
include "MI_example-cache.sm";
include "MI_example-dir.sm";
include "MI_example-dma.sm";
include "standard_1level_CMP-protocol.sm";

1
src/mem/protocol/MOESI_CMP_directory.slicc
View file

@ -5,4 +5,3 @@ include "MOESI_CMP_directory-L2cache.sm";
include "MOESI_CMP_directory-L1cache.sm";
include "MOESI_CMP_directory-dma.sm";
include "MOESI_CMP_directory-dir.sm";
include "standard_CMP-protocol.sm";

1
src/mem/protocol/MOESI_CMP_token.slicc
View file

@ -5,4 +5,3 @@ include "MOESI_CMP_token-L1cache.sm";
include "MOESI_CMP_token-L2cache.sm";
include "MOESI_CMP_token-dir.sm";
include "MOESI_CMP_token-dma.sm";
include "standard_CMP-protocol.sm";

1
src/mem/protocol/MOESI_hammer.slicc
View file

@ -4,4 +4,3 @@ include "MOESI_hammer-msg.sm";
include "MOESI_hammer-cache.sm";
include "MOESI_hammer-dir.sm";
include "MOESI_hammer-dma.sm";
include "standard_1level_CMP-protocol.sm";

22
src/mem/protocol/RubySlicc_ComponentMapping.sm
View file

@ -30,34 +30,12 @@
// Mapping functions
int machineCount(MachineType machType);
// NodeID map_address_to_node(Address addr);
MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
NetDest broadcast(MachineType type);
MachineID map_Address_to_DMA(Address addr);
MachineID map_Address_to_Directory(Address addr);
NodeID map_Address_to_DirectoryNode(Address addr);
MachineID getL1MachineID(NodeID L1RubyNode);
NodeID getChipID(MachineID L2machID);
MachineID getCollectorDest(MachineID L1machID);
MachineID getCollectorL1Cache(MachineID colID);
NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers);
bool isL1OnChip(MachineID L1machID, NodeID L2NodeID);
bool isL2OnChip(MachineID L2machID, NodeID L2NodeID);
int getNumBanksInBankSet();
NodeID machineIDToNodeID(MachineID machID);
NodeID machineIDToVersion(MachineID machID);
MachineType machineIDToMachineType(MachineID machID);
NodeID L1CacheMachIDToProcessorNum(MachineID machID);
NodeID L2CacheMachIDToChipID(MachineID machID);
Set getOtherLocalL1IDs(MachineID L1);
Set getLocalL1IDs(MachineID L1);
Set getExternalL1IDs(MachineID L1);
NetDest getAllPertinentL2Banks(Address addr);
bool isLocalProcessor(MachineID thisId, MachineID tarId);
GenericMachineType ConvertMachToGenericMach(MachineType machType);

2
src/mem/protocol/RubySlicc_Types.sm
View file

@ -48,7 +48,7 @@ structure(InPort, external = "yes", primitive="yes") {
bool isEmpty();
}
external_type(NodeID, default="0");
external_type(NodeID, default="0", primitive="yes");
external_type(MachineID);
MessageBuffer getMandatoryQueue(int core_id);

40
src/mem/protocol/standard_1level_CMP-protocol.sm
View file

@ -1,40 +0,0 @@
/*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* $Id$
*/
// global protocol features
global(Protocol, desc="Global properties of this protocol",
interface = "AbstractProtocol") {
bool TwoLevelCache := false;
bool CMP := true;
}

36
src/mem/protocol/standard_CMP-protocol.sm
View file

@ -1,36 +0,0 @@
/*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// global protocol features
global(Protocol, desc="Global properties of this protocol",
interface = "AbstractProtocol") {
bool TwoLevelCache := true;
bool CMP := true;
}

1
src/mem/ruby/SConscript
View file

@ -109,7 +109,6 @@ MakeInclude('system/DirectoryMemory.hh')
MakeInclude('system/MachineID.hh')
MakeInclude('system/MemoryControl.hh')
MakeInclude('system/WireBuffer.hh')
MakeInclude('system/NodeID.hh')
MakeInclude('system/PerfectCacheMemory.hh')
MakeInclude('system/PersistentTable.hh')
MakeInclude('system/Sequencer.hh')

3
src/mem/ruby/common/Address.hh
View file

@ -33,8 +33,7 @@
#include <iomanip>
#include "base/hashmap.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/common/TypeDefines.hh"
const int ADDRESS_WIDTH = 64; // address width in bytes

2
src/mem/ruby/common/DataBlock.hh
View file

@ -32,7 +32,7 @@
#include <iomanip>
#include <iostream>
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/TypeDefines.hh"
class DataBlock
{

1
src/mem/ruby/common/Driver.hh
View file

@ -34,7 +34,6 @@
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
class Driver
{

11
src/mem/ruby/common/Global.hh
View file

@ -29,16 +29,7 @@
#ifndef __MEM_RUBY_COMMON_GLOBAL_HH__
#define __MEM_RUBY_COMMON_GLOBAL_HH__
// external includes for all classes
#include "mem/ruby/common/TypeDefines.hh"
// simple type declarations
typedef Time LogicalTime;
typedef int64 Index; // what the address bit ripper returns
typedef int word; // one word of a cache line
typedef unsigned int uint;
typedef int SwitchID;
typedef int LinkID;
#include "base/str.hh"
class RubyEventQueue;
extern RubyEventQueue* g_eventQueue_ptr;

2
src/mem/ruby/common/Histogram.hh
View file

@ -32,7 +32,7 @@
#include <iostream>
#include <vector>
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/TypeDefines.hh"
class Histogram
{

1
src/mem/ruby/common/NetDest.hh
View file

@ -42,7 +42,6 @@
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/Set.hh"
#include "mem/ruby/system/MachineID.hh"
#include "mem/ruby/system/NodeID.hh"
class NetDest
{

1
src/mem/ruby/common/Set.hh
View file

@ -36,7 +36,6 @@
#include <limits>
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/system/System.hh"
class Set

5
src/mem/ruby/common/TypeDefines.hh
View file

@ -44,4 +44,9 @@ typedef long long integer_t;
typedef int64 Time;
typedef uint64 physical_address_t;
typedef int64 Index; // what the address bit ripper returns
typedef int LinkID;
typedef int NodeID;
typedef int SwitchID;
#endif

2
src/mem/ruby/eventqueue/RubyEventQueue.hh
View file

@ -59,7 +59,7 @@
#include <iostream>
#include "config/no_vector_bounds_checks.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "sim/eventq.hh"
class Consumer;

1
src/mem/ruby/network/Network.hh
View file

@ -47,7 +47,6 @@
#include "mem/protocol/LinkDirection.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/system/System.hh"
#include "params/RubyNetwork.hh"
#include "sim/sim_object.hh"

3
src/mem/ruby/network/Topology.hh
View file

@ -45,8 +45,7 @@
#include <vector>
#include "mem/protocol/LinkDirection.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "params/Topology.hh"
#include "sim/sim_object.hh"

278
src/mem/ruby/network/fault_model/FaultModel.cc Normal file
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@ -0,0 +1,278 @@
/*
* Copyright (c) 2011 Massachusetts Institute of Technology
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Konstantinos Aisopos
*/
/*
* Official Tool Website: www.mit.edu/~kaisopos/FaultModel
*
* If you use our tool for academic research, we request that you cite:
* Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling
* System-Level Modeling of Variation-Induced Faults in Networks-on-Chip.
* Proceedings of the 48th Design Automation Conference (DAC'11)
*/
// C includes
#include <assert.h>
#include <stdio.h>
// C++ includes
#include <fstream>
#include <iostream>
#include <vector>
// GEM5 includes
#include "FaultModel.hh"
#include "base/misc.hh"
#define MAX(a,b) ((a > b) ? (a) : (b))
FaultModel::FaultModel(const Params *p) : SimObject(p)
{
// read configurations into "configurations" vector
// format: <buff/vc> <vcs> <10 fault types>
bool more_records = true;
for (int i = 0; more_records; i += (fields_per_conf_record)){
system_conf configuration;
configuration.buff_per_vc =
p->baseline_fault_vector_database[i + conf_record_buff_per_vc];
configuration.vcs =
p->baseline_fault_vector_database[i + conf_record_vcs];
for (int fault_index = 0; fault_index < number_of_fault_types;
fault_index++){
configuration.fault_type[fault_index] =
p->baseline_fault_vector_database[i +
conf_record_first_fault_type + fault_index] / 100;
}
configurations.push_back(configuration);
if (p->baseline_fault_vector_database[i+fields_per_conf_record] < 0){
more_records = false;
}
}
// read temperature weights into "temperature_weights" vector
// format: <temperature> <weight>
more_records = true;
for (int i = 0; more_records; i += (fields_per_temperature_record)){
int record_temperature =
p->temperature_weights_database[i + temperature_record_temp];
int record_weight =
p->temperature_weights_database[i + temperature_record_weight];
static int first_record = true;
if (first_record){
for (int temperature = 0; temperature < record_temperature;
temperature++){
temperature_weights.push_back(0);
}
first_record = false;
}
assert(record_temperature == temperature_weights.size());
temperature_weights.push_back(record_weight);
if (p->temperature_weights_database[i +
fields_per_temperature_record] < 0){
more_records = false;
}
}
}
string
FaultModel::fault_type_to_string(int ft)
{
if (ft == data_corruption__few_bits){
return "data_corruption__few_bits";
} else if (ft == data_corruption__all_bits){
return "data_corruption__all_bits";
} else if (ft == flit_conservation__flit_duplication){
return "flit_conservation__flit_duplication";
} else if (ft == flit_conservation__flit_loss_or_split){
return "flit_conservation__flit_loss_or_split";
} else if (ft == misrouting){
return "misrouting";
} else if (ft == credit_conservation__credit_generation){
return "credit_conservation__credit_generation";
} else if (ft == credit_conservation__credit_loss){
return "credit_conservation__credit_loss";
} else if (ft == erroneous_allocation__VC){
return "erroneous_allocation__VC";
} else if (ft == erroneous_allocation__switch){
return "erroneous_allocation__switch";
} else if (ft == unfair_arbitration){
return "unfair_arbitration";
} else if (ft == number_of_fault_types){
return "none";
} else {
return "none";
}
}
int
FaultModel::declare_router(int number_of_inputs,
int number_of_outputs,
int number_of_vcs_per_input,
int number_of_buff_per_data_vc,
int number_of_buff_per_ctrl_vc)
{
// check inputs (are they legal?)
if (number_of_inputs <= 0 || number_of_outputs <= 0 ||
number_of_vcs_per_input <= 0 || number_of_buff_per_data_vc <= 0 ||
number_of_buff_per_ctrl_vc <= 0){
fatal("Fault Model: ERROR in argument of FaultModel_declare_router!");
}
int number_of_buffers_per_vc = MAX(number_of_buff_per_data_vc,
number_of_buff_per_ctrl_vc);
int total_vcs = number_of_inputs * number_of_vcs_per_input;
if (total_vcs > MAX_VCs){
fatal("Fault Model: ERROR! Number inputs*VCs (MAX_VCs) unsupported");
}
if (number_of_buffers_per_vc > MAX_BUFFERS_per_VC){
fatal("Fault Model: ERROR! buffers/VC (MAX_BUFFERS_per_VC) too high");
}
// link the router to a DB record
int record_hit = -1;
for (int record = 0; record < configurations.size(); record++){
if ((configurations[record].buff_per_vc == number_of_buffers_per_vc)&&
(configurations[record].vcs == total_vcs)){
record_hit = record;
}
}
if (record_hit == -1){
panic("Fault Model: ERROR! configuration not found in DB. BUG?");
}
// remember the router and return its ID
routers.push_back(configurations[record_hit]);
static int router_index = 0;
return router_index++;
}
bool
FaultModel::fault_vector(int routerID,
int temperature_input,
float fault_vector[])
{
bool ok = true;
// is the routerID recorded?
if (routerID < 0 || routerID >= ((int) routers.size())){
warn("Fault Model: ERROR! unknown router ID argument.");
fatal("Fault Model: Did you enable the fault model flag)?");
}
// is the temperature too high/too low?
int temperature = temperature_input;
if (temperature_input >= ((int) temperature_weights.size())){
ok = false;
warn_once("Fault Model: Temperature exceeded simulated upper bound.");
warn_once("Fault Model: The fault model is not accurate any more.");
temperature = (temperature_weights.size() - 1);
} else if (temperature_input < 0){
ok = false;
warn_once("Fault Model: Temperature exceeded simulated lower bound.");
warn_once("Fault Model: The fault model is not accurate any more.");
temperature = 0;
}
// recover the router record and return its fault vector
for (int i = 0; i < number_of_fault_types; i++){
fault_vector[i] = routers[routerID].fault_type[i] *
((float)temperature_weights[temperature]);
}
return ok;
}
bool
FaultModel::fault_prob(int routerID,
int temperature_input,
float *aggregate_fault_prob)
{
*aggregate_fault_prob = 1.0;
bool ok = true;
// is the routerID recorded?
if (routerID < 0 || routerID >= ((int) routers.size())){
warn("Fault Model: ERROR! unknown router ID argument.");
fatal("Fault Model: Did you enable the fault model flag)?");
}
// is the temperature too high/too low?
int temperature = temperature_input;
if (temperature_input >= ((int) temperature_weights.size()) ){
ok = false;
warn_once("Fault Model: Temperature exceeded simulated upper bound.");
warn_once("Fault Model: The fault model is not accurate any more.");
temperature = (temperature_weights.size()-1);
} else if (temperature_input < 0){
ok = false;
warn_once("Fault Model: Temperature exceeded simulated lower bound.");
warn_once("Fault Model: The fault model is not accurate any more.");
temperature = 0;
}
// recover the router record and return its aggregate fault probability
for (int i = 0; i < number_of_fault_types; i++){
*aggregate_fault_prob= *aggregate_fault_prob *
( 1.0 - (routers[routerID].fault_type[i] *
((float)temperature_weights[temperature])) );
}
*aggregate_fault_prob = 1.0 - *aggregate_fault_prob;
return ok;
}
// this function is used only for debugging purposes
void
FaultModel::print(void)
{
cout << "--- PRINTING configurations ---\n";
for (int record = 0; record < configurations.size(); record++){
cout << "(" << record << ") ";
cout << "VCs=" << configurations[record].vcs << " ";
cout << "Buff/VC=" << configurations[record].buff_per_vc << " [";
for (int fault_type_num = 0;
fault_type_num < number_of_fault_types;
fault_type_num++){
cout << (100 * configurations[record].fault_type[fault_type_num]);
cout << "% ";
}
cout << "]\n";
}
cout << "--- PRINTING temperature weights ---\n";
for (int record = 0; record < temperature_weights.size(); record++){
cout << "temperature=" << record << " => ";
cout << "weight=" << temperature_weights[record];
cout << "\n";
}
}
FaultModel *
FaultModelParams::create()
{
return new FaultModel(this);
}

142
src/mem/ruby/network/fault_model/FaultModel.hh Normal file
View file

@ -0,0 +1,142 @@
/*
* Copyright (c) 2011 Massachusetts Institute of Technology
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Konstantinos Aisopos
*/
/*
* Official Tool Website: www.mit.edu/~kaisopos/FaultModel
*
* If you use our tool for academic research, we request that you cite:
* Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling
* System-Level Modeling of Variation-Induced Faults in Networks-on-Chip.
* Proceedings of the 48th Design Automation Conference (DAC'11)
*/
#ifndef __MEM_RUBY_NETWORK_FAULT_MODEL_HH__
#define __MEM_RUBY_NETWORK_FAULT_MODEL_HH__
// tool limitations and fixed inputs
#define MAX_VCs 40
#define MAX_BUFFERS_per_VC 5
#define BASELINE_TEMPERATURE_CELCIUS 71
// C++ includes
#include <string>
using namespace std;
// GEM5 includes
#include "params/FaultModel.hh"
#include "sim/sim_object.hh"
class FaultModel : public SimObject
{
public:
typedef FaultModelParams Params;
FaultModel(const Params *p);
const Params *params() const { return (const Params *)_params; }
/************************************************************************/
/********** THE FAULT TYPES SUPPORTED BY THE FAULT MODEL ***************/
/************************************************************************/
enum fault_type
{
data_corruption__few_bits,
data_corruption__all_bits,
flit_conservation__flit_duplication,
flit_conservation__flit_loss_or_split,
misrouting,
credit_conservation__credit_generation,
credit_conservation__credit_loss,
erroneous_allocation__VC,
erroneous_allocation__switch,
unfair_arbitration,
number_of_fault_types
};
/************************************************************************/
/******************** INTERFACE OF THE FAULT MODEL *********************/
/************************************************************************/
enum conf_record_format
{
conf_record_buff_per_vc,
conf_record_vcs,
conf_record_first_fault_type,
conf_record_last_fault_type = conf_record_first_fault_type + number_of_fault_types - 1,
fields_per_conf_record
};
enum temperature_record_format
{
temperature_record_temp,
temperature_record_weight,
fields_per_temperature_record
};
struct system_conf
{
int vcs;
int buff_per_vc;
float fault_type[number_of_fault_types];
};
int declare_router(int number_of_inputs,
int number_of_outputs,
int number_of_vcs_per_vnet,
int number_of_buff_per_data_vc,
int number_of_buff_per_ctrl_vc);
string fault_type_to_string(int fault_type_index);
// the following 2 functions are called at runtime, to get the probability
// of each fault type (fault_vector) or the aggregate fault probability
// (fault_prob). Note: the probability values are provided by reference
// (in the variables fault_vector[] & aggregate_fault_prob respectively).
// Both functions also return a success flag (which is always true if
// temperature ranges from 0C to 125C)
bool fault_vector(int routerID,
int temperature,
float fault_vector[]);
bool fault_prob(int routerID,
int temperature,
float *aggregate_fault_prob);
// for debugging purposes
void print(void);
private:
vector <system_conf> configurations;
vector <system_conf> routers;
vector <int> temperature_weights;
};
#endif // __MEM_RUBY_NETWORK_FAULT_MODEL_HH__

302
src/mem/ruby/network/fault_model/FaultModel.py Normal file
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@ -0,0 +1,302 @@
# Copyright (c) 2011 Massachusetts Institute of Technology
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Konstantinos Aisopos
# Official Tool Website: www.mit.edu/~kaisopos/FaultModel
#
# If you use our tool for academic research, we request that you cite:
# Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling
# System-Level Modeling of Variation-Induced Faults in Networks-on-Chip.
# Proceedings of the 48th Design Automation Conference (DAC'11)
from m5.params import *
from m5.SimObject import SimObject
class FaultModel(SimObject):
type = 'FaultModel'
cxx_class = 'FaultModel'
baseline_fault_vector_database = VectorParam.Float([
5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500,
5, 39, 0.062640, 0.089100, 0.016821, 0.109620, 0.051462, 0.060210, 0.029700, 0.076140, 0.062100, 0.116100,
5, 38, 0.050490, 0.076950, 0.015782, 0.091530, 0.044550, 0.046170, 0.025920, 0.070200, 0.057294, 0.110700,
5, 37, 0.042120, 0.067770, 0.014191, 0.082890, 0.040986, 0.037800, 0.023760, 0.065880, 0.053568, 0.104490,
5, 36, 0.035910, 0.061020, 0.013211, 0.075600, 0.035100, 0.030240, 0.021060, 0.061560, 0.049815, 0.100710,
5, 35, 0.032130, 0.054810, 0.011964, 0.071550, 0.031860, 0.026730, 0.019710, 0.057510, 0.047169, 0.094230,
5, 34, 0.028890, 0.051030, 0.011054, 0.067500, 0.030510, 0.023450, 0.018630, 0.054000, 0.045900, 0.088290,
5, 33, 0.026460, 0.047250, 0.010160, 0.062640, 0.028971, 0.021600, 0.017280, 0.049410, 0.042903, 0.082080,
5, 32, 0.024300, 0.042930, 0.009312, 0.057780, 0.027000, 0.019710, 0.016470, 0.045360, 0.041310, 0.075600,
5, 31, 0.022410, 0.037260, 0.008910, 0.054540, 0.024732, 0.018171, 0.015660, 0.043470, 0.039447, 0.070740,
5, 30, 0.021870, 0.032130, 0.008162, 0.050220, 0.023625, 0.016762, 0.013770, 0.039150, 0.037557, 0.065880,
5, 29, 0.020790, 0.028080, 0.007657, 0.042660, 0.020061, 0.016043, 0.012690, 0.036720, 0.035451, 0.062370,
5, 28, 0.019440, 0.025650, 0.007123, 0.037800, 0.018900, 0.015363, 0.011880, 0.033480, 0.032400, 0.057780,
5, 27, 0.018473, 0.023760, 0.006737, 0.034830, 0.018036, 0.014153, 0.011232, 0.030240, 0.030645, 0.055890,
5, 26, 0.017550, 0.021330, 0.006440, 0.032130, 0.016497, 0.013511, 0.010031, 0.027621, 0.028242, 0.051030,
5, 25, 0.016462, 0.020520, 0.006210, 0.028890, 0.015822, 0.013095, 0.009442, 0.021600, 0.026379, 0.046170,
5, 24, 0.015930, 0.018360, 0.005940, 0.026730, 0.015047, 0.012377, 0.008918, 0.018360, 0.023193, 0.037800,
5, 23, 0.015390, 0.017931, 0.005594, 0.025488, 0.013365, 0.012037, 0.008775, 0.015120, 0.018657, 0.031590,
5, 22, 0.014804, 0.017167, 0.005338, 0.023976, 0.012258, 0.011734, 0.008087, 0.013500, 0.015444, 0.026190,
5, 21, 0.014180, 0.016548, 0.004995, 0.022194, 0.011807, 0.011073, 0.007236, 0.011070, 0.013500, 0.021870,
5, 20, 0.013743, 0.016176, 0.004613, 0.020414, 0.011070, 0.010415, 0.006220, 0.010415, 0.010800, 0.019077,
5, 19, 0.011877, 0.015412, 0.003861, 0.016659, 0.008235, 0.008640, 0.005400, 0.009720, 0.008532, 0.013770,
5, 18, 0.011097, 0.014310, 0.003483, 0.014526, 0.006912, 0.007560, 0.003780, 0.008640, 0.006885, 0.010260,
5, 17, 0.010419, 0.011939, 0.002700, 0.011394, 0.005400, 0.006318, 0.003038, 0.008100, 0.005400, 0.009450,
5, 16, 0.009887, 0.009720, 0.002395, 0.010152, 0.004023, 0.005400, 0.002743, 0.007020, 0.004590, 0.008370,
5, 15, 0.009617, 0.007825, 0.002079, 0.008289, 0.003780, 0.004806, 0.002236, 0.006480, 0.003996, 0.008127,
5, 14, 0.008710, 0.006820, 0.001817, 0.007749, 0.003240, 0.004185, 0.001760, 0.005400, 0.002538, 0.006615,
5, 13, 0.008116, 0.006566, 0.001566, 0.006426, 0.002741, 0.003564, 0.001299, 0.004590, 0.001917, 0.005994,
5, 12, 0.007908, 0.006151, 0.001350, 0.005400, 0.002471, 0.003132, 0.000794, 0.004050, 0.001323, 0.005940,
5, 11, 0.007690, 0.005627, 0.001094, 0.005076, 0.002363, 0.002052, 0.000567, 0.003510, 0.001188, 0.004860,
5, 10, 0.007560, 0.005038, 0.000805, 0.004536, 0.001985, 0.000540, 0.000000, 0.002430, 0.000999, 0.003240,
5, 9, 0.007314, 0.004193, 0.000540, 0.003834, 0.001715, 0.000000, 0.000000, 0.002160, 0.000945, 0.002700,
5, 8, 0.006750, 0.003240, 0.000000, 0.003240, 0.001323, 0.000000, 0.000000, 0.001350, 0.000837, 0.002646,
5, 7, 0.006461, 0.002700, 0.000000, 0.002700, 0.001215, 0.000000, 0.000000, 0.000000, 0.000810, 0.001809,
5, 6, 0.006240, 0.001796, 0.000000, 0.002052, 0.001013, 0.000000, 0.000000, 0.000000, 0.000756, 0.001620,
5, 5, 0.005430, 0.000675, 0.000000, 0.000864, 0.000864, 0.000000, 0.000000, 0.000000, 0.000729, 0.001593,
5, 4, 0.003780, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.001080,
5, 3, 0.001350, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000540,
5, 2, 0.000540, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000270,
5, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
4, 40, 0.079484, 0.106785, 0.018198, 0.122699, 0.057538, 0.076974, 0.034813, 0.079276, 0.061426, 0.112509,
4, 39, 0.062146, 0.088671, 0.016205, 0.108082, 0.050454, 0.059905, 0.029600, 0.075465, 0.057362, 0.106596,
4, 38, 0.050047, 0.076478, 0.014924, 0.090994, 0.043475, 0.045808, 0.025794, 0.069220, 0.054351, 0.101993,
4, 37, 0.041712, 0.067272, 0.013551, 0.082516, 0.040026, 0.037390, 0.023580, 0.064897, 0.051395, 0.097511,
4, 36, 0.035384, 0.060487, 0.012434, 0.075287, 0.034229, 0.029784, 0.020859, 0.060167, 0.048222, 0.094055,
4, 35, 0.031455, 0.054259, 0.011290, 0.071141, 0.031259, 0.026055, 0.019560, 0.055478, 0.045887, 0.088965,
4, 34, 0.028307, 0.050427, 0.010342, 0.067048, 0.029835, 0.022525, 0.018495, 0.052523, 0.044253, 0.083727,
4, 33, 0.025847, 0.046687, 0.009384, 0.062196, 0.028000, 0.020646, 0.017102, 0.048735, 0.041837, 0.079286,
4, 32, 0.023688, 0.042449, 0.008645, 0.057303, 0.026070, 0.018765, 0.016315, 0.045001, 0.040163, 0.073143,
4, 31, 0.021905, 0.036781, 0.008235, 0.054011, 0.024200, 0.017496, 0.015528, 0.042795, 0.038273, 0.068675,
4, 30, 0.021195, 0.031563, 0.007456, 0.049545, 0.022757, 0.016081, 0.013646, 0.038817, 0.036410, 0.063086,
4, 29, 0.020115, 0.027494, 0.006992, 0.042302, 0.019517, 0.015096, 0.012562, 0.035562, 0.034223, 0.059954,
4, 28, 0.018889, 0.025040, 0.006472, 0.037295, 0.018383, 0.014540, 0.011760, 0.032949, 0.032022, 0.055782,
4, 27, 0.017630, 0.023150, 0.006055, 0.034262, 0.017183, 0.013759, 0.010949, 0.029876, 0.030294, 0.053339,
4, 26, 0.016875, 0.020762, 0.005743, 0.031664, 0.016002, 0.013123, 0.009740, 0.026487, 0.027824, 0.048681,
4, 25, 0.015930, 0.019660, 0.005516, 0.028215, 0.015147, 0.012420, 0.009311, 0.020643, 0.025988, 0.043443,
4, 24, 0.015425, 0.017790, 0.005211, 0.026190, 0.014530, 0.011838, 0.008783, 0.017314, 0.022518, 0.035681,
4, 23, 0.014947, 0.017314, 0.004878, 0.024813, 0.012897, 0.011507, 0.008451, 0.014445, 0.017982, 0.029673,
4, 22, 0.014430, 0.016278, 0.004610, 0.023077, 0.011945, 0.011148, 0.007918, 0.012825, 0.015107, 0.023814,
4, 21, 0.013643, 0.015699, 0.004320, 0.021686, 0.011598, 0.010383, 0.007113, 0.010395, 0.013176, 0.019197,
4, 20, 0.013023, 0.015244, 0.003995, 0.019155, 0.010935, 0.009227, 0.005914, 0.009227, 0.010665, 0.016234,
4, 19, 0.011185, 0.014467, 0.003186, 0.015718, 0.007822, 0.007965, 0.005273, 0.008374, 0.008262, 0.012623,
4, 18, 0.010399, 0.013419, 0.002808, 0.013696, 0.006681, 0.006885, 0.003579, 0.007579, 0.006197, 0.009315,
4, 17, 0.009773, 0.011089, 0.002025, 0.010882, 0.005054, 0.005881, 0.002928, 0.007101, 0.004914, 0.008100,
4, 16, 0.009054, 0.009054, 0.001743, 0.009477, 0.003799, 0.005081, 0.002365, 0.006345, 0.003942, 0.007061,
4, 15, 0.008575, 0.006882, 0.001404, 0.007792, 0.003449, 0.004131, 0.001793, 0.005327, 0.002903, 0.006264,
4, 14, 0.008069, 0.005655, 0.001169, 0.006920, 0.002808, 0.003510, 0.001277, 0.004307, 0.001782, 0.005184,
4, 13, 0.007668, 0.005173, 0.000986, 0.005751, 0.002336, 0.002889, 0.000919, 0.003609, 0.001283, 0.004631,
4, 12, 0.007403, 0.004563, 0.000675, 0.004852, 0.002066, 0.002457, 0.000532, 0.003083, 0.000662, 0.004374,
4, 11, 0.007152, 0.004127, 0.000547, 0.004401, 0.001937, 0.001377, 0.000284, 0.002473, 0.000594, 0.003456,
4, 10, 0.006885, 0.003530, 0.000402, 0.003920, 0.001613, 0.000405, 0.000000, 0.001755, 0.000500, 0.002565,
4, 9, 0.006746, 0.002920, 0.000270, 0.003159, 0.001404, 0.000000, 0.000000, 0.001485, 0.000473, 0.002025,
4, 8, 0.006257, 0.002290, 0.000000, 0.002565, 0.001107, 0.000000, 0.000000, 0.000675, 0.000419, 0.001971,
4, 7, 0.005931, 0.001825, 0.000000, 0.002025, 0.000999, 0.000000, 0.000000, 0.000000, 0.000405, 0.001134,
4, 6, 0.005585, 0.001199, 0.000000, 0.001463, 0.000844, 0.000000, 0.000000, 0.000000, 0.000378, 0.000945,
4, 5, 0.004967, 0.000545, 0.000000, 0.000637, 0.000695, 0.000000, 0.000000, 0.000000, 0.000405, 0.000864,
4, 4, 0.003105, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000540,
4, 3, 0.000888, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000270,
4, 2, 0.000270, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000135,
4, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
3, 40, 0.078075, 0.104396, 0.017531, 0.114991, 0.055352, 0.076378, 0.034795, 0.075122, 0.055352, 0.103518,
3, 39, 0.061652, 0.088241, 0.015590, 0.106545, 0.049445, 0.059600, 0.029500, 0.074790, 0.052623, 0.097092,
3, 38, 0.049604, 0.076005, 0.014067, 0.090458, 0.042401, 0.045446, 0.025669, 0.068240, 0.051408, 0.093285,
3, 37, 0.041305, 0.066774, 0.012911, 0.082142, 0.039066, 0.036979, 0.023401, 0.063914, 0.049221, 0.090531,
3, 36, 0.034857, 0.059954, 0.011656, 0.074974, 0.033359, 0.029327, 0.020658, 0.058774, 0.046629, 0.087399,
3, 35, 0.030780, 0.053708, 0.010616, 0.070732, 0.030659, 0.025380, 0.019410, 0.053447, 0.044604, 0.083700,
3, 34, 0.027724, 0.049823, 0.009631, 0.066596, 0.029160, 0.021600, 0.018360, 0.051046, 0.042606, 0.079164,
3, 33, 0.025234, 0.046124, 0.008608, 0.061752, 0.027030, 0.019691, 0.016924, 0.048060, 0.040770, 0.076491,
3, 32, 0.023077, 0.041969, 0.007979, 0.056827, 0.025140, 0.017820, 0.016160, 0.044642, 0.039015, 0.070686,
3, 31, 0.021400, 0.036302, 0.007560, 0.053482, 0.023668, 0.016821, 0.015395, 0.042120, 0.037098, 0.066609,
3, 30, 0.020520, 0.030996, 0.006750, 0.048870, 0.021889, 0.015401, 0.013522, 0.038483, 0.035262, 0.060291,
3, 29, 0.019440, 0.026908, 0.006326, 0.041945, 0.018973, 0.014148, 0.012434, 0.034403, 0.032994, 0.057537,
3, 28, 0.018338, 0.024430, 0.005821, 0.036790, 0.017866, 0.013716, 0.011640, 0.032419, 0.031644, 0.053784,
3, 27, 0.016786, 0.022540, 0.005373, 0.033693, 0.016330, 0.013365, 0.010665, 0.029511, 0.029943, 0.050787,
3, 26, 0.016200, 0.020193, 0.005046, 0.031199, 0.015506, 0.012736, 0.009450, 0.025353, 0.027405, 0.046332,
3, 25, 0.015398, 0.018800, 0.004822, 0.027540, 0.014472, 0.011745, 0.009180, 0.019686, 0.025596, 0.040716,
3, 24, 0.014920, 0.017221, 0.004482, 0.025650, 0.014013, 0.011300, 0.008648, 0.016268, 0.021843, 0.033561,
3, 23, 0.014504, 0.016697, 0.004161, 0.024138, 0.012428, 0.010978, 0.008127, 0.013770, 0.017307, 0.027756,
3, 22, 0.014056, 0.015390, 0.003883, 0.022178, 0.011632, 0.010562, 0.007749, 0.012150, 0.014769, 0.021438,
3, 21, 0.013106, 0.014850, 0.003645, 0.021179, 0.011389, 0.009693, 0.006990, 0.009720, 0.012852, 0.016524,
3, 20, 0.012304, 0.014313, 0.003378, 0.017896, 0.010800, 0.008039, 0.005608, 0.008039, 0.010530, 0.013392,
3, 19, 0.010492, 0.013522, 0.002511, 0.014777, 0.007409, 0.007290, 0.005146, 0.007028, 0.007992, 0.011475,
3, 18, 0.009701, 0.012528, 0.002133, 0.012866, 0.006450, 0.006210, 0.003378, 0.006518, 0.005508, 0.008370,
3, 17, 0.009126, 0.010238, 0.001350, 0.010371, 0.004709, 0.005443, 0.002819, 0.006102, 0.004428, 0.006750,
3, 16, 0.008222, 0.008389, 0.001091, 0.008802, 0.003575, 0.004763, 0.001987, 0.005670, 0.003294, 0.005751,
3, 15, 0.007533, 0.005940, 0.000729, 0.007295, 0.003119, 0.003456, 0.001350, 0.004174, 0.001809, 0.004401,
3, 14, 0.007428, 0.004490, 0.000521, 0.006091, 0.002376, 0.002835, 0.000794, 0.003213, 0.001026, 0.003753,
3, 13, 0.007220, 0.003780, 0.000405, 0.005076, 0.001931, 0.002214, 0.000540, 0.002627, 0.000648, 0.003267,
3, 12, 0.006899, 0.002975, 0.000000, 0.004304, 0.001661, 0.001782, 0.000270, 0.002117, 0.000000, 0.002808,
3, 11, 0.006615, 0.002627, 0.000000, 0.003726, 0.001512, 0.000702, 0.000000, 0.001436, 0.000000, 0.002052,
3, 10, 0.006210, 0.002022, 0.000000, 0.003305, 0.001242, 0.000270, 0.000000, 0.001080, 0.000000, 0.001890,
3, 9, 0.006178, 0.001647, 0.000000, 0.002484, 0.001094, 0.000000, 0.000000, 0.000810, 0.000000, 0.001350,
3, 8, 0.005765, 0.001339, 0.000000, 0.001890, 0.000891, 0.000000, 0.000000, 0.000000, 0.000000, 0.001296,
3, 7, 0.005400, 0.000950, 0.000000, 0.001350, 0.000783, 0.000000, 0.000000, 0.000000, 0.000000, 0.000459,
3, 6, 0.004930, 0.000602, 0.000000, 0.000875, 0.000675, 0.000000, 0.000000, 0.000000, 0.000000, 0.000270,
3, 5, 0.004504, 0.000416, 0.000000, 0.000410, 0.000527, 0.000000, 0.000000, 0.000000, 0.000081, 0.000135,
3, 4, 0.002430, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
3, 3, 0.000427, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
3, 2, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
3, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
2, 40, 0.077418, 0.103451, 0.016828, 0.109064, 0.054341, 0.075962, 0.034795, 0.075122, 0.051976, 0.081459,
2, 39, 0.060720, 0.087215, 0.014756, 0.103532, 0.048041, 0.059297, 0.029376, 0.074115, 0.050193, 0.077382,
2, 38, 0.048859, 0.074947, 0.013362, 0.089180, 0.041598, 0.045021, 0.025537, 0.066803, 0.048722, 0.074655,
2, 37, 0.040158, 0.065781, 0.012126, 0.080282, 0.038175, 0.036686, 0.023178, 0.062884, 0.047088, 0.072630,
2, 36, 0.033881, 0.058774, 0.011001, 0.072895, 0.032542, 0.028434, 0.020461, 0.057424, 0.045225, 0.069728,
2, 35, 0.030294, 0.052831, 0.009800, 0.069422, 0.029587, 0.024311, 0.019232, 0.052294, 0.043254, 0.067311,
2, 34, 0.026957, 0.048824, 0.008847, 0.065224, 0.028054, 0.020655, 0.018095, 0.049876, 0.041553, 0.064112,
2, 33, 0.024349, 0.045159, 0.007976, 0.060371, 0.026226, 0.018652, 0.016776, 0.047385, 0.039704, 0.061695,
2, 32, 0.022078, 0.040951, 0.007202, 0.055330, 0.024365, 0.017145, 0.016065, 0.043944, 0.037719, 0.057699,
2, 31, 0.020733, 0.035223, 0.006791, 0.052327, 0.022850, 0.015790, 0.015233, 0.041124, 0.035964, 0.054810,
2, 30, 0.019626, 0.029984, 0.006021, 0.046551, 0.021086, 0.014673, 0.013133, 0.037757, 0.034007, 0.049923,
2, 29, 0.018765, 0.025923, 0.005677, 0.039731, 0.018291, 0.013707, 0.011973, 0.033543, 0.031847, 0.047048,
2, 28, 0.017539, 0.023491, 0.005192, 0.035180, 0.017033, 0.013349, 0.011092, 0.031296, 0.029970, 0.044240,
2, 27, 0.016270, 0.021488, 0.004753, 0.032258, 0.015628, 0.012909, 0.010419, 0.028179, 0.028202, 0.041756,
2, 26, 0.015525, 0.019557, 0.004390, 0.029942, 0.014652, 0.012207, 0.009339, 0.024975, 0.025745, 0.037679,
2, 25, 0.014638, 0.018036, 0.004146, 0.026314, 0.013797, 0.011314, 0.009099, 0.018864, 0.023517, 0.032832,
2, 24, 0.014075, 0.016575, 0.003788, 0.024444, 0.013045, 0.010780, 0.008541, 0.015587, 0.019710, 0.028013,
2, 23, 0.013597, 0.015638, 0.003430, 0.022970, 0.011632, 0.010471, 0.008031, 0.012675, 0.015296, 0.023004,
2, 22, 0.012968, 0.014715, 0.003089, 0.021096, 0.010990, 0.009929, 0.007642, 0.010846, 0.012825, 0.017253,
2, 21, 0.012088, 0.014175, 0.002884, 0.020046, 0.010148, 0.009032, 0.006813, 0.008261, 0.010449, 0.013500,
2, 20, 0.010976, 0.013381, 0.002693, 0.016732, 0.009381, 0.007742, 0.005400, 0.006437, 0.008100, 0.010841,
2, 19, 0.009566, 0.012631, 0.001836, 0.013686, 0.007125, 0.006782, 0.003923, 0.005431, 0.005589, 0.008613,
2, 18, 0.008982, 0.011349, 0.001458, 0.011744, 0.005708, 0.005742, 0.002724, 0.004884, 0.003618, 0.006764,
2, 17, 0.008273, 0.009439, 0.000845, 0.009291, 0.004250, 0.004857, 0.002327, 0.004469, 0.002673, 0.004847,
2, 16, 0.007679, 0.007704, 0.000545, 0.007737, 0.003394, 0.003988, 0.001534, 0.004045, 0.001742, 0.003834,
2, 15, 0.007236, 0.005265, 0.000365, 0.006442, 0.002565, 0.003089, 0.000675, 0.003023, 0.000959, 0.002808,
2, 14, 0.007090, 0.003787, 0.000261, 0.004990, 0.001802, 0.002400, 0.000397, 0.002249, 0.000608, 0.002457,
2, 13, 0.006877, 0.003029, 0.000203, 0.004076, 0.001404, 0.001835, 0.000270, 0.001814, 0.000324, 0.002012,
2, 12, 0.006575, 0.002311, 0.000000, 0.003502, 0.001249, 0.001458, 0.000135, 0.001436, 0.000000, 0.001850,
2, 11, 0.006314, 0.001836, 0.000000, 0.003051, 0.001114, 0.000597, 0.000000, 0.000841, 0.000000, 0.001350,
2, 10, 0.005971, 0.001434, 0.000000, 0.002570, 0.000945, 0.000230, 0.000000, 0.000540, 0.000000, 0.001215,
2, 9, 0.005627, 0.001172, 0.000000, 0.001809, 0.000783, 0.000019, 0.000000, 0.000405, 0.000000, 0.000675,
2, 8, 0.005144, 0.000940, 0.000000, 0.001276, 0.000668, 0.000038, 0.000000, 0.000000, 0.000000, 0.000648,
2, 7, 0.004686, 0.000622, 0.000000, 0.000890, 0.000581, 0.000009, 0.000000, 0.000000, 0.000000, 0.000230,
2, 6, 0.004247, 0.000428, 0.000000, 0.000541, 0.000473, 0.000019, 0.000000, 0.000000, 0.000000, 0.000135,
2, 5, 0.003857, 0.000269, 0.000000, 0.000320, 0.000419, 0.000000, 0.000000, 0.000000, 0.000041, 0.000068,
2, 4, 0.001459, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
2, 3, 0.000213, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
2, 2, 0.000011, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
2, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
1, 40, 0.076761, 0.102506, 0.016124, 0.103138, 0.053330, 0.075546, 0.034795, 0.075122, 0.048600, 0.059400,
1, 39, 0.059789, 0.086189, 0.013921, 0.100518, 0.046637, 0.058995, 0.029252, 0.073440, 0.047763, 0.057672,
1, 38, 0.048114, 0.073888, 0.012658, 0.087901, 0.040794, 0.044596, 0.025404, 0.065367, 0.046035, 0.056025,
1, 37, 0.039012, 0.064789, 0.011340, 0.078422, 0.037284, 0.036393, 0.022955, 0.061854, 0.044955, 0.054729,
1, 36, 0.032905, 0.057594, 0.010346, 0.070816, 0.031725, 0.027540, 0.020264, 0.056074, 0.043821, 0.052056,
1, 35, 0.029808, 0.051953, 0.008983, 0.068113, 0.028515, 0.023242, 0.019054, 0.051141, 0.041904, 0.050922,
1, 34, 0.026190, 0.047825, 0.008062, 0.063852, 0.026949, 0.019710, 0.017831, 0.048705, 0.040500, 0.049059,
1, 33, 0.023463, 0.044194, 0.007344, 0.058990, 0.025423, 0.017612, 0.016629, 0.046710, 0.038637, 0.046899,
1, 32, 0.021079, 0.039933, 0.006426, 0.053833, 0.023590, 0.016470, 0.015971, 0.043246, 0.036423, 0.044712,
1, 31, 0.020066, 0.034144, 0.006021, 0.051173, 0.022032, 0.014758, 0.015071, 0.040127, 0.034830, 0.043011,
1, 30, 0.018733, 0.028971, 0.005292, 0.044231, 0.020282, 0.013946, 0.012744, 0.037031, 0.032751, 0.039555,
1, 29, 0.018090, 0.024937, 0.005027, 0.037517, 0.017609, 0.013265, 0.011513, 0.032684, 0.030699, 0.036558,
1, 28, 0.016740, 0.022553, 0.004563, 0.033569, 0.016200, 0.012982, 0.010544, 0.030173, 0.028296, 0.034695,
1, 27, 0.015755, 0.020436, 0.004134, 0.030823, 0.014926, 0.012452, 0.010174, 0.026846, 0.026460, 0.032724,
1, 26, 0.014850, 0.018922, 0.003734, 0.028685, 0.013797, 0.011678, 0.009229, 0.024597, 0.024084, 0.029025,
1, 25, 0.013878, 0.017272, 0.003470, 0.025088, 0.013122, 0.010884, 0.009018, 0.018041, 0.021438, 0.024948,
1, 24, 0.013230, 0.015930, 0.003094, 0.023239, 0.012077, 0.010260, 0.008435, 0.014907, 0.017577, 0.022464,
1, 23, 0.012690, 0.014580, 0.002700, 0.021803, 0.010835, 0.009963, 0.007935, 0.011580, 0.013284, 0.018252,
1, 22, 0.011880, 0.014040, 0.002295, 0.020015, 0.010349, 0.009296, 0.007536, 0.009542, 0.010881, 0.013068,
1, 21, 0.011070, 0.013500, 0.002122, 0.018914, 0.008907, 0.008370, 0.006637, 0.006801, 0.008046, 0.010476,
1, 20, 0.009647, 0.012450, 0.002009, 0.015568, 0.007962, 0.007444, 0.005192, 0.004836, 0.005670, 0.008289,
1, 19, 0.008640, 0.011740, 0.001161, 0.012596, 0.006842, 0.006275, 0.002700, 0.003834, 0.003186, 0.005751,
1, 18, 0.008262, 0.010171, 0.000783, 0.010622, 0.004965, 0.005273, 0.002071, 0.003251, 0.001728, 0.005157,
1, 17, 0.007420, 0.008640, 0.000340, 0.008211, 0.003791, 0.004271, 0.001836, 0.002835, 0.000918, 0.002943,
1, 16, 0.007136, 0.007020, 0.000000, 0.006672, 0.003213, 0.003213, 0.001080, 0.002419, 0.000189, 0.001917,
1, 15, 0.006939, 0.004590, 0.000000, 0.005589, 0.002012, 0.002722, 0.000000, 0.001871, 0.000108, 0.001215,
1, 14, 0.006753, 0.003083, 0.000000, 0.003888, 0.001229, 0.001966, 0.000000, 0.001285, 0.000189, 0.001161,
1, 13, 0.006534, 0.002279, 0.000000, 0.003075, 0.000878, 0.001455, 0.000000, 0.001002, 0.000000, 0.000756,
1, 12, 0.006251, 0.001647, 0.000000, 0.002700, 0.000837, 0.001134, 0.000000, 0.000756, 0.000000, 0.000891,
1, 11, 0.006013, 0.001045, 0.000000, 0.002376, 0.000716, 0.000491, 0.000000, 0.000246, 0.000000, 0.000648,
1, 10, 0.005732, 0.000845, 0.000000, 0.001836, 0.000648, 0.000189, 0.000000, 0.000000, 0.000000, 0.000540,
1, 9, 0.005076, 0.000697, 0.000000, 0.001134, 0.000473, 0.000038, 0.000000, 0.000000, 0.000000, 0.000000,
1, 8, 0.004523, 0.000540, 0.000000, 0.000662, 0.000446, 0.000076, 0.000000, 0.000000, 0.000000, 0.000000,
1, 7, 0.003972, 0.000294, 0.000000, 0.000429, 0.000378, 0.000019, 0.000000, 0.000000, 0.000000, 0.000000,
1, 6, 0.003564, 0.000254, 0.000000, 0.000208, 0.000270, 0.000038, 0.000000, 0.000000, 0.000000, 0.000000,
1, 5, 0.003210, 0.000122, 0.000000, 0.000230, 0.000311, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
1, 4, 0.000489, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
1, 3, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
1, 2, 0.000022, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
1, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000,
-1], "");
temperature_weights_database = VectorParam.Int([
71, 1,
72, 2,
73, 3,
74, 4,
75, 5,
76, 5,
77, 6,
78, 7,
79, 8,
80, 10,
81, 11,
82, 12,
83, 12,
84, 13,
85, 14,
86, 16,
87, 17,
88, 18,
89, 19,
90, 20,
91, 22,
92, 24,
93, 26,
94, 27,
95, 29,
96, 30,
97, 32,
98, 35,
99, 37,
100, 39,
101, 42,
102, 45,
103, 47,
104, 50,
105, 53,
106, 56,
107, 61,
108, 65,
109, 70,
110, 74,
111, 78,
112, 82,
113, 89,
114, 95,
115, 100,
116, 106,
117, 115,
118, 122,
119, 130,
120, 139,
121, 147,
122, 156,
123, 169,
124, 178,
125, 190,
-1], "");

43
src/mem/ruby/network/fault_model/SConscript Normal file
View file

@ -0,0 +1,43 @@
# Copyright (c) 2011 Massachusetts Institute of Technology
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Konstantinos Aisopos
# Official Tool Website: www.mit.edu/~kaisopos/FaultModel
#
# If you use our tool for academic research, we request that you cite:
# Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling
# System-Level Modeling of Variation-Induced Faults in Networks-on-Chip.
# Proceedings of the 48th Design Automation Conference (DAC'11)
Import('*')
if env['PROTOCOL'] == 'None':
Return()
SimObject('FaultModel.py')
Source('FaultModel.cc')

3
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
View file

@ -38,6 +38,9 @@ BaseGarnetNetwork::BaseGarnetNetwork(const Params *p)
{
m_ni_flit_size = p->ni_flit_size;
m_vcs_per_vnet = p->vcs_per_vnet;
m_enable_fault_model = p->enable_fault_model;
if (m_enable_fault_model)
fault_model = p->fault_model;
m_ruby_start = 0;
m_flits_received = 0;

4
src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
View file

@ -38,6 +38,7 @@
#include "mem/ruby/network/garnet/NetworkHeader.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/network/fault_model/FaultModel.hh"
#include "params/BaseGarnetNetwork.hh"
#include "math.h"
@ -50,10 +51,13 @@ class BaseGarnetNetwork : public Network
void init();
int getNiFlitSize() {return m_ni_flit_size; }
int getVCsPerVnet() {return m_vcs_per_vnet; }
bool isFaultModelEnabled() {return m_enable_fault_model;}
FaultModel* fault_model;
protected:
int m_ni_flit_size;
int m_vcs_per_vnet;
bool m_enable_fault_model;
int m_flits_received;
int m_flits_injected;

2
src/mem/ruby/network/garnet/BaseGarnetNetwork.py
View file

@ -36,3 +36,5 @@ class BaseGarnetNetwork(RubyNetwork):
abstract = True
ni_flit_size = Param.Int(16, "network interface flit size in bytes")
vcs_per_vnet = Param.Int(4, "virtual channels per virtual network");
enable_fault_model = Param.Bool(False, "enable network fault model");
fault_model = Param.FaultModel(NULL, "network fault model");

3
src/mem/ruby/network/garnet/NetworkHeader.hh
View file

@ -31,9 +31,6 @@
#ifndef __MEM_RUBY_NETWORK_GARNET_NETWORKHEADER_HH__
#define __MEM_RUBY_NETWORK_GARNET_NETWORKHEADER_HH__
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
enum flit_type {HEAD_, BODY_, TAIL_, HEAD_TAIL_, NUM_FLIT_TYPE_};
enum VC_state_type {IDLE_, VC_AB_, ACTIVE_, NUM_VC_STATE_TYPE_};
enum VNET_type {CTRL_VNET_, DATA_VNET_, NULL_VNET_, NUM_VNET_TYPE_};

17
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
View file

@ -97,6 +97,23 @@ GarnetNetwork_d::init()
NetworkLink_d* net_link = safe_cast<NetworkLink_d*>(*i);
net_link->init_net_ptr(this);
}
// FaultModel: declare each router to the fault model
if(isFaultModelEnabled()){
for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin();
i != m_router_ptr_vector.end(); ++i) {
Router_d* router = safe_cast<Router_d*>(*i);
int router_id=fault_model->declare_router(router->get_num_inports(),
router->get_num_outports(),
router->get_vc_per_vnet(),
getBuffersPerDataVC(),
getBuffersPerCtrlVC());
assert(router_id == router->get_id());
router->printAggregateFaultProbability(cout);
router->printFaultVector(cout);
}
}
}
GarnetNetwork_d::~GarnetNetwork_d()

1
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
View file

@ -39,6 +39,7 @@
#include "mem/ruby/network/Network.hh"
#include "params/GarnetNetwork_d.hh"
class FaultModel;
class NetworkInterface_d;
class MessageBuffer;
class Router_d;

29
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
View file

@ -189,6 +189,35 @@ Router_d::printConfig(ostream& out)
out << "]" << endl;
}
void
Router_d::printFaultVector(ostream& out)
{
int temperature_celcius = BASELINE_TEMPERATURE_CELCIUS;
int num_fault_types = m_network_ptr->fault_model->number_of_fault_types;
float fault_vector[num_fault_types];
get_fault_vector(temperature_celcius, fault_vector);
out << "Router-" << m_id << " fault vector: " << endl;
for (int fault_type_index = 0; fault_type_index < num_fault_types;
fault_type_index++){
out << " - probability of (";
out <<
m_network_ptr->fault_model->fault_type_to_string(fault_type_index);
out << ") = ";
out << fault_vector[fault_type_index] << endl;
}
}
void
Router_d::printAggregateFaultProbability(std::ostream& out)
{
int temperature_celcius = BASELINE_TEMPERATURE_CELCIUS;
float aggregate_fault_prob;
get_aggregate_fault_probability(temperature_celcius,
&aggregate_fault_prob);
out << "Router-" << m_id << " fault probability: ";
out << aggregate_fault_prob << endl;
}
Router_d *
GarnetRouter_dParams::create()
{

12
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
View file

@ -50,6 +50,7 @@ class RoutingUnit_d;
class VCallocator_d;
class SWallocator_d;
class Switch_d;
class FaultModel;
class Router_d : public BasicRouter
{
@ -86,6 +87,8 @@ class Router_d : public BasicRouter
void vcarb_req();
void swarb_req();
void printConfig(std::ostream& out);
void printFaultVector(std::ostream& out);
void printAggregateFaultProbability(std::ostream& out);
double calculate_power();
void calculate_performance_numbers();
@ -93,6 +96,15 @@ class Router_d : public BasicRouter
double get_dynamic_power(){return m_power_dyn;}
double get_static_power(){return m_power_sta;}
double get_clk_power(){return m_clk_power;}
bool get_fault_vector(int temperature, float fault_vector[]){
return m_network_ptr->fault_model->fault_vector(m_id, temperature,
fault_vector);
}
bool get_aggregate_fault_probability(int temperature,
float *aggregate_fault_prob){
return m_network_ptr->fault_model->fault_prob(m_id, temperature,
aggregate_fault_prob);
}
private:
int m_virtual_networks, m_num_vcs, m_vc_per_vnet;

1
src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
View file

@ -31,6 +31,7 @@
#ifndef __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_IN_VC_STATE_HH__
#define __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_IN_VC_STATE_HH__
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/garnet/NetworkHeader.hh"
class InVcState

1
src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
View file

@ -31,6 +31,7 @@
#ifndef __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_OUT_VC_STATE_HH__
#define __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_OUT_VC_STATE_HH__
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/garnet/NetworkHeader.hh"
class OutVcState

7
src/mem/ruby/network/orion/Clock.cc
View file

@ -137,13 +137,10 @@ void Clock::init()
double router_diagonal = m_orion_cfg_ptr->get<double>("ROUTER_DIAGONAL");
double Clockwire = m_tech_param_ptr->get_ClockCap();
double Reswire = m_tech_param_ptr->get_Reswire();
double htree_clockcap;
double htree_res;
int k;
double h;
double cap_clock_buf = 0;
double BufferNMOSOffCurrent = m_tech_param_ptr->get_BufferNMOSOffCurrent();
double BufferPMOSOffCurrent = m_tech_param_ptr->get_BufferPMOSOffCurrent();
@ -151,7 +148,6 @@ void Clock::init()
if (m_tech_param_ptr->is_trans_type_hvt() || m_tech_param_ptr->is_trans_type_nvt())
{
htree_clockcap = (4+4+2+2)*(router_diagonal*1e-6)*Clockwire;
htree_res = (4+4+2+2)*(router_diagonal*1e-6)*Reswire;
wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));
i_static_nmos = BufferNMOSOffCurrent*h*k*15;
@ -160,15 +156,12 @@ void Clock::init()
else
{
htree_clockcap = (8+4+4+4+4)*(router_diagonal*1e-6)*Clockwire;
htree_res = (8+4+4+4+4)*(router_diagonal*1e-6)*Reswire;
wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));
i_static_nmos = BufferNMOSOffCurrent*h*k*29;
i_static_pmos = BufferPMOSOffCurrent*h*k*15;
}
cap_clock_buf = ((double)k)*cap_clock*h;
m_e_htree = (htree_clockcap+cap_clock)*e_factor;
}
else

3
src/mem/ruby/network/simple/PerfectSwitch.cc
View file

@ -71,8 +71,7 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in)
for (int j = 0; j < m_virtual_networks; j++) {
m_in[port][j]->setConsumer(this);
string desc = csprintf("[Queue from port %s %s %s to PerfectSwitch]",
NodeIDToString(m_switch_id), NodeIDToString(port),
NodeIDToString(j));
to_string(m_switch_id), to_string(port), to_string(j));
m_in[port][j]->setDescription(desc);
m_in[port][j]->setIncomingLink(port);
m_in[port][j]->setVnet(j);

1
src/mem/ruby/network/simple/PerfectSwitch.hh
View file

@ -42,7 +42,6 @@
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
class MessageBuffer;
class NetDest;

1
src/mem/ruby/network/simple/SimpleNetwork.hh
View file

@ -34,7 +34,6 @@
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/NodeID.hh"
#include "params/SimpleNetwork.hh"
#include "sim/sim_object.hh"

4
src/mem/ruby/network/simple/Throttle.cc
View file

@ -113,8 +113,8 @@ Throttle::addVirtualNetwork(MessageBuffer* in_ptr, MessageBuffer* out_ptr)
// Set consumer and description
m_in[m_vnets]->setConsumer(this);
string desc = "[Queue to Throttle " + NodeIDToString(m_sID) + " " +
NodeIDToString(m_node) + "]";
string desc = "[Queue to Throttle " + to_string(m_sID) + " " +
to_string(m_node) + "]";
m_in[m_vnets]->setDescription(desc);
m_vnets++;
}

1
src/mem/ruby/network/simple/Throttle.hh
View file

@ -45,7 +45,6 @@
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/system/System.hh"
class MessageBuffer;

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