inorder:regress: host-inst-rate improved ~58%

there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext)
the latest changes to how instruction scheduling (how instructions figure out what they want to
do on each pipeline stage in the inorder model) were able to improve performance by a nice
amount... The latest results for the inorder model process about 100k insts/second
(note: 58% is over the last time run on 64-bit pool machines at UM)
This commit is contained in:
Korey Sewell 2011-02-12 10:14:52 -05:00
parent 470aa289da
commit 2971b8401a
4 changed files with 16 additions and 16 deletions

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@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 27953 # Simulator instruction rate (inst/s)
host_mem_usage 1692040 # Number of bytes of host memory used
host_seconds 3160.33 # Real time elapsed on the host
host_tick_rate 13823537 # Simulator tick rate (ticks/s)
host_inst_rate 106274 # Simulator instruction rate (inst/s)
host_mem_usage 1642336 # Number of bytes of host memory used
host_seconds 831.26 # Real time elapsed on the host
host_tick_rate 52555245 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated
sim_seconds 0.043687 # Number of seconds simulated

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@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 25888 # Simulator instruction rate (inst/s)
host_mem_usage 1480704 # Number of bytes of host memory used
host_seconds 3550.03 # Real time elapsed on the host
host_tick_rate 11417230 # Simulator tick rate (ticks/s)
host_inst_rate 105929 # Simulator instruction rate (inst/s)
host_mem_usage 1434716 # Number of bytes of host memory used
host_seconds 867.59 # Real time elapsed on the host
host_tick_rate 46717114 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated
sim_seconds 0.040531 # Number of seconds simulated

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@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 37548 # Simulator instruction rate (inst/s)
host_mem_usage 223436 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_tick_rate 130476959 # Simulator tick rate (ticks/s)
host_inst_rate 76381 # Simulator instruction rate (inst/s)
host_mem_usage 190468 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_tick_rate 264969940 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated

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@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 32668 # Simulator instruction rate (inst/s)
host_mem_usage 224608 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_tick_rate 120542676 # Simulator tick rate (ticks/s)
host_inst_rate 1339 # Simulator instruction rate (inst/s)
host_mem_usage 191872 # Number of bytes of host memory used
host_seconds 4.35 # Real time elapsed on the host
host_tick_rate 4946645 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated