O3: Update stats for memory order violation checking patch.
This commit is contained in:
Ali Saidi
parent
7dde557fdc
commit
1114be4b78
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@ -115,6 +115,7 @@ assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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@ -413,6 +414,7 @@ assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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@ -448,6 +450,7 @@ assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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is_top_level=false
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latency=1000
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max_miss_count=0
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mshrs=10
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@ -5,10 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Feb 7 2011 01:47:18
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M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
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M5 started Feb 7 2011 01:47:50
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M5 executing on burrito
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M5 compiled Mar 17 2011 21:44:37
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M5 started Mar 17 2011 22:44:08
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M5 executing on zizzer
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -44,4 +43,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 162779779500 because target called exit()
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Exiting @ tick 162342217500 because target called exit()
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@ -1,41 +1,41 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 121046 # Simulator instruction rate (inst/s)
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host_mem_usage 226784 # Number of bytes of host memory used
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host_seconds 4672.20 # Real time elapsed on the host
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host_tick_rate 34840083 # Simulator tick rate (ticks/s)
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host_inst_rate 243015 # Simulator instruction rate (inst/s)
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host_mem_usage 208616 # Number of bytes of host memory used
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host_seconds 2327.23 # Real time elapsed on the host
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host_tick_rate 69757618 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.162780 # Number of seconds simulated
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sim_ticks 162779779500 # Number of ticks simulated
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sim_seconds 0.162342 # Number of seconds simulated
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sim_ticks 162342217500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 63926991 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 71320793 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 193 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 4120736 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 70355271 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 76295210 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1675650 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 19927815 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 20370282 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 315794082 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.905853 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.338192 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::samples 315015358 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44% 32.44% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84% 64.28% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67% 75.95% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95% 78.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25% 82.14% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88% 89.02% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97% 92.99% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70% 93.69% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 315015358 # Number of insts commited each cycle
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system.cpu.commit.COM:count 601856963 # Number of instructions committed
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system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed.
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@ -44,352 +44,352 @@ system.cpu.commit.COM:loads 114514042 # Nu
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 153965363 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4119890 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 60520337 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.575649 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.575649 # CPI: Total CPI of All Threads
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system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 112312480 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 111525313 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11934036500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007009 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 787167 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 569138 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218029 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 38165820 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 18355912888 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.032584 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1285501 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1028584 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 256917 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943 # average number of cycles each access was blocked
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system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 315.175064 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 773498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 151763801 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14613.989982 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 149691133 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 30289949388 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.013657 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2072668 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1597722 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4509676994 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003130 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 474946 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999550 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.156298 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 151763801 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14613.989982 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency
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system.cpu.dcache.occ_%::0 0.999549 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 149691133 # number of overall hits
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system.cpu.dcache.overall_miss_latency 30289949388 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.013657 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2072668 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1597722 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4509676994 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003130 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 474946 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 149582203 # number of overall hits
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system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2073649 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 470850 # number of replacements
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system.cpu.dcache.sampled_refs 474946 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 471038 # number of replacements
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system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.156298 # Cycle average of tags in use
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system.cpu.dcache.total_refs 149691136 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 126698000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 423042 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 45000094 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 877 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4176202 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 688674202 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 142513181 # Number of cycles decode is idle
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||||
system.cpu.decode.DECODE:RunCycles 122905016 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 9698747 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 3338 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5375791 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 163053496 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 423176 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 44833716 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 844 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4163323 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 687863087 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 142213399 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 122593858 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 9601978 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 3402 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5374385 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 163150258 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 163001268 # DTB hits
|
||||
system.cpu.dtb.data_misses 52228 # DTB misses
|
||||
system.cpu.dtb.data_hits 163097305 # DTB hits
|
||||
system.cpu.dtb.data_misses 52953 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 122206073 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 122245622 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 122181392 # DTB read hits
|
||||
system.cpu.dtb.read_misses 24681 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40847423 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 122220880 # DTB read hits
|
||||
system.cpu.dtb.read_misses 24742 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40904636 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 40819876 # DTB write hits
|
||||
system.cpu.dtb.write_misses 27547 # DTB write misses
|
||||
system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 130078631 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed
|
||||
system.cpu.dtb.write_hits 40876425 # DTB write hits
|
||||
system.cpu.dtb.write_misses 28211 # DTB write misses
|
||||
system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 65602641 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.143680 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 325492829 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.144120 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.095910 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 195414198 60.04% 60.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10425646 3.20% 63.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 15856104 4.87% 68.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13952359 4.29% 72.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 12095872 3.72% 76.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 13761061 4.23% 80.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5876732 1.81% 82.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3435361 1.06% 83.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 54675496 16.80% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 265 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 58 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 65559135 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42777500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 253 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 50 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1180 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32318500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 72043.005495 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 65560315 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36252.118644 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 65559135 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42777500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1180 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32318500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.378389 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 774.939822 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 65560315 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36252.118644 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.378270 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 65559135 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42777500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 65446683 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1180 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32318500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1151 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 34 # number of replacements
|
||||
system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 32 # number of replacements
|
||||
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 774.939822 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 65559135 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 66731 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67424273 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43222760 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.839913 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 163081324 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 40875188 # Number of stores executed
|
||||
system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67449018 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43212719 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.845435 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 163178153 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 40932468 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 487722865 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 595805949 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811742 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 486897348 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 595948678 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.812979 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 395904949 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.830098 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 596918670 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4602797 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1364972 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 126095826 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 395837342 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.835470 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597097102 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3115345 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 42628898 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 662516409 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122206136 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6268247 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599001166 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 43958 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 13859 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9698747 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 63343 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 729 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 9862373 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 10156 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 10009719 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 70243 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5936 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 11581784 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3177577 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 844691087 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 489153092 # number of integer regfile writes
|
||||
system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 24101 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 6020 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 11448147 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3134413 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 844972523 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 489243634 # number of integer regfile writes
|
||||
system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 439513912 72.61% 72.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 605269413 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 7095490 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011723 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 605609121 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 5929666 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5209273 73.42% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 47 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 73.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1541723 21.73% 95.15% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 344447 4.85% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 325492829 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.859548 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.691188 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 324617336 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 87236535 26.80% 26.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 66508902 20.43% 47.23% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 78677146 24.17% 71.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 34244703 10.52% 81.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 30387182 9.34% 91.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 15745565 4.84% 96.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 11042338 3.39% 99.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1062135 0.33% 99.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 588323 0.18% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 324617336 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.865224 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 52323110 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 12647 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 28040159 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 65560352 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 65447871 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 65560315 # ITB hits
|
||||
system.cpu.itb.fetch_hits 65447834 # ITB hits
|
||||
system.cpu.itb.fetch_misses 37 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -399,106 +399,106 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256917 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.809098 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.738523 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 197080 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2063108500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.232904 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876353000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232904 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 218939 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34396.642358 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.006381 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 186029 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1131993500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.150316 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32910 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020835500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150316 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32910 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 423042 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 423042 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5257.142857 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.281796 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 368000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 475856 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34449.653358 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 383109 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3195102000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194906 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 92747 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2897188500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194906 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 92747 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.052860 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.487907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1732.123670 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15987.736166 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 475856 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34449.653358 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.052925 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.487884 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 383109 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3195102000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 92747 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 383286 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 92757 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2897188500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 92747 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 74441 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 90342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 74455 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17719.859836 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 477168 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 59318 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 17165638 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.l2cache.writebacks 59322 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 325559560 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 324684436 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 12564419 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 149957875 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 662477 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 118 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 894828905 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 679288968 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 518109497 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 115552585 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 958179178 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1334457472 # The number of ROB writes
|
||||
system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 149604933 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 101 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 894089158 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 678776451 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 517767610 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 115293181 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9601978 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 37552130 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 1965 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 894087193 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 695 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 31 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 73444449 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 30 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 956313792 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1333072216 # The number of ROB writes
|
||||
system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:10:13
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 21:36:19
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -43,4 +42,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 212151683000 because target called exit()
|
||||
Exiting @ tick 196536810500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 130169 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 255152 # Number of bytes of host memory used
|
||||
host_seconds 4627.51 # Real time elapsed on the host
|
||||
host_tick_rate 45845717 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 157384 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 221236 # Number of bytes of host memory used
|
||||
host_seconds 3827.32 # Real time elapsed on the host
|
||||
host_tick_rate 51350965 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 602359950 # Number of instructions simulated
|
||||
sim_seconds 0.212152 # Number of seconds simulated
|
||||
sim_ticks 212151683000 # Number of ticks simulated
|
||||
sim_insts 602359870 # Number of instructions simulated
|
||||
sim_seconds 0.196537 # Number of seconds simulated
|
||||
sim_ticks 196536810500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 77353146 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 83702663 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1593 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3826409 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 84369915 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 91120892 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1482138 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 70826872 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 7259535 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 75961485 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 82107435 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1596 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3833895 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 81873360 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 88392158 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1389747 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 70826856 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 7927801 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 408127750 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.475910 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.811076 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 379302454 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.588073 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.904864 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 143768271 35.23% 35.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 130628056 32.01% 67.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 60243177 14.76% 81.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 18962619 4.65% 86.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 17622510 4.32% 90.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 14296756 3.50% 94.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 13120148 3.21% 97.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 2226678 0.55% 98.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 7259535 1.78% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 123535993 32.57% 32.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 123034003 32.44% 65.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 59238565 15.62% 80.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 18407109 4.85% 85.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 17194886 4.53% 90.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 14352047 3.78% 93.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 7619076 2.01% 95.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 7992974 2.11% 97.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 7927801 2.09% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 408127750 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 602360001 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 379302454 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 602359921 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 997573 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 533522759 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 148952624 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 533522695 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 148952608 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 1328 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 219173667 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 219173635 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 3887306 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 602360001 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 6327 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 105586113 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 602359950 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 602359950 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.704402 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.704402 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1392 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 1379 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 140500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.009339 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 13 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 13 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 139573989 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7875.361074 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 139338017 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3111966000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001691 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 235972 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 40375 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1540397000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 195597 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 1357 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 1357 # number of StoreCondReq hits
|
||||
system.cpu.commit.branchMispredicts 3894768 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 602359921 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 6311 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 86755718 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 602359870 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 602359870 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.652556 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.652556 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1359 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 10642.857143 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 1345 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 149000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.010302 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 139417902 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13041.209813 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7899.689585 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 139176030 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3154303500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001735 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 241872 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 46005 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1547288500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001405 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 195867 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 1341 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 1341 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 19453.548688 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10358.949737 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 68088613 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 25852171016 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.019144 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1328918 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1081042 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2567735025 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247876 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4395.291476 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17903.398328 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10349.195917 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 67926226 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 26699427444 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.021483 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1491305 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1243450 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2565099954 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003570 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247855 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4339.606397 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 467.742670 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 2182 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 466.744813 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 2251 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9590526 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 9768454 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 208991520 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18508.736727 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 207426630 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 28964137016 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.007488 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1564890 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1121417 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4108132025 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002122 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 443473 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 208835433 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 17224.859864 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 207102256 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 29853730944 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.008299 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1733177 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1289455 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4112388454 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 443722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.932917 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 208991520 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18508.736727 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999720 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.852027 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 208835433 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 17224.859864 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 207426630 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 28964137016 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.007488 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1564890 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1121417 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4108132025 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002122 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 443473 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 207102256 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 29853730944 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.008299 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1733177 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1289455 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4112388454 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 443722 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 439373 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 443469 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 439626 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 443722 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.932917 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 207429374 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 89412000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 394062 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 84592597 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 1269 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 6208796 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 740088879 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 168706146 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 141255851 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15304229 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 4703 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 13573155 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 4094.852027 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 207104942 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 89209000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 394231 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 63976815 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 1279 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 5983185 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 722294449 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 163843845 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 138493802 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 12857426 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 4707 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 12987991 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 91120892 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 73409824 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 157341177 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 853332 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 706778220 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 2056 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 4584124 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.214754 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 73409824 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 78835284 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.665738 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 423431978 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.775923 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.853239 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 88392158 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 71392458 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 153990332 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 937286 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 689759462 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 1876 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 4453848 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.224874 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 71392458 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 77351232 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.754784 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 392159879 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.871937 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.898017 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 266090925 62.84% 62.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 25382675 5.99% 68.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 18707202 4.42% 73.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 23120734 5.46% 78.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 11518747 2.72% 81.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 12813304 3.03% 84.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 4581816 1.08% 85.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7541689 1.78% 87.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 53674886 12.68% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 238169672 60.73% 60.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 25123756 6.41% 67.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 18408287 4.69% 71.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22743537 5.80% 77.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 11348841 2.89% 80.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 12044698 3.07% 83.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 4472652 1.14% 84.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7314673 1.87% 86.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 52533763 13.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 423431978 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 392159879 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 73409824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35098.824786 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34224.447514 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 73408888 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32852500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 71392458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35440.133038 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34413.407821 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 71391556 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 31967000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 936 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 212 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 24778500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 186 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 24640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 716 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 101956.788889 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 99708.877095 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 73409824 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35098.824786 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 73408888 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32852500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 71392458 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35440.133038 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 71391556 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 31967000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 936 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 212 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 24778500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 902 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 186 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 24640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 716 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.307623 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 630.012478 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 73409824 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35098.824786 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.304966 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 624.569528 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 71392458 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35440.133038 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 73408888 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32852500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 71391556 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 31967000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 936 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 212 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 24778500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 902 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 186 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 24640000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 716 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 33 # number of replacements
|
||||
system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 716 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 630.012478 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 73408888 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 624.569528 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 71391556 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 871389 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 73892971 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 61798 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.506493 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 238982736 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 73900874 # Number of stores executed
|
||||
system.cpu.idleCycles 913743 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 73697015 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 61594 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.622192 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 239145114 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 73370419 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 738975685 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 633750064 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.595052 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 736423030 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 631861927 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.594969 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 439728869 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.493625 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 634774515 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4294677 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 946102 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 181732576 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5902 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2934920 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 84682953 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 707943366 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 165081862 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6085968 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 639209952 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 15519 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 438148553 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.607490 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 632828783 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4309187 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 803250 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 176095139 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2962571 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 82148484 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 689113035 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 165774695 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6093175 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 637640921 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 25921 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2353 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15304229 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 50818 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 3894 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 12857426 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 66942 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 8944 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 24296735 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 57403 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 8942 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 25088282 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 91350 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 930118 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 15159 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 32779951 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 14461910 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 930118 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 636408 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3658269 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1727320002 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 496802288 # number of integer regfile writes
|
||||
system.cpu.ipc 1.419645 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.419645 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 610036 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 15544 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 27142530 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 11927457 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 610036 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 629916 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3679271 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1724659056 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 495413856 # number of integer regfile writes
|
||||
system.cpu.ipc 1.532435 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.532435 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 402470959 62.37% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6564 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 167645097 25.98% 88.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 75173297 11.65% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 400825580 62.27% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 168279108 26.14% 88.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 74622820 11.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 645295920 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 7755028 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.012018 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 643734096 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3962863 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006156 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 198697 2.56% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 7348141 94.75% 97.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 208190 2.68% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 103447 2.61% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 3410396 86.06% 88.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 449020 11.33% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 423431978 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.523966 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.473546 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 392159879 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641509 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.552773 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 124767045 29.47% 29.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 123576315 29.18% 58.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 78343969 18.50% 77.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 46750040 11.04% 88.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 32770284 7.74% 95.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 12193598 2.88% 98.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 3344839 0.79% 99.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 823717 0.19% 99.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 862171 0.20% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 108979156 27.79% 27.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 107509921 27.41% 55.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 76161777 19.42% 74.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 48539013 12.38% 87.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 26829140 6.84% 93.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 16734433 4.27% 98.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5468015 1.39% 99.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1020625 0.26% 99.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 917799 0.23% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 423431978 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.520836 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 392159879 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.637693 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 653050928 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 1722505687 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 633750048 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 814020305 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 707874308 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 645295920 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 7260 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 105229644 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 726877 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 933 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 212022368 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.int_alu_accesses 647696939 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 1683941472 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 631861911 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 776045363 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 689044280 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 643734096 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 7161 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 86384301 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 350574 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 162192952 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -415,114 +415,106 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 247874 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.539920 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.130694 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 189432 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2008274000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235773 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58442 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1826963000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235773 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58442 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 196316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34255.152982 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.089447 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 163665 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1118465000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.166319 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32651 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 247857 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.314168 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31234.317248 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 189417 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2006322000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235781 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58440 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825333500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235781 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58440 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 196581 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34342.701958 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31091.800820 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 163901 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1122319500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.166242 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32680 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1015393000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166288 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32645 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 394062 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 394062 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5824.362606 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1015893500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32674 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 394231 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 394231 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5401.428571 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.737794 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 353 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.739445 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 350 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 2056000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 1890500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 444190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34324.690152 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 353097 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3126739000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.205077 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 91093 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 444438 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34335.398376 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 353318 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3128641500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.205023 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 91120 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2842356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.205063 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 91087 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2841227000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.205009 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 91114 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.056232 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.489259 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1842.604757 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16032.025879 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 444190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34324.690152 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.057195 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.487171 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1874.172488 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15963.624075 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 444438 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34335.398376 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 353097 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3126739000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.205077 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 91093 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 353318 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3128641500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.205023 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 91120 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2842356000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.205063 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 91087 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2841227000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.205009 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 91114 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 72891 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 88396 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 72928 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 88438 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17874.630636 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 418802 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17837.796563 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 419147 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 58120 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 59394757 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 28028248 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 181732576 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 84682953 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 939363465 # number of misc regfile reads
|
||||
system.cpu.l2cache.writebacks 58125 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 25818022 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 23076545 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 176095139 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 82148484 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 922030590 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 9368 # number of misc regfile writes
|
||||
system.cpu.numCycles 424303367 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 393073622 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 12681660 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 471025546 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 63633162 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 186161185 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2954668 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 2083466922 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 728669573 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 566468470 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 137330990 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15304229 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 71846492 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 95442921 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:BlockCycles 9403650 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 471025466 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 50023577 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 176787767 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1922723 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 2034086698 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 711204835 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 553151366 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 138512795 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 12857426 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 54492155 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 82125897 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2083466826 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 107422 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 6263 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 128424972 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6268 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 1108813717 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1431196844 # The number of ROB writes
|
||||
system.cpu.timesIdled 36620 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2034086602 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 106086 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 6114 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 91032587 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6112 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 1060489680 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1391088840 # The number of ROB writes
|
||||
system.cpu.timesIdled 36977 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:36
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 23:04:27
|
||||
M5 started Mar 17 2011 23:11:57
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -43,4 +42,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 601458924000 because target called exit()
|
||||
Exiting @ tick 582418059000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 165526 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 228372 # Number of bytes of host memory used
|
||||
host_seconds 8491.76 # Real time elapsed on the host
|
||||
host_tick_rate 70828550 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 165963 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210376 # Number of bytes of host memory used
|
||||
host_seconds 8469.40 # Real time elapsed on the host
|
||||
host_tick_rate 68767363 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1405604152 # Number of instructions simulated
|
||||
sim_seconds 0.601459 # Number of seconds simulated
|
||||
sim_ticks 601458924000 # Number of ticks simulated
|
||||
sim_seconds 0.582418 # Number of seconds simulated
|
||||
sim_ticks 582418059000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 98804590 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 100538418 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 97659749 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 99018650 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 5348296 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 105813144 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 105813144 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 5339067 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 86248929 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 21328117 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 26710610 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1172142071 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1136580592 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.310530 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66% 35.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51% 78.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52% 82.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84% 91.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81% 94.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71% 95.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19% 97.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93% 98.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1136580592 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1489523295 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -44,435 +44,434 @@ system.cpu.commit.COM:loads 402512844 # Nu
|
|||
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 569360986 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5348296 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 219357232 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.855801 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.855801 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 295701881 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 294883584 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11994549000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 818297 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 604806 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 291461478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14664.632652 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7474.067095 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 290645276 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11969302500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 816202 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 602863 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1594510000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 165080859 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 27466889545 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010584 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1765957 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1497892 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 15381.021476 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13048.542893 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 165025455 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 28014392657 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010916 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1821361 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1553325 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3497479243 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 955.151791 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 946.591376 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 462548697 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 15269.953551 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 459964443 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 39461438545 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005587 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2584254 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2102698 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5032067799 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 458308294 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 15159.332747 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 455670731 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 39983695157 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005755 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2637563 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2156188 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5091989243 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.424247 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 462548697 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 15269.953551 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999855 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 459964443 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 39461438545 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005587 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2584254 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2102698 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5032067799 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 455670731 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 39983695157 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005755 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2637563 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2156188 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5091989243 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 477467 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 477286 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.424247 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 459965762 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 132304000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 428418 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 393633604 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 1750740297 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 405697462 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 351107020 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 30410517 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 21703374 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 105813144 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 173097327 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 375137003 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1429156 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1755978912 # Number of instructions fetch has processed
|
||||
system.cpu.dcache.tagsinuse 4095.405595 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 428224 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 373408138 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 1727466392 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 394807577 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 348667632 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 27885594 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 19696634 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1257771 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1732289789 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 6170643 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 173097327 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 98804590 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1202551977 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 5787763 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 170870865 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 97659749 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1164465575 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.491538 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.715145 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 827414974 68.80% 68.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 82887161 6.89% 75.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 45821959 3.81% 79.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22740624 1.89% 81.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 32823900 2.73% 86.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 14990247 1.25% 88.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7935660 0.66% 88.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 134105255 11.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 793817442 68.17% 68.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 81924135 7.04% 75.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 44978693 3.86% 79.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22977276 1.97% 81.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 33360505 2.86% 83.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 33148842 2.85% 86.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 14858388 1.28% 88.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7508131 0.64% 88.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 131892163 11.33% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 173095532 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 62951000 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1164465575 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16956220 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 10464632 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 170870865 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35272.495756 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.283732 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 170869098 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 62326500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45401500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_misses 1767 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45468000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1297 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 133767.799073 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 131843.439815 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 173097327 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35070.194986 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 173095532 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 62951000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 170870865 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35272.495756 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 170869098 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 62326500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 45401500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_misses 1767 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 45468000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1297 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.509893 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1044.260820 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 173097327 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35070.194986 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.511535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 173095532 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 62951000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 170869098 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 62326500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 45401500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_misses 1767 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 45468000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1297 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 158 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 159 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1296 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1044.260820 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173095532 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1047.623620 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 170869098 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 365872 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 89387996 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 102270134 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 590482875 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 169844843 # Number of stores executed
|
||||
system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 89603944 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 100373819 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 591399205 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 170154785 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1212153101 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1472498717 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.958322 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1209973999 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1473173854 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.961076 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1161632680 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1473870381 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5524543 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2523096 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 468104279 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4542154 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 188276128 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 1708972338 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 420638032 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6157621 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1475771230 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 66958 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1162877329 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.264705 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1474297623 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4553877 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 187022162 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 1689106884 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 421244420 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6318503 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1475928628 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 66196 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 9816 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 30410517 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 130917 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 124904328 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 129748862 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 65591435 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 21427986 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes
|
||||
system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 460365 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 237 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 58644458 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 20174020 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes
|
||||
system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685423 59.70% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618241 0.18% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 423844959 28.60% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780228 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1481928851 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3245613 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1482247131 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3391020 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 176489 5.44% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2530154 77.96% 89.96% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 325770 10.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202551977 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127764 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1164465575 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.272899 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 320557298 26.66% 26.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 511598029 42.54% 69.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 219313490 18.24% 87.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 94900060 7.89% 95.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 39948235 3.32% 98.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10701841 0.89% 99.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5167806 0.43% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 227063 0.02% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 138155 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 200593512 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 68539 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 832248 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 279087097 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.350752 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31318.935009 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2080612500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893856000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34037.381235 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958432 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1146379000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044247000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1164465575 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.272494 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 1762732094 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 1585633508 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1482247131 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3099557 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 182705519 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 207600 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2079988000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 60451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893368000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 214628 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34037.437678 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.970916 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1146925500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.156997 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33696 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044743500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33696 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 428224 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.114449 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.108819 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34275.002655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3226991500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 482679 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34275.266339 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3226913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.195051 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94147 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2938103000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2938111500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.195051 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.060606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1985.934249 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15675.618246 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34275.002655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.059800 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.479227 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 388708 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3226991500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94150 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 388532 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3226913500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.195051 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94147 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2938103000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2938111500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.195051 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94147 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 75917 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 91429 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 75916 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 91427 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17661.552495 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 467609 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17662.828910 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 467084 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 59275 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads
|
||||
system.cpu.l2cache.writebacks 59282 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 386274637 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 159916794 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 461157302 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 187022162 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 597198570 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
|
||||
system.cpu.numCycles 1202917849 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1164836119 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 115497905 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 134234465 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 443700933 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 41034559 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2924501033 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1732030714 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1445194568 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 329588798 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 2859629611 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 3448202738 # The number of ROB writes
|
||||
system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 28107626 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 128337052 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 433132347 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 2887426636 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1709740875 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1426816340 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 325737783 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 27885594 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 209164686 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 182045888 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 33660518 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2853766118 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 3085415 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 378977297 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3085429 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 2798818963 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 3405946340 # The number of ROB writes
|
||||
system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 16 2011 15:39:14
|
||||
M5 started Mar 16 2011 15:39:15
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 18 2011 20:12:06
|
||||
M5 started Mar 18 2011 20:12:27
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1066,4 +1066,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 766217705000 because target called exit()
|
||||
Exiting @ tick 751079230500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 213906 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226116 # Number of bytes of host memory used
|
||||
host_seconds 7580.41 # Real time elapsed on the host
|
||||
host_tick_rate 101078599 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 151077 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216016 # Number of bytes of host memory used
|
||||
host_seconds 10732.89 # Real time elapsed on the host
|
||||
host_tick_rate 69979188 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1621493982 # Number of instructions simulated
|
||||
sim_seconds 0.766218 # Number of seconds simulated
|
||||
sim_ticks 766217705000 # Number of ticks simulated
|
||||
sim_seconds 0.751079 # Number of seconds simulated
|
||||
sim_ticks 751079230500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 168460210 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 169652659 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 8971423 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 107161579 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 11445860 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1402522347 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.156127 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1402522347 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1621493982 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 607228182 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.926404 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 325401931 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7152.951878 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 325183672 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2205998500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000671 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 218259 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3345 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1537269500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 214914 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 186952974 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 24137025496 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006552 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1233083 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 982981 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2504097497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 250102 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1101.331236 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 472140500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 513587988 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18150.803874 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 512136646 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 26343023996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002826 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1451342 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 986326 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4041366997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 465016 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999792 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 517710070 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1455125 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 512136646 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 26343023996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002826 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1451342 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 986326 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4041366997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 465016 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 460779 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 460920 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 465016 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 411288 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dcache.tagsinuse 4095.146726 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 411408 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 587921420 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 2472731706 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 429893143 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 331529130 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 99378480 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 53178654 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 625222 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1408639601 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 15384200 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.119823 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 170058043 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 168460210 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.937744 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1501900827 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.699260 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.059388 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1104715792 73.55% 73.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 26107791 1.74% 75.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 14369087 0.96% 76.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 13756932 0.92% 77.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 30207594 2.01% 79.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 20132707 1.34% 80.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 34410865 2.29% 82.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 37556252 2.50% 85.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 220643807 14.69% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1501900827 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 170058043 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35240.756303 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 170056853 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 41936500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1190 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 321 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 30694000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 869 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 195692.581128 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 170058043 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35240.756303 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 170056853 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 41936500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1190 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 30694000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 869 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.387535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 168862206 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 170056853 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 41936500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1223 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1190 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 321 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 30694000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 869 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 11 # number of replacements
|
||||
system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 869 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 793.670730 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 170056853 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 111314295 # Number of branches executed
|
||||
system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 111429178 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 191312994 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 1.227514 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 636597814 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 191695864 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 2089450314 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 2082700302 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1838995466 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.683970 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1430463260 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1424504384 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.224235 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1842743630 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 312936 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 250798855 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2343198083 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 444901950 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 13067063 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1843921293 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 56293 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes
|
||||
system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes
|
||||
system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1856988356 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4273878 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1501900827 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.236425 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1501900827 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.236213 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2351086127 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1543114167 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3071160852 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2343198002 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1856988356 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 721564206 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 191287 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2024064500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235198 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58826 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832767000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235198 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58826 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 215772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 182665 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1130166500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.153435 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33107 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1026523000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33107 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 411408 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 411408 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.099879 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 465885 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34310.106273 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 373952 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3154231000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.197330 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 91933 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2859290000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.197330 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 91933 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.058491 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.491164 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 373812 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 91930 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 373952 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3154231000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.197330 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 91933 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2859290000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.197330 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 91933 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 73661 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 73660 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 89268 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18011.074755 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 455256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 58542 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 537232403 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads
|
||||
system.cpu.numCycles 1532435411 # number of cpu cycles simulated
|
||||
system.cpu.l2cache.writebacks 58532 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 528261825 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 206728085 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 615851374 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 250798855 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 931071836 # number of misc regfile reads
|
||||
system.cpu.numCycles 1502158462 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 169288978 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3775835718 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4802062478 # The number of ROB writes
|
||||
system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 298516669 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 493321936 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 70 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 5808956116 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2397077126 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2395694665 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 310095488 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 99378480 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 429812969 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 777700015 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 64 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5808956052 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 2976 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 89 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 706930007 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 89 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3734283918 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4785794667 # The number of ROB writes
|
||||
system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,12 +10,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/chips/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/chips/pd/randd/dist/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -926,7 +926,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -946,7 +946,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -1074,7 +1074,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 15 2011 18:10:57
|
||||
M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
|
||||
M5 started Mar 15 2011 18:10:59
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 17 2011 22:48:41
|
||||
M5 started Mar 17 2011 22:50:14
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 118370500
|
||||
Exiting @ tick 1900831106500 because m5_exit instruction encountered
|
||||
info: Launching CPU 1 @ 109002500
|
||||
Exiting @ tick 1901725056500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,12 +10,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/chips/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/chips/pd/randd/dist/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -493,7 +493,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -513,7 +513,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -641,7 +641,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 15 2011 18:10:57
|
||||
M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
|
||||
M5 started Mar 15 2011 18:10:59
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 17 2011 22:48:41
|
||||
M5 started Mar 17 2011 22:50:11
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1865724648500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1863702170500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
|
|||
boot_cpu_frequency=500
|
||||
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
|
|
@ -493,7 +493,7 @@ type=ExeTracer
|
|||
|
||||
[system.diskmem]
|
||||
type=PhysicalMemory
|
||||
file=/chips/pd/randd/dist/disks/ael-arm.ext2
|
||||
file=/dist/m5/system/disks/ael-arm.ext2
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@ warn: instruction 'mcr icimvau' unimplemented
|
|||
For more information see: http://www.m5sim.org/warn/21b09adb
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/21b09adb
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
For more information see: http://www.m5sim.org/warn/7998f2ea
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/21b09adb
|
||||
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:37
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:12:00
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 02:37:41
|
||||
M5 started Mar 18 2011 02:38:20
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 84388283500 because m5_exit instruction encountered
|
||||
Exiting @ tick 83363125500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1 +1 @@
|
|||
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed.
|
||||
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -496,9 +496,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 21:03:35
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 20:50:23
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -28,4 +27,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 45750115000 because target called exit()
|
||||
Exiting @ tick 44810819000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 113142 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 388016 # Number of bytes of host memory used
|
||||
host_seconds 806.51 # Real time elapsed on the host
|
||||
host_tick_rate 56726347 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 152339 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 354000 # Number of bytes of host memory used
|
||||
host_seconds 598.99 # Real time elapsed on the host
|
||||
host_tick_rate 74810841 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91249480 # Number of instructions simulated
|
||||
sim_seconds 0.045750 # Number of seconds simulated
|
||||
sim_ticks 45750115000 # Number of ticks simulated
|
||||
sim_insts 91249440 # Number of instructions simulated
|
||||
sim_seconds 0.044811 # Number of seconds simulated
|
||||
sim_ticks 44810819000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 25060777 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 26802034 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 13379 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 1583014 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 23911601 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 29845348 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 62467 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 18706972 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 599512 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 24834182 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 26488589 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 13381 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 1577083 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 23759439 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 29547808 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 61655 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 18706964 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 663516 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 85858585 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.062935 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.459577 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 84127548 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.084806 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.485867 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 40879742 47.61% 47.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 22675219 26.41% 74.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 9677073 11.27% 85.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 7600715 8.85% 94.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2662481 3.10% 97.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 219814 0.26% 97.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 922714 1.07% 98.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 621315 0.72% 99.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 599512 0.70% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 39814306 47.33% 47.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 21951452 26.09% 73.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 9558270 11.36% 84.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 7643193 9.09% 93.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2705607 3.22% 97.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 250022 0.30% 97.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 904462 1.08% 98.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 636720 0.76% 99.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 663516 0.79% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 85858585 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 91262089 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 84127548 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 91262049 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 56148 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 72532978 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 22575791 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 72532946 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 22575783 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 3888 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 27322459 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 27322443 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 1602069 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91262089 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 554321 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 39090054 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 91249480 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 91249480 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.002748 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.002748 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 6707 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 6700 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001044 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.commit.branchMispredicts 1596327 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91262049 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 554313 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 37919647 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 91249440 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 91249440 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.982161 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.982161 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 6690 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 6683 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001046 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 24501880 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5328.400499 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2255.904510 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23546851 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5088777000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.038978 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 955029 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 51059 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2039270000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036894 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 903970 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 5711 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 5711 # number of StoreCondReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 24486290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5359.849313 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2292.924521 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23465767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5469849500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.041677 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1020523 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 105108 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2098977500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.037385 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 915415 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 5703 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 5703 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 24088.951664 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22495.719344 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 4561444 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4180324405 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.036650 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 173537 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 127274 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1040719464 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009770 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 46263 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2889.691936 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26966.662287 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29146.815533 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 4581638 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4135148895 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.032385 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 153343 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 118616 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1012181463 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007334 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 34727 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.268241 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 29.593485 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 7453 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 29.532208 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 7497 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 21536874 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 21653347 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 29236861 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 8213.167334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 28108295 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 9269101405 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.038601 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1128566 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 178333 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3079989464 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.032501 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 29221271 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 8182.363570 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 28047405 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 9604998395 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.040172 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1173866 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 223724 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3111158963 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.032515 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 950142 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.852939 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3493.638101 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 29236861 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 8213.167334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.852969 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3493.759701 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 29221271 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 8182.363570 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 28108295 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 9269101405 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.038601 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1128566 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 178333 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3079989464 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.032501 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 28047405 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 9604998395 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.040172 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1173866 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 223724 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3111158963 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.032515 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 950142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 946137 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 950233 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 946046 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 950142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3493.638101 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 28120706 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 19296981000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 943150 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 18515611 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 9136 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4758893 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 141080898 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 33469255 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 33017602 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 5612232 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 30592 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 856116 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 3493.759701 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 28059791 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 18895308000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 943121 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 17616091 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 8947 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 4756283 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 139877523 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 32952944 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 32754638 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 5463778 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 29965 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 803874 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,81 +158,81 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 29845348 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 15520576 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 34753915 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 276813 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 143294690 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 20423 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 1615761 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.326178 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 15520576 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 25123244 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.566058 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 91470816 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.578120 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.573721 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 29547808 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 15301199 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 34415849 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 249988 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 142060699 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 19814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 1615180 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.329695 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 15301199 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 24895837 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.585116 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 89591325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.597262 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.585030 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 56780865 62.08% 62.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 6426529 7.03% 69.10% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 6459161 7.06% 76.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 4449430 4.86% 81.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3594685 3.93% 84.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1897731 2.07% 87.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1934782 2.12% 89.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3238407 3.54% 92.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 6689226 7.31% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 55239268 61.66% 61.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 6349932 7.09% 68.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 6414208 7.16% 75.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 4426055 4.94% 80.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3460419 3.86% 84.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1907279 2.13% 86.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1921135 2.14% 88.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3244772 3.62% 92.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 6628257 7.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 91470816 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 87 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 78 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 15520576 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35610.047847 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.604720 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 15519740 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 29770000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000054 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 158 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 23327000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.fetch.rateDist::total 89591325 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 83 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 76 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 15301199 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35691.320293 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34369.469027 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 15300381 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 29195500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 818 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 23302500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 678 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 22890.471976 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 22566.933628 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 15520576 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35610.047847 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 15519740 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 29770000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000054 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 836 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 158 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 23327000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 15301199 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35691.320293 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 15300381 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 29195500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 818 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 23302500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.276985 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 567.265894 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 15520576 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35610.047847 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.276968 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 567.230284 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 15301199 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35691.320293 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 15519740 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 29770000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000054 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 836 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 158 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 23327000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 15300381 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 29195500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 818 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 23302500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 678 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -240,161 +240,161 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 567.265894 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 15519740 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 567.230284 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 15300381 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 29415 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 20970115 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 54598 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.133641 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 30199659 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 5140774 # Number of stores executed
|
||||
system.cpu.idleCycles 30314 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 20925598 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 54439 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.157971 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 30252486 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 5191190 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 127211016 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 102056385 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.487951 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 127253538 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 102147077 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.488789 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 62072763 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.115368 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 102572716 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 1825852 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 421320 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 32016564 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 690308 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 299404 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 6585994 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 130352707 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 25058885 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2046100 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 103728443 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 170905 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 62200099 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.139759 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 102625765 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 1807591 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 317265 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 31522248 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 688638 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 326826 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 6607421 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 129183212 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 25061296 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2026821 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 103779294 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 171143 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 1567 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 5612232 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 206705 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 178 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 5463778 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 193382 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 21484 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 353411 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 19757 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 21870 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 400446 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 24865 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 3168 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 14115 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 9440772 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1839326 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 3168 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 298332 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1527520 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 259522598 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 80481877 # number of integer regfile writes
|
||||
system.cpu.ipc 0.997260 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.997260 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 8946464 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1860761 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 14115 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 301414 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1506177 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 259793995 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 80578248 # number of integer regfile writes
|
||||
system.cpu.ipc 1.018163 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.018163 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 74292294 70.24% 70.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 10639 0.01% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 38 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 26262906 24.83% 95.08% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5208640 4.92% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 74302206 70.22% 70.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 10686 0.01% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 37 0.00% 70.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 26235832 24.80% 95.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5257328 4.97% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 105774543 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 160185 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.001514 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 105806115 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 187983 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.001777 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 52262 32.63% 32.63% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 32.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 62957 39.30% 71.95% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 44939 28.05% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 52416 27.88% 27.88% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 27.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 77701 41.33% 69.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 57839 30.77% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 91470816 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.156375 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.444584 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 89591325 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180986 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458768 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 39774696 43.48% 43.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 24298391 26.56% 70.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 14242553 15.57% 85.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6365982 6.96% 92.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 2257550 2.47% 95.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2688100 2.94% 97.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1607594 1.76% 99.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 110764 0.12% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 125186 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 38472986 42.94% 42.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 23460608 26.19% 69.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 14306679 15.97% 85.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6444522 7.19% 92.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 2370548 2.65% 94.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2667663 2.98% 97.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1626344 1.82% 99.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 115788 0.13% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 126187 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 91470816 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.156003 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 190 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 87 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 105934631 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 303205662 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 102056298 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 169015166 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 129602907 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 105774543 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 695202 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 38714982 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 25765 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 140881 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 72800988 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 89591325 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.180587 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 94 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 184 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 160 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 105994004 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 301419127 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 102146993 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 166681021 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 128435251 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 105806115 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 693522 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 37544982 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 27773 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 139209 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 69554944 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,107 +416,107 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 46263 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34215.214251 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.691726 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 31724 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 497455000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.314268 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses 34763 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.176697 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.826604 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 20224 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 497658000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.418232 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451257000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.314268 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451273500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418232 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 904648 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34281.219272 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.589641 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 903631 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 34864000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001124 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1017 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 31227000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001110 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_accesses 916057 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34296.259843 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.565737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 915041 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 34845000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001109 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1016 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 31233000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001096 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1004 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 943150 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 943150 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_accesses 943121 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 943121 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 102.932573 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 104.841512 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 950911 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34219.529442 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 935355 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 532319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.016359 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 15556 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 482484000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016345 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_accesses 950820 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34233.558341 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 935265 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 532503000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.016360 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 15555 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 482506500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016347 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 15543 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.012326 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.249116 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 403.905799 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8163.029985 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 950911 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34219.529442 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.012390 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.250098 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 405.999438 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8195.227045 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 950820 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34233.558341 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 935355 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 532319000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.016359 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 15556 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 482484000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016345 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_hits 935265 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 532503000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.016360 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 15555 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 482506500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016347 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 15543 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 704 # number of replacements
|
||||
system.cpu.l2cache.replacements 702 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15528 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 8566.935784 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1598337 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 8601.226483 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1627979 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 32 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 1440720 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 1005315 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 32016564 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 6585994 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 198555291 # number of misc regfile reads
|
||||
system.cpu.memDep0.conflictingLoads 745583 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 374535 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 31522248 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 6607421 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 197265421 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1603310 # number of misc regfile writes
|
||||
system.cpu.numCycles 91500231 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 89621639 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 3003526 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 72121263 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2932731 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 36158864 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2288265 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:BlockCycles 2572422 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 72121223 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2896922 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 35550108 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1943384 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 352780022 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 136654080 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 107391797 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 31135789 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 5612232 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 6274602 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 35270531 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 655 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 352779367 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 9285803 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 702152 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 13506306 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 702838 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 215605482 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 266316908 # The number of ROB writes
|
||||
system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:RenameLookups 350234554 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 135614727 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 106518917 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 30912538 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 5463778 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 5897124 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 34397691 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 648 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 350233906 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 9195355 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 700993 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 13077041 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 701919 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 212639994 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 263827329 # The number of ROB writes
|
||||
system.cpu.timesIdled 1459 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -488,7 +491,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
||||
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -5,11 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 12 2011 02:22:23
|
||||
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
|
||||
M5 started Feb 12 2011 02:22:27
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
||||
M5 compiled Mar 18 2011 20:12:06
|
||||
M5 started Mar 18 2011 20:12:16
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -28,4 +27,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 98622214000 because target called exit()
|
||||
Exiting @ tick 81396224000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 133029 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 371192 # Number of bytes of host memory used
|
||||
host_seconds 2091.22 # Real time elapsed on the host
|
||||
host_tick_rate 47160241 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 173311 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 350460 # Number of bytes of host memory used
|
||||
host_seconds 1605.16 # Real time elapsed on the host
|
||||
host_tick_rate 50708988 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 278192519 # Number of instructions simulated
|
||||
sim_seconds 0.098622 # Number of seconds simulated
|
||||
sim_ticks 98622214000 # Number of ticks simulated
|
||||
sim_seconds 0.081396 # Number of seconds simulated
|
||||
sim_ticks 81396224000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 38238795 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 38788801 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 2465320 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 29309710 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 13548841 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 149131695 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.865415 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 149131695 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 278192519 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -44,344 +44,344 @@ system.cpu.commit.COM:loads 90779388 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 122219139 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.585179 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 63345837 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 6389.837562 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.424936 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 61126773 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 14179458500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.035031 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 2219064 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 247059 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5532312000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.031131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1972005 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 17790.751735 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17644.271587 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 31202641 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4218365144 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.007542 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 237110 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 131111 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1870275144 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003371 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 105999 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3445.783133 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 44.431869 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 286000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 94785588 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7490.439865 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 92329414 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 18397823644 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.025913 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2456174 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 378170 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7402587144 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.021923 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2078004 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.994940 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 98554006 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2344618 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 92329414 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 18397823644 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.025913 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2456174 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 378170 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7402587144 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.021923 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2078004 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2074218 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2073904 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2078000 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1442059 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dcache.tagsinuse 4075.274681 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1448011 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 13645155 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 390459172 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 68124952 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 66154578 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 12492114 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 1207010 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 310077 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 225429246 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 2638813 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.267241 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 30855910 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 38238795 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.384765 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 161623809 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.462324 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.240695 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 92912734 57.49% 57.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4821587 2.98% 60.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 3003433 1.86% 62.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6267047 3.88% 66.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 7344013 4.54% 70.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 5575474 3.45% 74.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 8028911 4.97% 79.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 6451248 3.99% 83.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 27219362 16.84% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 161623809 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 41 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 30855910 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36182.458888 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35209.772952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 30854633 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 46205000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 264 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35667500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1013 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 30488.767787 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 30855910 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36182.458888 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 30854633 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 46205000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 35667500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1013 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.396500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 34651154 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1341 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 30854633 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 46205000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1277 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 264 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 35667500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1013 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 60 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 63 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1012 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 812.031019 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 30854633 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 33755681 # Number of branches executed
|
||||
system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 32808514 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 33964004 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 2.009454 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 141715314 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 34352421 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 330470543 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 324204287 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.735351 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 254272214 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 243011799 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.991519 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 325408414 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 440749 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 39643183 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 367028456 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 107362893 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 4685170 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 327123971 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 4283 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 66782 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 12492114 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 101572 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 43812375 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 577634708 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 302216415 # number of integer regfile writes
|
||||
system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 57.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 237293 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 3275 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 30748500 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 8203432 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 572686347 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 291536884 # number of integer regfile writes
|
||||
system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 331809141 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1744992 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.745109 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 161623809 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 2.052972 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 161623809 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 2.038234 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 455842500 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 367027991 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 331809141 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 88592670 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 42420 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.399714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42420 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 63955 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1437979500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.396714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 42056 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308610000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42056 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1973004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34215.506485 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.372893 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1938541 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1179169000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.017467 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34463 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1069158500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017467 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34463 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
|
|
@ -389,85 +389,85 @@ system.cpu.l2cache.UpgradeReq_misses 1 # nu
|
|||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.Writeback_accesses 1448011 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1448011 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 43.067418 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 2079015 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34202.596741 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2002496 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2617148500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.036805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 76519 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2377768500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.036805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 76519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.196368 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.354446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2002530 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 76793 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 2002496 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2617148500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.036805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 76519 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2377768500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.036805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 76519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 49342 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 49066 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 77071 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18049.049074 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3319249 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 29450 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads
|
||||
system.cpu.numCycles 197244429 # number of cpu cycles simulated
|
||||
system.cpu.l2cache.writebacks 29185 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 49162785 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 10611644 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 121527888 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 39643183 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 211169577 # number of misc regfile reads
|
||||
system.cpu.numCycles 162792449 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 3023364 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 574492355 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 837321831 # The number of ROB writes
|
||||
system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 130274 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 72054036 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 12 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 941229334 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 383108308 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 343773743 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 63044913 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 12492114 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 11002939 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 95429551 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 586 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 941228748 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6443 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 468 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 25868384 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 462 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 502617672 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 746575877 # The number of ROB writes
|
||||
system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,9 +496,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 21:06:16
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 21:12:45
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -72,4 +71,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 345312086000 because target called exit()
|
||||
Exiting @ tick 334221751500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 137280 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 259116 # Number of bytes of host memory used
|
||||
host_seconds 4176.43 # Real time elapsed on the host
|
||||
host_tick_rate 82681134 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 115680 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225512 # Number of bytes of host memory used
|
||||
host_seconds 4956.26 # Real time elapsed on the host
|
||||
host_tick_rate 67434212 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 573342432 # Number of instructions simulated
|
||||
sim_seconds 0.345312 # Number of seconds simulated
|
||||
sim_ticks 345312086000 # Number of ticks simulated
|
||||
sim_insts 573342252 # Number of instructions simulated
|
||||
sim_seconds 0.334222 # Number of seconds simulated
|
||||
sim_ticks 334221751500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 147772005 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 179850444 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 2706777 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 15769862 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 177167417 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 222186718 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 11015263 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 116606359 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 6384495 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 146248863 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 176289381 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 2732047 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 15792639 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 173563787 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 218029317 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 10847475 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 116606323 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 7009812 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 625227574 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.919163 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.394949 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 605188855 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.949598 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.450627 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 321936350 51.49% 51.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 172149257 27.53% 79.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 71132688 11.38% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 25332872 4.05% 94.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 16298028 2.61% 97.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 5238396 0.84% 97.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5475401 0.88% 98.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1280087 0.20% 98.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 6384495 1.02% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 311994753 51.55% 51.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 161715098 26.72% 78.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 68890759 11.38% 89.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 25427565 4.20% 93.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 17265141 2.85% 96.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 5227008 0.86% 97.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5978308 0.99% 98.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1680411 0.28% 98.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 7009812 1.16% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 625227574 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 574686316 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 605188855 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 574686136 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 9757362 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 473702213 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 126773184 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 473702069 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 126773148 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 1488542 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 184377289 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 184377217 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 21484787 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 574686316 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 3877900 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 412531053 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 573342432 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 573342432 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.204558 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.204558 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 2604377 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 8985.294118 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 2604343 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 305500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000013 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 34 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 34 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 142611934 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10444.092632 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7123.731625 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 141561974 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 10965879500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007362 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1049960 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 198181 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 6067845000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 851779 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 2232169 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 2232169 # number of StoreCondReq hits
|
||||
system.cpu.commit.branchMispredicts 21479549 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 574686136 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 3877864 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 397226721 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 573342252 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 573342252 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.165872 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.165872 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 2604331 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 7833.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 2604295 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 282000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 142077585 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10714.447779 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6999.796046 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 141007026 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11470448500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007535 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1070559 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 219878 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5954593500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005987 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 850681 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 2232133 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 2232133 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 14556.604118 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12575.325933 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 52898794 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 19513302500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.024715 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1340512 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1004937 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4219965000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006187 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 335575 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 15646.653056 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13092.754811 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 52838909 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 21911526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.025819 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1400397 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1056210 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4506356000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006346 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 344187 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 167.850641 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 166.282010 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 196851240 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 12750.277769 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8664.484223 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 194460768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 30479182000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.012144 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2390472 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1203118 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10287810000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006032 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1187354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 196316891 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 13509.740562 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 193845935 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 33381974500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.012587 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2470956 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1276088 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10460949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006086 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1194868 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.990968 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4059.005774 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 196851240 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 12750.277769 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8664.484223 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.991141 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4059.712057 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 196316891 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 13509.740562 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8754.899704 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 194460768 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 30479182000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.012144 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2390472 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1203118 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10287810000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006032 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1187354 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 193845935 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 33381974500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.012587 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2470956 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1276088 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10460949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006086 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1194868 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1183253 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1187349 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 1190756 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1194852 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4059.005774 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 199297291 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7009642000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1060964 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 99879126 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 76616 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 33311544 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 1125601371 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 285750111 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 233945838 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 60722303 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 217312 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5652498 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 4059.712057 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 198682392 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 6636207000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1064084 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 88183325 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 76234 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 32910143 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 1105509065 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 280452015 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 231095248 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 58620851 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 216396 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5458266 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 222186718 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 126406345 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 243921736 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 3067508 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1002303501 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 5157741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 21891737 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.321719 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 126406345 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 158787268 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.451301 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 685949876 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.695461 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.705917 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 218029317 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 124225331 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 240845488 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 2943984 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 985167776 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 5168276 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 21620484 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.326175 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 124225331 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 157096338 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.473824 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 663809705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.722895 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.715589 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 442039747 64.44% 64.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 19794967 2.89% 67.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 33809086 4.93% 72.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 38427852 5.60% 77.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 37318627 5.44% 83.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 18120316 2.64% 85.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 18761200 2.74% 88.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 13563249 1.98% 90.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 64114832 9.35% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 422975812 63.72% 63.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 19490823 2.94% 66.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 33888081 5.11% 71.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 39021858 5.88% 77.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 37073066 5.58% 83.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 16674783 2.51% 85.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 18304020 2.76% 88.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 13198645 1.99% 90.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 63182617 9.52% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 685949876 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 663809705 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 126406345 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14514.118554 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10752.907416 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 126392073 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 207145500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 14272 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1030 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 142390000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 13242 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 124225331 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14458.321717 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10724.096566 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 124210983 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 207448000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000115 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 14348 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1010 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 143038000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000107 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 13338 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 9548.392612 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 9323.748912 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 126406345 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 14514.118554 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 10752.907416 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 126392073 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 207145500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 14272 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1030 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 142390000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 13242 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 124225331 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 14458.321717 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 124210983 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 207448000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000115 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 14348 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1010 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 143038000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000107 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 13338 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.510807 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1046.133692 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 126406345 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 14514.118554 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 10752.907416 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.515723 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1056.199986 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 124225331 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 14458.321717 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 10724.096566 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 126392073 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 207145500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 14272 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1030 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 142390000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 13242 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 124210983 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 207448000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000115 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 14348 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1010 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 143038000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000107 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 13338 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 11420 # number of replacements
|
||||
system.cpu.icache.sampled_refs 13237 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 11505 # number of replacements
|
||||
system.cpu.icache.sampled_refs 13322 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1046.133692 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 126392073 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1056.199986 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 124210983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 4674297 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 138497028 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12955862 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.047031 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 218144468 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 66082703 # Number of stores executed
|
||||
system.cpu.idleCycles 4633799 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 138142297 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12876339 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.081001 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 219209030 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 66375463 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 791991230 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 685951510 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.483503 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 788336695 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 685357565 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.485374 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 382930143 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.993234 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 714914629 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 25642135 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3016830 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 198100704 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2797901 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 7211752 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 114500942 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 987209077 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 152061765 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 22604731 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 723105102 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 125136 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 382637953 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.025304 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 714473572 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 25616212 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2985344 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 194483391 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2822926 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 7041770 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 112758143 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 971912060 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 152833567 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 22948891 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 722588050 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 111523 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 5730 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 60722303 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 194914 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 15327 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 58620851 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 199342 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 4520039 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 10219 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 77 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 5719789 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 15891 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 426900 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 14200 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 71327515 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 56896833 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 426900 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 10953146 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 14688989 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1644155544 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 528242138 # number of integer regfile writes
|
||||
system.cpu.ipc 0.830180 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.830180 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 94425 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 23277 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 67710242 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 55154074 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 94425 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 10897628 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 14718584 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 1644594876 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 527674952 # number of integer regfile writes
|
||||
system.cpu.ipc 0.857727 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.857727 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 515258626 69.10% 69.10% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 385422 0.05% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 76 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 160083543 21.47% 90.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 69982165 9.38% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 513661883 68.90% 68.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 386634 0.05% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 160948708 21.59% 90.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 70539607 9.46% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 745709835 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10315393 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.013833 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 745536941 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10587544 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.014201 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 2085862 20.22% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 20.22% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5244548 50.84% 71.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 2984983 28.94% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 2110928 19.94% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 19.94% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5343659 50.47% 70.41% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 3132957 29.59% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 685949876 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.087120 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.369949 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 663809705 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.123118 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.406431 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 322453331 47.01% 47.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 152222370 22.19% 69.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 115563946 16.85% 86.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 51318874 7.48% 93.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 26753309 3.90% 97.43% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 7611284 1.11% 98.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 7427521 1.08% 99.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 2025759 0.30% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 573482 0.08% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 308965401 46.54% 46.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 144668555 21.79% 68.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 110038020 16.58% 84.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 52350888 7.89% 92.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 29088648 4.38% 97.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 8324547 1.25% 98.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 7676240 1.16% 99.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1874333 0.28% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 823073 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 685949876 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.079762 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 188 # Number of floating instruction queue reads
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 663809705 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.115333 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 756025132 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 2190014235 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 685951494 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 1361390433 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 969594427 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 745709835 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4658788 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 386770433 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 2329486 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 780888 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 694137605 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 756124359 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 2167725865 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 685357549 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 1330295825 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 954351941 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 745536941 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4683780 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 371189493 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 2254982 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 805916 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 656102390 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -415,109 +415,115 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 335898 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.024874 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.131537 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 231251 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3584267000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.311544 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 104647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3244594000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311544 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 104647 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 864685 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34190.230739 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.195188 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 736835 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 4371221000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.147857 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 127850 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3965242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.147841 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 127836 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_hits 3 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.Writeback_accesses 1060964 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1060964 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_accesses 344509 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.550447 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.397937 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 231966 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3855447500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.326677 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 112543 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3489440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.326677 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 112543 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 863665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34190.772563 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31027.525161 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 739947 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 4230014000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.143248 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 123718 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3838260000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.143233 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 123705 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_hits 13 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.187500 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.187500 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1064084 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1064084 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 6.548774 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.437044 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1200583 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34217.594206 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31012.314879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 968086 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 7955488000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.193653 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 232497 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7209836000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.193642 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 232483 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_accesses 1208174 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34222.582229 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 971913 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 8085461500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.195552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 236261 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7327700500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.195541 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 236248 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.235755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.409558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 7725.216525 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13420.386918 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1200583 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34217.594206 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31012.314879 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.213211 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.422279 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 6986.504420 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13837.237986 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1208174 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34222.582229 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.984271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 968086 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 7955488000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.193653 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 232497 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7209836000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.193642 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 232483 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_hits 971913 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 8085461500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.195552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 236261 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7327700500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.195541 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 236248 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 213383 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 233608 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 217136 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 237363 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 21145.603443 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1529846 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 251648343000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 169621 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 69633889 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 68589382 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 198100704 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 114500942 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1230715150 # number of misc regfile reads
|
||||
system.cpu.l2cache.tagsinuse 20823.742406 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1527916 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 241420822000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 171788 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 54696737 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 61739671 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 194483391 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 112758143 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1214411471 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 344749 # number of misc regfile writes
|
||||
system.cpu.numCycles 690624173 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 668443504 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 13815420 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 448650958 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 11250412 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 301168670 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 11014301 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 24 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2669060394 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1077315314 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 784928020 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 223928164 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 60722303 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 28708652 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 336277040 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 1236 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2669059158 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 57606667 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2819849 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 78103763 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2819793 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 1606053310 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 2035197393 # The number of ROB writes
|
||||
system.cpu.timesIdled 113698 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 12415646 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 448650778 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 9472750 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 295422634 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 10451000 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 22 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2625367121 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1059917765 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 772660527 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 221340746 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 58620851 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 26319878 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 324009746 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 1198 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 2625365923 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 49689950 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2845114 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 73898765 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2845067 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 1570084762 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 2002485622 # The number of ROB writes
|
||||
system.cpu.timesIdled 109548 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -488,7 +491,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
||||
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 16 2011 11:44:34
|
||||
M5 started Mar 16 2011 11:44:36
|
||||
M5 compiled Mar 18 2011 20:12:06
|
||||
M5 started Mar 18 2011 20:27:45
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/tests/fast/build/X86_SE/m5.fast -d build/X86_SE/tests/fast/build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -73,4 +73,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 610952992000 because target called exit()
|
||||
Exiting @ tick 584102039000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,475 +1,475 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 189714 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 264736 # Number of bytes of host memory used
|
||||
host_seconds 8051.48 # Real time elapsed on the host
|
||||
host_tick_rate 75880827 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 135575 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 259672 # Number of bytes of host memory used
|
||||
host_seconds 11277.84 # Real time elapsed on the host
|
||||
host_tick_rate 51792019 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1527476062 # Number of instructions simulated
|
||||
sim_seconds 0.610953 # Number of seconds simulated
|
||||
sim_ticks 610952992000 # Number of ticks simulated
|
||||
sim_insts 1528988756 # Number of instructions simulated
|
||||
sim_seconds 0.584102 # Number of seconds simulated
|
||||
sim_ticks 584102039000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 218742072 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 237579384 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 16731555 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 252612909 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 252612909 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 149616585 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:branches 149758588 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 41097639 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1035309655 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.476842 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1527476062 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1035309655 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1528988756 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 383724495 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 384102160 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 532790180 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 533262345 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1527476062 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses
|
||||
system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.764037 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 323639192 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8444.942006 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 320628262 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 47924451000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.009303 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 3010930 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1248670 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14882183500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005445 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1762260 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 147539972 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 38441849000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010862 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1620229 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 607112 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 18287673500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006792 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1013117 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 185.317160 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 472799393 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18648.960228 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 468168234 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 86366300000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.009795 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4631159 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1855782 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 33169857000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005870 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2775377 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.998173 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 464556927 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4555120 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 468168234 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 86366300000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.009795 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4631159 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1855782 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 33169857000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005870 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2775377 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2504740 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2529347 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2533443 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2229751 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dcache.tagsinuse 4088.515779 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2231104 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 187291575 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 2489806075 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 422005844 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 404270583 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 108207267 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 21741653 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 252612909 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 3788635 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1360923556 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 78504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 19199509 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.216240 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 188594062 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 218742072 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.164971 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1143516922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.221243 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.208291 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 707206433 61.84% 61.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 32665502 2.86% 64.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 37223305 3.26% 67.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 33654778 2.94% 70.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 21116720 1.85% 72.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 40194771 3.52% 76.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 44517058 3.89% 80.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 36097891 3.16% 83.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 190840464 16.69% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 31 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 1143516922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 188594062 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6510.591789 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3406.338578 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 188336504 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1676855000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001366 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 257558 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 872465500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001358 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 256130 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16890.533363 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 188594062 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 6510.591789 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 188336504 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1676855000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001366 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 257558 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 872465500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001358 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 256130 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.469099 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 190192396 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 269416 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 188336504 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1676855000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001366 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 257558 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 872465500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001358 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 256130 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 9298 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 9707 # number of replacements
|
||||
system.cpu.icache.sampled_refs 11150 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 960.715295 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 188329447 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 3 # number of writebacks
|
||||
system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 175611349 # Number of branches executed
|
||||
system.cpu.icache.writebacks 6 # number of writebacks
|
||||
system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 173444431 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 164362000 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 1.602205 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 612750445 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 165978925 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 2150204737 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 2110704618 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1858331416 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.678632 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1432457554 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 9848 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 24902521 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1432391344 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.590759 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1864643959 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2269927 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 223085364 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2324941378 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 446771520 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 30325762 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1871702722 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1004270 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 42321 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 108207267 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 1500742 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 122021898 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 146459 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes
|
||||
system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 446588314 23.46% 91.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2443893 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1254 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 202017116 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 73925179 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes
|
||||
system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1903752720 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1902028484 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 11137895 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1143516922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.663315 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 147240856 12.30% 86.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 95168175 7.95% 94.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1913488177 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5017400187 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2368907105 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1903752720 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9295 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1472780543 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1143516922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.628165 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3120531509 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2324931719 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1902028484 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 9659 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 793159883 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 528344 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8477993500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.318983 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 247472 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7672259500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318983 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247472 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1768657 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34159.791245 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.301453 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1429599 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11582150500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191704 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 339058 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10512595500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191704 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 339058 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 244851 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.349749 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.844007 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_hits 1225 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 10317500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994997 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 243626 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7553342500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994997 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 243626 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2231110 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2231110 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.363240 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 2544473 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34201.394643 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1957943 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 20060144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.230511 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 586530 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18184855000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230511 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 586530 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.236559 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.418198 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1955854 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 563673 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1957943 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 20060144000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.230511 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 586530 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18184855000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230511 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 586530 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 553099 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 575744 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 594863 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 404346 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 432038121 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 167866970 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads
|
||||
system.cpu.numCycles 1221905985 # number of cpu cycles simulated
|
||||
system.cpu.l2cache.tagsinuse 21455.072285 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3190393 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 306991433000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 412280 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 354716110 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 139191834 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 586119276 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 223082546 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1024751398 # number of misc regfile reads
|
||||
system.cpu.numCycles 1168204079 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3418371032 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4851844016 # The number of ROB writes
|
||||
system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 50725953 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 53866080 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 461056510 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 8215 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 5693696762 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2424853504 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2263021553 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 385257729 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 108207267 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 138255029 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 835722526 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 18042 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5693678720 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 14434 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2322 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 301380597 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2286 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3319156234 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4758159890 # The number of ROB writes
|
||||
system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,15 +5,14 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:47
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:58:43
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.133333
|
||||
Exiting @ tick 136326909500 because target called exit()
|
||||
OO-style eon Time= 0.100000
|
||||
Exiting @ tick 113012733500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,395 +1,395 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 86954 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 233264 # Number of bytes of host memory used
|
||||
host_seconds 4319.23 # Real time elapsed on the host
|
||||
host_tick_rate 31562755 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 169900 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215004 # Number of bytes of host memory used
|
||||
host_seconds 2210.56 # Real time elapsed on the host
|
||||
host_tick_rate 51124064 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.136327 # Number of seconds simulated
|
||||
sim_ticks 136326909500 # Number of ticks simulated
|
||||
sim_insts 375574812 # Number of instructions simulated
|
||||
sim_seconds 0.113013 # Number of seconds simulated
|
||||
sim_ticks 113012733500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 35459307 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 43810174 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1426 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 5614078 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 35351284 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 62456368 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 12662154 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 44587532 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 12699878 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 30270394 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 39807126 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1409 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 5223677 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 44587533 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 16035403 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 256761438 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.552665 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.229770 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 216073988 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.845037 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 124458766 48.47% 48.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 50855968 19.81% 68.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 19650568 7.65% 75.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 20252396 7.89% 83.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 10775172 4.20% 88.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 8940653 3.48% 91.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5548934 2.16% 93.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 3579103 1.39% 95.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 12699878 4.95% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 398664594 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 216073988 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 398664587 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 316365851 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:int_insts 316365844 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 94754489 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 168275218 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5609735 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 98058240 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.725964 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.725964 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 96258234 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33424.104432 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31993.883792 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 96256587 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 55049500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1647 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 666 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31386000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
|
||||
system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574812 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.601812 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 93199835 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33131.956912 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31878.172589 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 93198164 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 55363500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1671 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 686 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30170.708432 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35486.697966 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73502915 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 537461000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30218.957186 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.663747 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73502931 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 537837000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 17814 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 14619 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 113380000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_misses 17798 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 14601 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 113412500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3197 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40651.222462 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 39861.573171 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 169778963 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30446.045938 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169759502 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 592510500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000115 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 19461 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 15285 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 144766000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 166720564 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30468.976321 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 166701095 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 593200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 19469 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 15287 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 144812500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.804250 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3294.209288 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 169778963 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30446.045938 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.803985 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 169759502 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 592510500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000115 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 19461 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 15285 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 144766000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 166701095 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 593200500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 19469 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 15287 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 144812500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 781 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 786 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3294.209288 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169759505 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3293.121210 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 662 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 21274693 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4421 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11335478 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 536362282 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 133648516 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100614513 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15751437 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 13226 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1223716 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 185361756 # DTB accesses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_hits 185333824 # DTB hits
|
||||
system.cpu.dtb.data_misses 27932 # DTB misses
|
||||
system.cpu.dcache.writebacks 664 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 5613634 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4438 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 10679460 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 490538381 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 118863884 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 90994213 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 9813191 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 13275 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 602257 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 183645342 # DTB accesses
|
||||
system.cpu.dtb.data_acv 48603 # DTB access violations
|
||||
system.cpu.dtb.data_hits 183566296 # DTB hits
|
||||
system.cpu.dtb.data_misses 79046 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 105061264 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 105034802 # DTB read hits
|
||||
system.cpu.dtb.read_misses 26462 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 80300492 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 80299022 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1470 # DTB write misses
|
||||
system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 104167812 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed
|
||||
system.cpu.dtb.read_accesses 103678274 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 48603 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 103600815 # DTB read hits
|
||||
system.cpu.dtb.read_misses 77459 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 79967068 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 79965481 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1587 # DTB write misses
|
||||
system.cpu.fetch.Branches 56786170 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 58423687 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 93710532 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1318185 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 502037270 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 48121461 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.013431 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 272512875 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.014472 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.018403 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 5229387 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.251238 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 58423687 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 41692920 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.221154 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 225887179 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.222513 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.113255 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 168345063 61.78% 61.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 11153110 4.09% 65.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 11633749 4.27% 70.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6179991 2.27% 72.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 14406846 5.29% 77.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 9876694 3.62% 81.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 7175383 2.63% 83.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3990457 1.46% 85.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 39751582 14.59% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 132176647 58.51% 58.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 9507177 4.21% 62.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 8947595 3.96% 66.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6461834 2.86% 69.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 13588400 6.02% 75.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 8169586 3.62% 79.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 6674990 2.96% 82.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 2889669 1.28% 83.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 37471281 16.59% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 161565122 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 106206809 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 64422617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 156225500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4846 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 935 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120601500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3911 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 225887179 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 159270832 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 104392422 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 58423687 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 32309.424084 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30830.816483 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 58418912 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 154277500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000082 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4775 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 868 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120456000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3907 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16472.159806 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 14952.370617 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 64427463 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 32238.031366 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 64422617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 156225500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4846 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 935 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120601500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3911 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 58423687 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 32309.424084 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 58418912 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 154277500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000082 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4775 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 868 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120456000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3907 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.891874 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1826.557172 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 64427463 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 32238.031366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.890605 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 64422617 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 156225500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4846 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 935 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120601500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3911 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 58418912 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 154277500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000082 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4775 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 868 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120456000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3907 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1989 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3911 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1986 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3907 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1826.557172 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 64422617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1823.959859 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 58418912 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 140947 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51277692 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27475837 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.546858 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 185361805 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 80300524 # Number of stores executed
|
||||
system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 48687009 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 26082950 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.805331 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 183693980 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 79967080 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 290508552 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 417530576 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.697486 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 258989364 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 404042671 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.726642 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 202625525 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.531358 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 418298724 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6117740 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3299737 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 117580442 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6436127 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92914841 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 496723261 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 105061281 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 8627247 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 421756759 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 169659 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 188192474 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.787598 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 405020447 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6012421 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 86376940 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 454930236 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 103726900 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 9802128 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 408050842 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 63 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 28133 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15751437 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 607162 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8600585 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 30861 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 10208559 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 663165 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 175980 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 22825953 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 19394112 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 421360455 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 182139619 # number of integer regfile writes
|
||||
system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 5629 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 192417 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 12228157 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 12856211 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 406883956 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 173490032 # number of integer regfile writes
|
||||
system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 175581687 40.80% 40.80% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2149994 0.50% 41.30% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.30% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34727338 8.07% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7823215 1.82% 51.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2961066 0.69% 51.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16836878 3.91% 55.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569908 0.36% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 106389727 24.72% 80.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82310612 19.12% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 430384006 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 8629906 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.020052 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 417852970 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10358398 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 24317 0.28% 0.28% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.28% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 44159 0.51% 0.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 3134 0.04% 0.83% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 6690 0.08% 0.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 1184776 13.73% 14.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 981942 11.38% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5222594 60.52% 86.53% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1162294 13.47% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 272512875 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579316 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717067 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 225887179 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.849830 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 101003308 37.06% 37.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 58496079 21.47% 58.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 41698303 15.30% 73.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 27977806 10.27% 84.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 23760656 8.72% 92.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 11524865 4.23% 97.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5162499 1.89% 98.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 2198912 0.81% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 690447 0.25% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 175992487 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 346671239 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 165916628 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 231922736 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 262987844 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 796105773 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 251613948 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 330463092 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 92662056 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 866219 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 70475093 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 225887179 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.848699 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 283872417 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 428847047 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 417852970 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 47599271 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 64427767 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 58423991 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 64427463 # ITB hits
|
||||
system.cpu.itb.fetch_hits 58423687 # ITB hits
|
||||
system.cpu.itb.fetch_misses 304 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -399,28 +399,28 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34601.370736 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.240357 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 108544500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.980619 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3201 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.558495 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.559133 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 64 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 108554500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.980006 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98684500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980619 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98685500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980006 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.345635 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.742134 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34349.065531 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31163.354625 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 145228500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 145193500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 131754500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 131727500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_accesses 664 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 664 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks.
|
||||
|
|
@ -429,76 +429,76 @@ system.cpu.l2cache.blocked::no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8087 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34461.298207 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 723 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 253773000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.910597 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_accesses 8089 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34457.903313 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 725 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 253748000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.910372 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 230439000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.910597 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 230413000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.910372 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.108677 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011575 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3561.129355 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 379.284506 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 8087 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34461.298207 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.108576 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011590 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 723 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 253773000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.910597 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_hits 725 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 253748000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.910372 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7364 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 230439000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.910597 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 230413000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.910372 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 13 # number of replacements
|
||||
system.cpu.l2cache.replacements 14 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3940.413861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3937.604676 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 71937561 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 7819910 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 6085624 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 106982646 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 86376940 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 272653822 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 226025470 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 138476212 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7076079 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:BlockCycles 3360184 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 311 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 122116498 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 688559814 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 522801702 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 337940166 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96677987 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 326649614 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 361910200 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 740781417 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 1009223784 # The number of ROB writes
|
||||
system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:RenameLookups 625408393 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 477751875 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 306658733 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 88296359 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9813191 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1960754 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47126400 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 292973848 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 332434545 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 340193 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 36156 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5383709 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 654965356 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 919674888 # The number of ROB writes
|
||||
system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:19:35
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 21:17:10
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -17,5 +16,5 @@ Eon, Version 1.1
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.170000
|
||||
Exiting @ tick 173737299500 because target called exit()
|
||||
OO-style eon Time= 0.150000
|
||||
Exiting @ tick 151690547000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 105768 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 263952 # Number of bytes of host memory used
|
||||
host_seconds 3300.30 # Real time elapsed on the host
|
||||
host_tick_rate 52642890 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 139716 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230084 # Number of bytes of host memory used
|
||||
host_seconds 2498.39 # Real time elapsed on the host
|
||||
host_tick_rate 60715238 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 349065960 # Number of instructions simulated
|
||||
sim_seconds 0.173737 # Number of seconds simulated
|
||||
sim_ticks 173737299500 # Number of ticks simulated
|
||||
sim_insts 349065980 # Number of instructions simulated
|
||||
sim_seconds 0.151691 # Number of seconds simulated
|
||||
sim_ticks 151690547000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 20216884 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 26426271 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 53555 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3385203 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 19876693 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 36665151 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 7335349 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 30506630 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 6423122 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 20064052 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 26320164 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 70860 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3397653 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 19939350 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 36470167 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 7288898 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 30506634 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 7586748 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 340217087 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.026011 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.609311 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 297315049 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.174063 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.830157 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 170345162 50.07% 50.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 99509001 29.25% 79.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 28782057 8.46% 87.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 16235874 4.77% 92.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 9859908 2.90% 95.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 4137947 1.22% 96.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 2696620 0.79% 97.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 2227396 0.65% 98.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 6423122 1.89% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 153879250 51.76% 51.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 68550967 23.06% 74.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 27297315 9.18% 83.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 16153153 5.43% 89.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 11239863 3.78% 93.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 6593648 2.22% 95.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 3258875 1.10% 96.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 2755230 0.93% 97.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 7586748 2.55% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 340217087 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 349066572 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 297315049 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 349066592 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 287529355 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 94648992 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 287529371 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 94648996 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 11033 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 177024829 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 177024837 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 3371287 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 349066572 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 3555471 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 38687255 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 349065960 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 349065960 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.995441 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.995441 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 11396 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.commit.branchMispredicts 3383925 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 349066592 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 3555475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 29789757 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 349065980 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 349065980 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.869122 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.869122 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 11409 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 11394 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 11407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 97345834 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33073.410778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30661.926872 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 97342735 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 102494500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 95593398 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33910.477454 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30796.467863 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95590382 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 102274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 3099 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1376 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 52830500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_misses 3016 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1289 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 53185500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1723 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 11142 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 11142 # number of StoreCondReq hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1727 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 82052672 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 31425.125183 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35401.373723 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 82033500 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 602482500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000234 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 19172 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 16333 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 100504500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32102.269728 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35439.570120 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 82033727 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 608177500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 18945 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 16107 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 100577500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2839 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2838 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 19863.636364 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 39324.588119 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 38940.524331 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 218500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 179398506 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31654.483409 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33611.354669 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 179376235 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 704977000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_accesses 177646070 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32350.598789 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 177624109 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 710451500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 22271 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 17709 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 153335000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4562 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_misses 21961 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 17396 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 153763000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4565 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.753400 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3085.925842 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 179398506 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31654.483409 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33611.354669 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.753135 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 3084.839186 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 177646070 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32350.598789 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33683.023001 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 179376235 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 704977000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits 177624109 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 710451500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 22271 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 17709 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 153335000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4562 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_misses 21961 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 17396 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 153763000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4565 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1404 # number of replacements
|
||||
system.cpu.dcache.replacements 1402 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4562 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3085.925842 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179398771 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3084.839186 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 177646672 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1024 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 177195286 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 71850 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 7266733 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 418101627 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 89070591 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 70339326 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 7142428 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 201892 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 3611883 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.writebacks 1023 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 139700611 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 71034 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 7228761 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 408720937 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 85085390 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 69907941 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 5944542 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 201754 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2621106 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 36665151 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 39333951 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 76200894 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 219495 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 327214024 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 19976 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 3525022 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.105519 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 39333951 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 27552233 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.941692 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 347359514 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.232140 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.649316 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 36470167 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 38697287 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 74568068 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 438780 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 318859916 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 20920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 3516150 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.120212 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 38697287 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 27352950 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.051021 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 303259590 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.373282 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.757488 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 271714378 78.22% 78.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 9098002 2.62% 80.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 5614129 1.62% 82.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6550857 1.89% 84.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 5401109 1.55% 85.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 4665359 1.34% 87.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 3626849 1.04% 88.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 4186087 1.21% 89.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 36502744 10.51% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 229247017 75.59% 75.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 9043835 2.98% 78.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 5596121 1.85% 80.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 6435084 2.12% 82.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 5316543 1.75% 84.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 4702041 1.55% 85.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 3588760 1.18% 87.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 4030820 1.33% 88.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 35299369 11.64% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 347359514 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 185260821 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 130652752 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 39333951 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 12067.997808 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8366.912236 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 39317524 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 198241000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000418 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 16427 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 817 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 130607500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000397 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 15610 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 303259590 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 185391890 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 131539425 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 38697287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 11752.678794 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8359.038302 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 38681235 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 188654000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000415 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 16052 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 130727000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000404 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 15639 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 2518.739526 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2473.857316 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 39333951 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 12067.997808 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 8366.912236 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 39317524 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 198241000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000418 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 16427 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 817 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 130607500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000397 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 15610 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 38697287 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 11752.678794 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 38681235 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 188654000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000415 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 16052 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 130727000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000404 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 15639 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.894157 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1831.233820 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 39333951 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 12067.997808 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 8366.912236 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.893029 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1828.923459 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 38697287 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 11752.678794 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 8359.038302 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 39317524 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 198241000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000418 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 16427 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 817 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 130607500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000397 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 15610 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 38681235 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 188654000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000415 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 16052 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 130727000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000404 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 15639 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 13743 # number of replacements
|
||||
system.cpu.icache.sampled_refs 15610 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 13772 # number of replacements
|
||||
system.cpu.icache.sampled_refs 15636 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1831.233820 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 39317524 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1828.923459 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 38681233 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 115086 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 31830970 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 56108 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.053222 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 183288367 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 84683782 # Number of stores executed
|
||||
system.cpu.idleCycles 121505 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 31578601 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 55958 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.199464 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 183601400 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 84386759 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 326571947 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 364037870 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.499993 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 302383263 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 361678841 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.513536 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 163283573 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.047668 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 364350526 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3594029 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 769955 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 107131506 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 3647750 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5567384 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 91507860 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 387756246 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 98604585 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2702902 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 365967822 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 137 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 155284641 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.192160 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 362172156 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3565736 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 6223 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 104097603 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 3634765 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5762936 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 89132401 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 378858680 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 99214641 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3439356 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 363894705 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 7142428 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 44317 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 5944542 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 242 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 109 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1040195 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1660 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 3534064 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 41128 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 177809 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 44277 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 12482513 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 9132023 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 177809 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 383406 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3210623 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 849409468 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 186524631 # number of integer regfile writes
|
||||
system.cpu.ipc 1.004580 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.004580 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 165865 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 275 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 9448606 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 6756560 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 165865 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 371765 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 3193971 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 845234199 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 184410543 # number of integer regfile writes
|
||||
system.cpu.ipc 1.150586 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.150586 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 127517311 34.59% 34.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2147275 0.58% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.17% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684179 1.81% 36.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.98% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8181294 2.22% 39.20% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3298042 0.89% 40.10% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567223 0.43% 40.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20157898 5.47% 45.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7156749 1.94% 47.93% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077602 1.92% 49.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175287 0.05% 49.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 99210852 26.91% 76.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 85497009 23.19% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 125195241 34.08% 34.08% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 2147341 0.58% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684288 1.82% 36.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8300579 2.26% 38.75% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402180 0.93% 39.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567163 0.43% 40.10% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20208124 5.50% 45.60% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197502 1.96% 47.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077300 1.93% 49.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 100094621 27.25% 76.78% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 85284432 23.22% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 368670724 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6503476 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017640 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 367334061 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 12197832 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.033206 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 17082 0.26% 0.26% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.08% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1526 0.02% 0.36% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.36% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 257921 3.97% 4.33% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 627 0.01% 4.34% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 182979 2.81% 7.15% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.15% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 4701020 72.28% 79.44% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1337212 20.56% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5508 0.05% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1308 0.01% 0.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233645 1.92% 2.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 627 0.01% 2.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.64% 4.66% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.66% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 7433926 60.94% 65.60% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 4195769 34.40% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 347359514 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.061352 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.398972 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 303259590 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211286 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.642583 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 164898974 47.47% 47.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 92888126 26.74% 74.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 38718431 11.15% 85.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 21127173 6.08% 91.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 18826760 5.42% 96.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 6953193 2.00% 98.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 2902778 0.84% 99.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 878088 0.25% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 165991 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 151189237 49.85% 49.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 63508236 20.94% 70.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 27984122 9.23% 80.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 21601335 7.12% 87.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 21428973 7.07% 94.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10561255 3.48% 97.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 4840954 1.60% 99.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1678139 0.55% 99.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 467339 0.15% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 347359514 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.061000 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 120434049 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 238151015 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 116197950 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 135223001 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 254740151 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 853728758 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 247839920 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 290561942 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 384041147 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 368670724 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3658991 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 38001894 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 675335 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 103520 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 93798234 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 303259590 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.210801 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 125152178 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 243612430 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 116468066 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 124271782 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 254379715 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 807715135 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 245210775 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 282420664 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 375156709 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 367334061 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3646013 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 27828461 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1202021 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 90538 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 56356812 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,107 +416,114 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 2839 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34387.668320 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.927711 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 97042000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.994012 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 2822 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88136500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994012 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 2822 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 17333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34339.384829 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.919476 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 13009 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 148483500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.249466 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4324 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 2835 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34417.287895 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31254.348598 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 96953500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.993651 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 2817 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88043500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993651 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 2817 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 17363 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34335.562731 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31152.310924 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 13027 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 148879000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.249726 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4336 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 133081000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246466 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4272 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1024 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1024 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 133456500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.246732 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4284 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1023 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1023 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.521086 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.520377 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 20172 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34358.452281 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.746828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 13026 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 245525500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.354253 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7146 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 20198 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34367.747798 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 13045 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 245832500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.354144 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7153 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 221217500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.351676 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7094 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 221500000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.351569 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7101 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.103741 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011357 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3399.382463 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 372.162474 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 20172 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34358.452281 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.746828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.103835 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3402.462231 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 371.534678 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 20198 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34367.747798 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.789748 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 13026 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 245525500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.354253 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7146 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 13045 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 245832500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.354144 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7153 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 52 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 221217500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.351676 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7094 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 221500000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.351569 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7101 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 53 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 5193 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 5202 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3771.544937 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13092 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3773.996909 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13111 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 57304786 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 64927444 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 107131506 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 91507860 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 972227372 # number of misc regfile reads
|
||||
system.cpu.memDep0.conflictingLoads 11713930 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 25106151 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 104097603 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 89132401 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 963036910 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 43097542 # number of misc regfile writes
|
||||
system.cpu.numCycles 347474600 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 303381095 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 9320114 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 344460442 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1304973 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 97580493 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 14494347 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 1601896967 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 403426158 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 392194299 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 65706997 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 7142428 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 28947021 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47733854 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 827888222 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 774008745 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 138662461 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 12572275 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 80571383 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3693310 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 721545269 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 782665651 # The number of ROB writes
|
||||
system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 825170 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 344460462 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 48323 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 92021425 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 4815329 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 1568557063 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 396913119 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 386168908 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 66099997 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 5944542 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 17924907 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 41708443 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 797945883 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 770611180 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 120443549 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 12410013 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 58864418 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3692672 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 668582127 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 763657860 # The number of ROB writes
|
||||
system.cpu.timesIdled 2620 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:38
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:45:13
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1390,4 +1389,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 699853545500 because target called exit()
|
||||
Exiting @ tick 689104583500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 179836 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 233568 # Number of bytes of host memory used
|
||||
host_seconds 10137.27 # Real time elapsed on the host
|
||||
host_tick_rate 69037678 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 161084 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215416 # Number of bytes of host memory used
|
||||
host_seconds 11317.35 # Real time elapsed on the host
|
||||
host_tick_rate 60889223 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_seconds 0.699854 # Number of seconds simulated
|
||||
sim_ticks 699853545500 # Number of ticks simulated
|
||||
sim_seconds 0.689105 # Number of seconds simulated
|
||||
sim_ticks 689104583500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 236956975 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 289938750 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 831 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 28355380 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 231810934 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 346110000 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 49326422 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 234435463 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 286093994 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 847 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 28355376 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 266706457 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 69159882 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 71745000 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1301001982 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.544185 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.202693 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1283484985 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.565260 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 594587557 45.70% 45.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 273537466 21.03% 66.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 173768132 13.36% 80.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 65535935 5.04% 85.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 48802734 3.75% 88.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 34016841 2.61% 91.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 18422173 1.42% 92.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 23171262 1.78% 94.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 69159882 5.32% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1301001982 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1283484985 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 71824891 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 39955347 # Number of function calls committed.
|
||||
|
|
@ -44,280 +44,280 @@ system.cpu.commit.COM:loads 511070026 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 721864922 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 28343547 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 686655102 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.767786 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.767786 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 463432344 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37080.555893 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34168.158766 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 461506110 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 71425827500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004156 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1926234 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 467104 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 49855785500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1459130 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.755994 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 462144938 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37091.734782 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34178.023898 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 460219169 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 71430113000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004167 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1925769 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 466816 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 49864130500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458953 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 37974.555169 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34786.244627 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210247535 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 20785790492 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 37975.971712 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34787.911566 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210247520 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 20787135492 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 547361 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 475709 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2492504000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_misses 547376 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 475729 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2492449500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 71652 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6045.454545 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 438.830385 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 71647 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5583.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 438.041746 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 66500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 67000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 14000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 674227240 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 37278.381462 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 671753645 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 92211617992 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003669 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2473595 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 942813 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 52348289500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002270 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1530782 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 672939834 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 37287.441089 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 670466689 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 92217248492 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003675 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2473145 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 942545 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 52356580000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002274 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1530600 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.102160 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 674227240 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 37278.381462 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999779 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 671753645 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 92211617992 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003669 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2473595 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 942813 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 52348289500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002270 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1530782 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 670466689 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 92217248492 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003675 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2473145 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 942545 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 52356580000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002274 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1530600 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1526686 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530782 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 1526504 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530600 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.102160 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 671753654 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 273600000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107376 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 31383327 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 11899 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 30414248 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2922892540 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 711748047 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 557786525 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 98570758 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45781 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 84083 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 772896747 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4095.093805 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107391 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 27367471 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 11874 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 29084935 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2889732822 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 703418574 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 551446436 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 94589845 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45736 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1252504 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 766409541 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 772274639 # DTB hits
|
||||
system.cpu.dtb.data_misses 622108 # DTB misses
|
||||
system.cpu.dtb.data_hits 765750752 # DTB hits
|
||||
system.cpu.dtb.data_misses 658789 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 514573141 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 514686384 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 513988912 # DTB read hits
|
||||
system.cpu.dtb.read_misses 584229 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 258323606 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 514070459 # DTB read hits
|
||||
system.cpu.dtb.read_misses 615925 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 251723157 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 258285727 # DTB write hits
|
||||
system.cpu.dtb.write_misses 37879 # DTB write misses
|
||||
system.cpu.fetch.Branches 346110000 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 346350693 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 575714813 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 4322310 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3016744002 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 28792194 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.247273 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 346350693 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 286283397 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.155268 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1399572740 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.155475 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.033799 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.write_hits 251680293 # DTB write hits
|
||||
system.cpu.dtb.write_misses 42864 # DTB write misses
|
||||
system.cpu.fetch.Branches 342127414 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 343698672 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 569144710 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 4322809 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2972544545 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 28790520 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.248241 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 343698672 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 283762997 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.156817 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1378074830 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.157027 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.030206 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 823857927 58.86% 58.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53203147 3.80% 62.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 38576379 2.76% 65.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 62027989 4.43% 69.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 120526716 8.61% 78.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 36144136 2.58% 81.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 38696119 2.76% 83.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7022744 0.50% 84.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 219517583 15.68% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 808930120 58.70% 58.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53203120 3.86% 62.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 38710034 2.81% 65.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 60833254 4.41% 69.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 120527197 8.75% 78.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 36009747 2.61% 81.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 37301448 2.71% 83.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7023896 0.51% 84.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 215536014 15.64% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1399572740 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 79145201 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 52656290 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 346350693 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15859.786377 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.165644 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 346340020 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 169271500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1378074830 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 77822211 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 52656376 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 343698672 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15692.605534 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11569.674647 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 343688083 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 166169000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 893 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 113899500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 10589 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 815 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 113082000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 9780 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 9774 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 35416.711320 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 35167.101504 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 346350693 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15859.786377 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 346340020 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 169271500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 343698672 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15692.605534 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 343688083 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 166169000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 893 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 113899500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 10589 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 815 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 113082000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 9780 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 9774 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.787644 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1613.094407 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 346350693 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15859.786377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.787641 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 346340020 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 169271500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 343688083 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 166169000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10673 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 893 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 113899500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 10589 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 815 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 113082000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 9780 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 9774 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 8107 # number of replacements
|
||||
system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8102 # number of replacements
|
||||
system.cpu.icache.sampled_refs 9773 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1613.094407 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 346340020 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1613.087790 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 343688083 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 134352 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 273830635 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 328407505 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.428327 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 772897467 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 258324248 # Number of stores executed
|
||||
system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 273848647 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 323098610 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.444031 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 766410290 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 251723816 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1628729095 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1998228085 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.696311 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1598918223 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1989129822 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.699683 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1134102180 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.427604 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1999182270 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 30874102 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3363341 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 651766159 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 47334 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 302842543 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2705917270 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 514573219 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 84025502 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1999238951 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 131775 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1118735591 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.443271 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1990119861 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3006027 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 294900052 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2668815228 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 514686474 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 77427097 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1990177336 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 131680 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2470 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 98570758 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 141708 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 50552549 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 226 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 51921347 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 3569 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 4004 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 140696133 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 92047647 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 3569 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 787992 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 30086110 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 2538504149 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1455287800 # number of integer regfile writes
|
||||
system.cpu.ipc 1.302446 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.302446 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 1647 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 4160 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 130104006 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 84105156 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes
|
||||
system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1202273174 57.71% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 18400 0.00% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850829 1.34% 59.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 554531536 26.62% 86.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283128420 13.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2083264453 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 36972943 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017748 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2067604433 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 36218004 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5487 0.01% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||
|
|
@ -346,51 +346,51 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.01% #
|
|||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 27783755 75.15% 75.16% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 9183701 24.84% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1399572740 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.488500 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636855 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1378074830 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.500357 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 529155150 37.81% 37.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 284031316 20.29% 58.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 272535453 19.47% 77.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 155737122 11.13% 88.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 63080149 4.51% 93.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 50551840 3.61% 96.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 32415692 2.32% 99.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 9151227 0.65% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2914791 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1399572740 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.488357 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 76224315 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 150190709 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 73940522 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 77634670 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2044010329 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5465284170 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1924287563 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 2854317928 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2377509698 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2083264453 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 554439445 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 12400290 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 512014253 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1378074830 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.500211 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 2793381779 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2345716556 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2067604433 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 522645709 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 346350897 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 343698869 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 346350693 # ITB hits
|
||||
system.cpu.itb.fetch_misses 204 # ITB misses
|
||||
system.cpu.itb.fetch_hits 343698672 # ITB hits
|
||||
system.cpu.itb.fetch_misses 197 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -399,106 +399,106 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 71652 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.301769 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32133.325356 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_accesses 71647 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.169863 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32132.901547 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2349178000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.933107 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 66859 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148402000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933107 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 66859 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1468910 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34259.233914 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.653566 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 55127 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 48435122500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.962471 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1413783 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43828197000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1413783 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107376 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 107376 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2348993500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.933103 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 66854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148213000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933103 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 66854 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1468727 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34262.381882 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.673392 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 54988 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 48438065500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.962561 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1413739 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43826861000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962561 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1413739 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107391 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 107391 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.041462 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.041372 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540562 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34298.838274 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 59920 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 50784300500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.961105 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1480642 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 1540374 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34301.836494 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 59781 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 50787059000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.961191 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1480593 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 45976599000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.961105 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1480642 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 45975074000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.961191 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1480593 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.881690 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.093104 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 28891.219129 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 3050.823306 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1540562 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34298.838274 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.881563 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.093197 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 59920 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 50784300500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.961105 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1480642 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 59781 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 50787059000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.961191 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1480593 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 45976599000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.961105 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1480642 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 45975074000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.961191 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1480593 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 1480407 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1513094 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1480376 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1513063 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31942.042436 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 62736 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 31940.931964 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 62599 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66898 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 118268475 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 21018090 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 651766159 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 302842543 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 45514192 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 5837090 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 641174032 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 294900052 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 1399707092 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1378209168 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 19659094 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 17364773 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 672257 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 725352464 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 10949822 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3294686946 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2827218564 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1880762420 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 542782008 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 98570758 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 13186877 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 495793350 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 113413742 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 3181273204 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 21539 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2826 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 26818332 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3921848396 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5489856325 # The number of ROB writes
|
||||
system.cpu.timesIdled 3665 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 667601 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 717318588 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3251110860 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2789102688 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1858404761 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 538784806 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 94589845 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 9995832 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 473435691 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 109436331 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 3141674529 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 20986 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2820 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 26060288 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 67 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3864626779 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5411636382 # The number of ROB writes
|
||||
system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:10:23
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 21:04:48
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -1390,4 +1389,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 888395700000 because target called exit()
|
||||
Exiting @ tick 856846060000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 93209 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 261176 # Number of bytes of host memory used
|
||||
host_seconds 20227.01 # Real time elapsed on the host
|
||||
host_tick_rate 43921255 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 120907 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 227772 # Number of bytes of host memory used
|
||||
host_seconds 15593.28 # Real time elapsed on the host
|
||||
host_tick_rate 54949698 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1885343196 # Number of instructions simulated
|
||||
sim_seconds 0.888396 # Number of seconds simulated
|
||||
sim_ticks 888395700000 # Number of ticks simulated
|
||||
sim_insts 1885343186 # Number of instructions simulated
|
||||
sim_seconds 0.856846 # Number of seconds simulated
|
||||
sim_ticks 856846060000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 320049862 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 448194519 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 4209077 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 36587037 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 430263617 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 576330823 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 59151677 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 291323462 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 52629133 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 305871415 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 427428565 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 4211226 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 36020935 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 415846626 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 551391601 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 57603360 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 291323460 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 56939437 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1586798560 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.188150 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.801160 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1535085949 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.228175 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.842995 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 733168598 46.20% 46.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 461552384 29.09% 75.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 183176106 11.54% 86.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 69760651 4.40% 91.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 39275971 2.48% 93.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 21329022 1.34% 95.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 17961260 1.13% 96.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 7945435 0.50% 96.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 52629133 3.32% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 710902830 46.31% 46.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 422912424 27.55% 73.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 179951323 11.72% 85.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 73924591 4.82% 90.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 52811288 3.44% 93.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 15756065 1.03% 94.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 17991551 1.17% 96.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 3896440 0.25% 96.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 56939437 3.71% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1586798560 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1885354212 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1535085949 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1885354202 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 1660589620 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 631390751 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 1660589612 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 631390749 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 9986 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 908389617 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 908389613 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 42140724 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1885354212 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 211801 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1156399971 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1885343196 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1885343196 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.942423 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.942423 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 16519 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 16516 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 108000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000182 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.commit.branchMispredicts 41574667 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1885354202 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 211799 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1130143872 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1885343186 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1885343186 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.908955 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.908955 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 16574 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 16571 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000181 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 722622865 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34341.472519 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34097.365081 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 720694089 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 66237008000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002669 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1928776 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 466378 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 49863918500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1462398 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 13554 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 13554 # number of StoreCondReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 710900650 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34447.466761 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34122.014006 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 708969387 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 66527118000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002717 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1931263 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 468894 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 49898975500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002057 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1462369 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 13552 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 13552 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 276935679 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35036.584459 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32455.691504 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 276128738 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 28272456500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 806941 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 734201 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2360827000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35080.855979 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32457.559426 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 276128837 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 28304708000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002913 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 806842 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 734105 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2360865500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 72740 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 72737 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 13500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 649.359320 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 641.733949 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 40500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 999558544 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34546.506272 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34019.577067 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 996822827 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 94509464500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002737 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2735717 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1200579 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 52224745500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001536 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1535138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 987836329 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34634.108626 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 985098224 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 94831826000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002772 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2738105 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1202999 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 52259841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001554 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1535106 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999736 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.919644 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 999558544 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34546.506272 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34019.577067 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.999728 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4094.887061 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 987836329 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34634.108626 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 996822827 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 94509464500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002737 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2735717 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1200579 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 52224745500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001536 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1535138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 985098224 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 94831826000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002772 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2738105 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1202999 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 52259841000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001554 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1535106 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1531037 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1535133 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 1531008 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1535104 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.919644 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 996852921 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 338455000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107062 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 151107419 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 10897 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 90820701 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 3444690201 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 769283467 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 663881028 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 162526897 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 20592 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2526644 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 4094.887061 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 985128352 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 336577000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107051 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 147664711 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 10715 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 87011249 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 3347721217 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 741403203 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 643451103 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 155800890 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 20615 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2566930 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 576330823 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 375416464 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 685697881 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 13774150 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2674548145 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 41436 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 45967312 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.324366 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 375416464 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 379201539 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.505269 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1749325455 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.017320 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.964953 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 551391601 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 362185761 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 665483414 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 16434136 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2595927696 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 41205 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 42962333 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.321757 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 362185761 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 363474775 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.514816 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1690886837 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.036253 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.984064 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1063664133 60.80% 60.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 45709797 2.61% 63.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 107764294 6.16% 69.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 64274521 3.67% 73.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 89788894 5.13% 78.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 63164111 3.61% 82.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 32677214 1.87% 83.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 54411477 3.11% 86.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 227871014 13.03% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1025439720 60.65% 60.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 44027477 2.60% 63.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 104237585 6.16% 69.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 62717330 3.71% 73.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 88060980 5.21% 78.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 56164505 3.32% 81.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 31149333 1.84% 83.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 50263393 2.97% 86.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 228826514 13.53% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1749325455 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 71543998 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 49528427 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 375416464 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9589.174687 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6216.542791 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 375392982 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 225173000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 23482 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 475 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 143024000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 23007 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 1690886837 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 71543856 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 49528271 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 362185761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9513.703009 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6161.539130 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 362162299 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 223210500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 23462 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 449 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 141795500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 23013 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16320.014868 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15738.659728 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 375416464 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9589.174687 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6216.542791 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 375392982 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 225173000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 23482 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 475 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 143024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 23007 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 362185761 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9513.703009 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 362162299 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 223210500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 23462 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 141795500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 23013 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.752121 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1540.344515 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 375416464 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9589.174687 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6216.542791 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.754539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1545.296100 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 362185761 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9513.703009 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 375392982 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 225173000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 23482 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 475 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 143024000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 23007 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 362162299 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 223210500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 23462 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 449 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 141795500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 23013 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 21420 # number of replacements
|
||||
system.cpu.icache.sampled_refs 23002 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 21424 # number of replacements
|
||||
system.cpu.icache.sampled_refs 23011 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1540.344515 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 375392982 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1545.296100 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 362162299 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 27465946 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 359805156 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 99005 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.327116 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 1136161492 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 370067841 # Number of stores executed
|
||||
system.cpu.idleCycles 22805284 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 354837598 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 98250 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.389523 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 1168779203 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 410575996 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 2411359497 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2310892149 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.529668 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 2421323747 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2344814753 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.534499 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1277221062 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.300598 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2315816685 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 45692986 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 17451585 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 932904384 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 231723 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 12876854 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 478323402 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 3041768804 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 766093651 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 62095934 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2358008462 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1124743 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1294194313 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.368282 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2351424737 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 45254697 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 17472224 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 920596247 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 229114 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5701638 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 478927516 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 3015512989 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 758203207 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 66026694 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2381213830 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1233247 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 162526897 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2446641 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 293 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 155800890 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2569235 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 31009134 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1377501 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 34849398 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1378004 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 4866291 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2578924 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 301513632 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 201324536 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 4866291 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 7718452 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 37974534 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 5503137315 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1718781055 # number of integer regfile writes
|
||||
system.cpu.ipc 1.061094 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.061094 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 289205497 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 201928652 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2578924 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 7840428 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 37414269 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 5603494067 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1718225433 # number of integer regfile writes
|
||||
system.cpu.ipc 1.100164 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.100164 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1183656160 48.91% 48.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 11225256 0.46% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8912 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 49.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501174 0.23% 49.94% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385813 0.97% 50.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 791490934 32.70% 83.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 396584385 16.39% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1176897350 48.09% 48.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 11209556 0.46% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8683 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 48.89% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501174 0.22% 49.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385811 0.96% 50.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 790636932 32.31% 82.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 431349255 17.63% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2420104396 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 57562117 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.023785 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2447240524 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 85394641 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.034894 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 17939 0.03% 0.03% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 45310366 78.72% 78.79% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 12209699 21.21% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 17844 0.02% 0.02% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 55081470 64.50% 64.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 30271214 35.45% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1749325455 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.383450 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.501844 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1690886837 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.447312 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.581356 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 679087816 38.82% 38.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 375608779 21.47% 60.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 324177593 18.53% 78.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 189762671 10.85% 89.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 109320419 6.25% 95.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 45946515 2.63% 98.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 20912326 1.20% 99.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1710477 0.10% 99.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2798859 0.16% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 652913002 38.61% 38.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 347943808 20.58% 59.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 308699944 18.26% 77.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 176613135 10.45% 87.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 115002206 6.80% 94.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 60495189 3.58% 98.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 19163759 1.13% 99.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 5856252 0.35% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 4199542 0.25% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1749325455 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.362064 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 63302900 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 122479905 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 59166670 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 79315867 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2414363613 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 6524640046 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2251725479 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 4122242728 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 3041425729 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2420104396 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 244070 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1156073456 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 23587 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 32269 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1931732931 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1690886837 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.428051 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 67428170 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 127980204 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 59166521 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 84999921 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2465206995 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 6542850406 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2285648232 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 4061650965 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 3015173249 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2447240524 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 241490 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1129860503 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 68084 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 29691 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1732452415 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -417,114 +417,108 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 72735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.554826 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.104688 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.577525 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.142520 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 6653 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2279733500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2279735000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.908531 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048615000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048617500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908531 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1485400 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34238.677361 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.325576 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 70955 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 48428726000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.952232 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1414445 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43847418500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.952214 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1414418 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 5 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 1485380 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34263.370250 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.336529 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 70915 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 48464338000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.952258 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1414465 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43848085000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.952241 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1414439 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.600000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.600000 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107062 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 107062 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_accesses 107051 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 107051 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.052436 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.052408 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1558135 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34250.276760 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.360351 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 77608 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 50708459500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.950192 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1480527 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 45896033500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.950174 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1480500 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_accesses 1558115 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34273.868374 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 77568 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 50744073000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.950217 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1480547 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 45896702500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.950200 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1480521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.884303 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.091380 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 28976.831350 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 2994.327644 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1558135 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34250.276760 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.360351 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.884259 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.091385 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 28975.398232 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 2994.491803 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 1558115 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34273.868374 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 77608 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 50708459500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.950192 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1480527 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 45896033500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.950174 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1480500 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_hits 77568 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 50744073000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.950217 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1480547 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 45896702500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.950200 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1480521 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 1479411 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1512131 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1479423 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1512143 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31971.158994 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 79290 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 31969.890035 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 79248 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 103195431 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 198192590 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 932904384 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 478323402 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 3956756575 # number of misc regfile reads
|
||||
system.cpu.memDep0.conflictingLoads 68608597 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 90712102 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 920596247 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 478927516 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 3922986795 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 14227477 # number of misc regfile writes
|
||||
system.cpu.numCycles 1776791401 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1713692121 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 26318091 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1523914797 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 14245310 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 796885476 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9677436 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 9044956904 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3344057735 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2666278058 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 638477320 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 162526897 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 33719663 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1142363258 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 419453355 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 8625503549 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 91398008 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8495416 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 83627358 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 245009 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 4575905265 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6246035428 # The number of ROB writes
|
||||
system.cpu.timesIdled 1346500 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 26481185 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1523914787 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 14530739 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 769489537 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9665417 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 8794817078 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3244153999 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2590050394 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 617757360 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 155800890 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32816862 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1066135604 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 420246695 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 8374570383 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 88541003 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8494560 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 86318102 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 244150 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 4493626241 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 6186797097 # The number of ROB writes
|
||||
system.cpu.timesIdled 1346446 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:45:41
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 26961586000 because target called exit()
|
||||
Exiting @ tick 25567234000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 86589 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 236008 # Number of bytes of host memory used
|
||||
host_seconds 919.19 # Real time elapsed on the host
|
||||
host_tick_rate 29331748 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 229170 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217968 # Number of bytes of host memory used
|
||||
host_seconds 347.30 # Real time elapsed on the host
|
||||
host_tick_rate 73616120 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.026962 # Number of seconds simulated
|
||||
sim_ticks 26961586000 # Number of ticks simulated
|
||||
sim_seconds 0.025567 # Number of seconds simulated
|
||||
sim_ticks 25567234000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 8073497 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 14157572 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 36043 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 458661 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 10575039 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 16280778 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1941652 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 3390195 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3841167 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 51426557 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.717803 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.342707 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 49654357 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.779112 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 22406480 43.57% 43.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 11177974 21.74% 65.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 5100083 9.92% 75.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 3515976 6.84% 82.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2514692 4.89% 86.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1504113 2.92% 89.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 1005597 1.96% 91.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 811447 1.58% 93.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 3390195 6.59% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 51426557 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 49654357 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 88340672 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 267754 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 1661057 # Number of function calls committed.
|
||||
|
|
@ -44,353 +44,353 @@ system.cpu.commit.COM:loads 20276638 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 34890015 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 362167 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 8347307 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.677497 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.677497 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20461848 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30161.580175 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20422.684261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20315611 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4410739000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007147 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 146237 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 84626 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1258262000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61611 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32533.052088 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32982.737586 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13581415 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 33572873499 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.070618 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1031962 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 888471 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4732725999 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009819 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143491 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 165.269329 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 35075225 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32238.707128 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33897026 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 37983612499 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.033591 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1178199 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 973097 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5990987999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 205102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995502 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4077.575152 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 35075225 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32238.707128 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.995275 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 33897026 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 37983612499 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.033591 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1178199 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 973097 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5990987999 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 205102 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 33980573 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1192412 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 201006 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205102 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 201055 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4077.575152 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33897070 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 178565000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 161507 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3275994 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 97418 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3660154 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101876983 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28458490 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19656582 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1300870 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 282338 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 35491 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 36639089 # DTB accesses
|
||||
system.cpu.dtb.data_acv 39 # DTB access violations
|
||||
system.cpu.dtb.data_hits 36464202 # DTB hits
|
||||
system.cpu.dtb.data_misses 174887 # DTB misses
|
||||
system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 161514 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 2460997 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 97681 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3594435 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 100084760 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 27762644 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19396266 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1063649 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 276834 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 34450 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 36973918 # DTB accesses
|
||||
system.cpu.dtb.data_acv 20 # DTB access violations
|
||||
system.cpu.dtb.data_hits 36772232 # DTB hits
|
||||
system.cpu.dtb.data_misses 201686 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 21567895 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 36 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21410565 # DTB read hits
|
||||
system.cpu.dtb.read_misses 157330 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15071194 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 3 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15053637 # DTB write hits
|
||||
system.cpu.dtb.write_misses 17557 # DTB write misses
|
||||
system.cpu.fetch.Branches 16280778 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13394904 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 19864093 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 154345 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103458756 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 26906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 576280 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.301925 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13394904 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 10015149 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.918633 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 52727427 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.962143 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.947691 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.read_accesses 21748478 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 19 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21577330 # DTB read hits
|
||||
system.cpu.dtb.read_misses 171148 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15225440 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15194902 # DTB write hits
|
||||
system.cpu.dtb.write_misses 30538 # DTB write misses
|
||||
system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 32863334 62.33% 62.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1866571 3.54% 65.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1546342 2.93% 68.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1858063 3.52% 72.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3933633 7.46% 79.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1853024 3.51% 83.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 690881 1.31% 84.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1144258 2.17% 86.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 6971321 13.22% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 31126722 61.37% 61.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1893724 3.73% 65.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1511025 2.98% 68.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1863843 3.67% 71.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3852588 7.60% 79.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1892655 3.73% 83.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 670633 1.32% 84.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1088115 2.15% 86.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 6818701 13.44% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 52727427 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 245061 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 242344 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 13394904 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9553.478677 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6055.148214 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13306149 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 847919000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006626 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 88755 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2832 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 520276500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006415 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85923 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 235864 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 240719 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 154.863120 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 13394904 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9553.478677 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13306149 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 847919000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006626 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 88755 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 2832 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 520276500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006415 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85923 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.937341 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1919.673560 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 13394904 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9553.478677 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.935566 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 13306149 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 847919000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006626 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 88755 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 2832 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 520276500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006415 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85923 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 13070837 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 87881 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 83875 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85922 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 83010 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1919.673560 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13306149 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1195746 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14762410 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9405310 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.574714 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36640920 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15071432 # Number of stores executed
|
||||
system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14700654 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9311504 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.660486 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36975872 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15225695 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 42200394 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84434185 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765638 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 40429267 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84366668 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.767758 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 32310240 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.565824 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84670704 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 403347 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 511454 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22901502 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 341334 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16112849 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 99067942 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21569488 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 539182 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84913582 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 10145 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 31039892 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.649898 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84634554 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 16238 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1300870 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 39828 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 947280 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 706 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1016178 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 20765 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1373 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2624864 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1499472 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 20765 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 133024 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 270323 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 112261025 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 55957664 # number of integer regfile writes
|
||||
system.cpu.ipc 1.476021 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.476021 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6217 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1472 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2214794 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1168217 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 112360564 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 55786710 # number of integer regfile writes
|
||||
system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 48294833 56.52% 56.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 42901 0.05% 56.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122014 0.14% 56.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122228 0.14% 56.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38521 0.05% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 21679241 25.37% 82.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15152888 17.73% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 85452764 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 905523 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010597 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 85477986 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1052413 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 99616 11.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 404792 44.70% 55.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 401115 44.30% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 52727427 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.620651 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.723782 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 50718006 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.685358 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 17471285 33.14% 33.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 13743409 26.07% 59.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 8117223 15.39% 74.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 4850961 9.20% 83.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4579502 8.69% 92.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2116514 4.01% 96.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1152468 2.19% 98.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 461880 0.88% 99.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 234185 0.44% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 52727427 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.584713 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 300330 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 600062 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 291336 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 449677 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 86057957 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 223986187 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 84142849 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 99078725 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 89657627 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85452764 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9846565 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 47771 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6801202 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 50718006 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.671631 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 13421810 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 13184827 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 13394904 # ITB hits
|
||||
system.cpu.itb.fetch_misses 26906 # ITB misses
|
||||
system.cpu.itb.fetch_hits 13158718 # ITB hits
|
||||
system.cpu.itb.fetch_misses 26109 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -399,106 +399,106 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.769357 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31245.328098 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 12069 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4512807000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.915891 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 131424 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4106386000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915891 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 131424 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 147532 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.347507 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.670455 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 103884 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1489896000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.295854 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43648 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1354514000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295854 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43648 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 161507 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 161507 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.759811 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 291025 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34287.053327 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 115953 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6002703000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.601570 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5460900000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.601570 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.094660 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.481148 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 3101.833838 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15766.259215 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 291025 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34287.053327 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.091039 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.482420 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 115953 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6002703000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.601570 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 175072 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 115146 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 175063 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5460900000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.601570 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 148712 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 148713 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18868.093053 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 132261 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120513 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 12487229 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 11176863 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 22901502 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 16112849 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 38001 # number of misc regfile reads
|
||||
system.cpu.l2cache.writebacks 120512 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 37825 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 53923173 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 51134470 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 1782763 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 1389160 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 52474 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28901078 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1299024 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 36 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 121755454 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 101053942 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60784194 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19225803 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1300870 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1439133 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8237313 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 444545 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 121310909 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 77780 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5276 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 3015491 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5274 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 143406999 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 194680217 # The number of ROB writes
|
||||
system.cpu.timesIdled 39379 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 11049 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28153155 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 39 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 119490611 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 99297358 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 59691366 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19024050 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1063649 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1018413 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 7144485 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 428893 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 119061718 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 69579 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5023 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2212492 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5020 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 139404893 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 190882895 # The number of ROB writes
|
||||
system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:10:13
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 20:43:38
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 42429858000 because target called exit()
|
||||
Exiting @ tick 39814499000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 115309 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 263676 # Number of bytes of host memory used
|
||||
host_seconds 872.72 # Real time elapsed on the host
|
||||
host_tick_rate 48617676 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 141424 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230092 # Number of bytes of host memory used
|
||||
host_seconds 711.57 # Real time elapsed on the host
|
||||
host_tick_rate 55953326 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 100632835 # Number of instructions simulated
|
||||
sim_seconds 0.042430 # Number of seconds simulated
|
||||
sim_ticks 42429858000 # Number of ticks simulated
|
||||
sim_insts 100632680 # Number of instructions simulated
|
||||
sim_seconds 0.039814 # Number of seconds simulated
|
||||
sim_ticks 39814499000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 9648133 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 15114739 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 120896 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 708230 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 11837178 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 18100814 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1938552 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 13645712 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 1956948 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 9474553 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 14867699 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 120437 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 705175 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 11698396 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 17816526 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1920156 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 13645681 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2731708 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 81664789 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.232335 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.714285 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 76749449 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.311257 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.867212 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 35836252 43.88% 43.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 24456690 29.95% 73.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 7408660 9.07% 82.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 5445972 6.67% 89.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 4443469 5.44% 95.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1356942 1.66% 96.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 506701 0.62% 97.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 253155 0.31% 97.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 1956948 2.40% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 33503516 43.65% 43.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 22762482 29.66% 73.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 6689783 8.72% 82.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 4895670 6.38% 88.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 3997632 5.21% 93.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1356419 1.77% 95.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 502786 0.66% 96.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 309453 0.40% 96.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 2731708 3.56% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 81664789 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 100638387 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 76749449 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 100638232 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 1679850 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 91477547 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 27308299 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 91477423 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 27308268 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 15920 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 47865227 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 47865165 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 703198 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 100638387 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 700820 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 14515398 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 100632835 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 100632835 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.843261 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.843261 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 18610 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13134.615385 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 18584 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 341500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001397 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 26 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 26 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 27269611 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22490.604159 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18794.207345 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 27168396 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2276386500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003712 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 101215 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 46784 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1022987500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54431 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 17109 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 17109 # number of StoreCondReq hits
|
||||
system.cpu.commit.branchMispredicts 701341 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 100638232 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 700789 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 12187883 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 100632680 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 100632680 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.791284 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.791284 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 18554 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 12851.851852 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 18527 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 347000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.001455 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 26941109 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22340.076347 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18819.128231 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 26838682 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2288227000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003802 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 102427 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 47963 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1024965000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54464 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 17078 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 17078 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32466.100488 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34204.996866 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 18297917 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 50386868500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.078186 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1551984 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1445097 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3656069500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32476.175857 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34166.852204 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 18297799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 50406337500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.078192 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1552102 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1445205 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3652334000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106887 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106897 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 282.067538 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 279.970622 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 17500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 47119512 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31855.363450 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29005.176112 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 45466313 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 52663255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.035085 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1653199 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1491881 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4679057000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003424 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 161318 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 46791010 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31848.679896 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 28986.551893 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 45136481 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 52694564500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.035360 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1654529 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 1493168 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4677299000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003449 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 161361 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.995259 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4076.580163 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 47119512 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31855.363450 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29005.176112 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.994972 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4075.403467 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 46791010 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31848.679896 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 28986.551893 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 45466313 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 52663255000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.035085 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1653199 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1491881 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4679057000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003424 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 161318 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 45136481 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 52694564500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.035360 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1654529 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 1493168 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4677299000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003449 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 161361 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 157220 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 161316 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 157250 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 161346 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4076.580163 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 45502007 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 331251000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 123262 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 33824964 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 92972 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3728578 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 120838990 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 25532965 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 21535228 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 2196298 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 331340 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 771631 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 4075.403467 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 45172140 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 327456000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 123257 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 29986169 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 91538 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3619762 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 118267772 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 24869566 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 21242565 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1889316 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 325053 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 651148 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 18100814 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 11605237 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 22692685 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 153016 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 89098054 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 32223 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 835942 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.213303 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 11605237 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 11586685 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.049945 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 83861086 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.470767 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.783294 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 17816526 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 11383853 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 22263353 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 149960 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 87185179 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 32417 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 799636 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.223744 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 11383853 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 11394709 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.094892 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 78638764 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.535218 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.823911 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 61184703 72.96% 72.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2309063 2.75% 75.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 2572532 3.07% 78.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2218385 2.65% 81.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1638972 1.95% 83.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1774046 2.12% 85.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 996638 1.19% 86.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1509113 1.80% 88.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9657634 11.52% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 56390222 71.71% 71.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2286086 2.91% 74.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 2538611 3.23% 77.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2175303 2.77% 80.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1609869 2.05% 82.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1746559 2.22% 84.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 986099 1.25% 86.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1498585 1.91% 88.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 9407430 11.96% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 83861086 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 348 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 308 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 11605237 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 12815.490689 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9320.206177 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 11579783 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 326205500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.002193 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 25454 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 912 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 228736500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.002115 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 24542 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 78638764 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 366 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 320 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 11383853 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 12943.379124 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9472.145833 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 11359030 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 321293500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.002181 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 24823 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 823 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 227331500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.002108 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 24000 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 471.854570 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 473.568957 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 11605237 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 12815.490689 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 9320.206177 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 11579783 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 326205500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.002193 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 25454 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 912 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 228736500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.002115 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 24542 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 11383853 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 12943.379124 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 9472.145833 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 11359030 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 321293500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.002181 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 24823 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 823 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 227331500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 24000 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.876963 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1796.020608 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 11605237 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 12815.490689 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 9320.206177 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.878234 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1798.623677 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 11383853 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 12943.379124 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 9472.145833 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 11579783 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 326205500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.002193 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 25454 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 912 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 228736500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.002115 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 24542 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 11359030 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 321293500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.002181 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 24823 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 823 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 227331500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 24000 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 22507 # number of replacements
|
||||
system.cpu.icache.sampled_refs 24541 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 21955 # number of replacements
|
||||
system.cpu.icache.sampled_refs 23986 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1796.020608 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 11579783 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1798.623677 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 11359025 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 998631 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14720525 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 89802 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.245286 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 49064418 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 20899088 # Number of stores executed
|
||||
system.cpu.idleCycles 990235 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14607903 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 89799 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.318459 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 48979606 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 20848536 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 110564194 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 105075118 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.489698 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 107968668 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 104398441 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.491185 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 54143071 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.238221 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 105316682 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 772856 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1030923 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 29917156 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 748831 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 540612 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 22494076 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 115228257 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 28165330 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 744036 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 105674596 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 10554 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 53032589 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.311061 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 104647568 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 769833 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 1011566 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 29423654 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 740403 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 542722 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 21756532 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 112900513 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 28131070 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 777005 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 104987577 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 5988 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 9453 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 2196298 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 59055 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 6373 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1889316 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 50994 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 693039 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2022 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 986302 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2227 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 44278 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 8960 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 42 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2608845 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1937136 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 44278 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 252630 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 520226 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 252581804 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 78295108 # number of integer regfile writes
|
||||
system.cpu.ipc 1.185873 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.185873 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2115374 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1199623 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 8960 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 250530 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 519303 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 251243405 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 77636795 # number of integer regfile writes
|
||||
system.cpu.ipc 1.263769 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.263769 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 56936434 53.50% 53.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 90757 0.09% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 60 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 6 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.59% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 28415464 26.70% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 20975911 19.71% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 56346023 53.27% 53.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 90776 0.09% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 60 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 4 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 53.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 28386719 26.84% 80.20% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 20941000 19.80% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 106418639 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1769080 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.016624 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 105764589 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1807941 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.017094 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 82343 4.65% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1571781 88.85% 93.50% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 114956 6.50% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 62929 3.48% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1498776 82.90% 86.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 246236 13.62% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 83861086 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.268987 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.445189 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 78638764 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.344942 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.522879 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 32249828 38.46% 38.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 23882071 28.48% 66.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 13427667 16.01% 82.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6314911 7.53% 90.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4996611 5.96% 96.43% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 1765354 2.11% 98.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 709016 0.85% 99.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 455833 0.54% 99.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 59795 0.07% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 29814112 37.91% 37.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 21100770 26.83% 64.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 12756983 16.22% 80.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6513032 8.28% 89.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4951047 6.30% 95.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 1996772 2.54% 98.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 869647 1.11% 99.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 486381 0.62% 99.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 150020 0.19% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 83861086 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.254054 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 98 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 372 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 108187593 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 298548100 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 105075020 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 129476414 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 114372601 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 106418639 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 765854 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 14297482 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 80911 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 65034 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 24667303 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 78638764 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.328217 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 244 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 107572406 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 292071724 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 104398340 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 124776670 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 112053311 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 105764589 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 757403 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 11959480 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 96092 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 56614 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 19388799 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,114 +416,115 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 106886 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34447.118852 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.705881 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 4288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3534205500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.959882 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3207388500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959882 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 78971 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34178.924225 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31045.290979 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 46678 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1103740000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.408922 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses 106884 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.892788 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31241.062378 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 4284 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3529942000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.959919 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 102600 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205333000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959919 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 102600 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 78447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34190.010219 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31051.927909 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 46154 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1104098000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.411654 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 32293 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1000776000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.408200 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32236 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1001021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410940 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 32237 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 123262 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 123262 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.642857 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 279000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.642857 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 9 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 123257 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 123257 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.512422 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.508488 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 185857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34382.912870 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31209.965587 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 50966 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4637945500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.725778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 134891 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 57 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4208164500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.725472 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 134834 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_accesses 185331 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34353.450513 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31195.843871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 50438 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4634040000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.727849 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 134893 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4206354000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.727547 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 134837 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.069881 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.489057 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2289.872639 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16025.414403 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 185857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34382.912870 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31209.965587 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.070607 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.488287 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2313.642919 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16000.187006 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 185331 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34353.450513 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31195.843871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 50966 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4637945500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.725778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 134891 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 57 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4208164500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.725472 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 134834 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_hits 50438 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4634040000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.727849 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 134893 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4206354000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.727547 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 134837 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 114591 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 133433 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 114587 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 133431 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18315.287042 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 68374 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18313.829925 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 67848 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 88457 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 22231521 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 18598246 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 29917156 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 22494076 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 145950656 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1948148 # number of misc regfile writes
|
||||
system.cpu.numCycles 84859717 # number of cpu cycles simulated
|
||||
system.cpu.l2cache.writebacks 88456 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 17365346 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 14593147 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 29423654 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 21756532 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 143746938 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1948150 # number of misc regfile writes
|
||||
system.cpu.numCycles 79628999 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 3837556 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 76545937 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 321924 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 27362593 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 4158532 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 316348591 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 118493995 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 91447203 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 20319316 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 2196298 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 5609683 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 14901230 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 85544 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 316263047 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 24535640 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 768991 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 14793505 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 769620 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 194836327 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 232505480 # The number of ROB writes
|
||||
system.cpu.timesIdled 60947 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 3301986 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 76545782 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 219694 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 26561955 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3507385 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 309490180 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 116073660 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 89787248 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 20074378 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1889316 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 4839366 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 13241430 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 84864 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 309405316 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 21971763 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 760740 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 13287175 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 761380 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 186818557 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 227542910 # The number of ROB writes
|
||||
system.cpu.timesIdled 60754 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:44:53
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -28,4 +27,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 723991197000 because target called exit()
|
||||
Exiting @ tick 701966325500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 163492 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226772 # Number of bytes of host memory used
|
||||
host_seconds 10618.50 # Real time elapsed on the host
|
||||
host_tick_rate 68182084 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 172436 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208600 # Number of bytes of host memory used
|
||||
host_seconds 10067.76 # Real time elapsed on the host
|
||||
host_tick_rate 69724149 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.723991 # Number of seconds simulated
|
||||
sim_ticks 723991197000 # Number of ticks simulated
|
||||
sim_seconds 0.701966 # Number of seconds simulated
|
||||
sim_ticks 701966325500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 297134991 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 303959521 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 19913428 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 265314839 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 344584799 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 23886075 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 63016645 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 64109829 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1347786892 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.350199 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.111631 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1311318680 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.387748 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 706265401 52.40% 52.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 261524956 19.40% 71.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 126857294 9.41% 81.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 73810788 5.48% 86.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 49267201 3.66% 90.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 31663388 2.35% 92.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 24079219 1.79% 94.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 11302000 0.84% 95.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 63016645 4.68% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1347786892 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1311318680 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 805525 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 16767440 # Number of function calls committed.
|
||||
|
|
@ -44,14 +44,14 @@ system.cpu.commit.COM:loads 444595663 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 605324165 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 19912897 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 594069052 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.834070 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.834070 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
|
||||
|
|
@ -62,342 +62,342 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu
|
|||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 521802290 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16279.064598 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10961.675998 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 511855593 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 161922923000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.019062 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 9946697 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 2670317 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 79761320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013945 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7276380 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27145.945678 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20467.767187 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155989397 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 128647486892 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.029485 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4739105 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2854288 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38577995547 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011727 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1884817 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3153.493916 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 72.899308 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 37723 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65110 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 118959251 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1980503500 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 682530792 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 19785.804677 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 667844990 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 290570409892 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.021517 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 14685802 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 5524605 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 118339315547 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.013422 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9161197 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997439 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4085.509480 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 682530792 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 19785.804677 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.997370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 667844990 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 290570409892 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.021517 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 14685802 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 5524605 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 118339315547 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.013422 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9161197 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 670151455 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 14741918 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9157102 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9161198 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9157179 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4085.509480 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 667844992 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7084078000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 3077854 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 78806586 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 620 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 54720823 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2797425384 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 722637583 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 541899569 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 88987438 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1777 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 4443154 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 767802302 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 3077964 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 69300100 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 734 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 53326576 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2753583044 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 704925020 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 533426665 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 83930076 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1732 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 3666895 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 776927298 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 752449535 # DTB hits
|
||||
system.cpu.dtb.data_misses 15352767 # DTB misses
|
||||
system.cpu.dtb.data_hits 761318004 # DTB hits
|
||||
system.cpu.dtb.data_misses 15609294 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 566812903 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 573302197 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 557652499 # DTB read hits
|
||||
system.cpu.dtb.read_misses 9160404 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 200989399 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 563960671 # DTB read hits
|
||||
system.cpu.dtb.read_misses 9341526 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 203625101 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 194797036 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6192363 # DTB write misses
|
||||
system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 556959890 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed
|
||||
system.cpu.dtb.write_hits 197357333 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6267768 # DTB write misses
|
||||
system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 321021066 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.968972 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1436774330 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.984332 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.873889 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 879814440 61.24% 61.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 48078779 3.35% 64.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 31070380 2.16% 66.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 51055446 3.55% 70.30% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 122790894 8.55% 78.84% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 67990825 4.73% 83.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 47151543 3.28% 86.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 36952114 2.57% 89.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 151869909 10.57% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 848087817 60.78% 60.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 47124000 3.38% 64.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 30216424 2.17% 66.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 49573099 3.55% 69.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 121201096 8.69% 78.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 67474425 4.84% 83.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 44590738 3.20% 86.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 37036211 2.65% 89.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 149944946 10.75% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1436774330 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 752 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 445 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 354412327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35305.051302 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 354411060 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 44731500 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 788 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 457 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1267 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 346 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32661000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 921 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 384811.140065 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 354412327 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35305.051302 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 354411060 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 44731500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1267 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32661000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 921 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.352268 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 721.445735 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 354412327 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35305.051302 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.349808 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 354411060 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 44731500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 346934350 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1267 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 346 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32661000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1256 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 921 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 921 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 721.445735 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 354411060 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 11208065 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 280169878 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 129057525 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.565430 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 767802324 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 200989407 # Number of stores executed
|
||||
system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 278210520 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 128264130 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.613458 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 776927311 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 203625107 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1523016532 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2228484684 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811571 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1505740839 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2224607717 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.814091 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1236036667 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.539027 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2249496581 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21722236 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 15314374 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 617102957 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 1225810379 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.584554 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2246216503 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 21692258 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 232568585 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2603343055 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 566812917 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 38578662 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2266715425 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 389623 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 88987438 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 694096 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 161793 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 35773426 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 210663 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 39718780 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2851639 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 17 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 172507294 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 71840083 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2851639 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3390000 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 18332236 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3052206207 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1779704780 # number of integer regfile writes
|
||||
system.cpu.ipc 1.198940 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.198940 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 198174 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 165817327 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 66687540 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes
|
||||
system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1523557218 66.09% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 93 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 225 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 139 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 15 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 577672336 25.06% 91.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 204064018 8.85% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2305294087 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 13339064 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005786 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 2302863011 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 12654324 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 3077619 23.07% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 8405753 63.02% 86.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1855692 13.91% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1436774330 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.604493 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.761639 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1395248756 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.650504 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 552319838 38.44% 38.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 267044119 18.59% 57.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 243823244 16.97% 74.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 135766343 9.45% 83.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 111649965 7.77% 91.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 72620793 5.05% 96.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 43154972 3.00% 99.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8489654 0.59% 99.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 1905402 0.13% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1436774330 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.592073 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 831640 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 1663270 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 822278 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 878238 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2317801511 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 6060328576 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2227662406 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3193875126 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2474285485 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2305294087 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1395248756 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.640295 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 718781925 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1290278 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 318719479 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 354412360 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 346935639 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 354412327 # ITB hits
|
||||
system.cpu.itb.fetch_hits 346935606 # ITB hits
|
||||
system.cpu.itb.fetch_misses 33 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -407,106 +407,106 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884819 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34457.281872 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31270.548143 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 1001564 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 30434566500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.468615 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 883255 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27619868000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468615 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 883255 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7277300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34308.231469 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.566655 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5456738 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 62460262500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.250170 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1820562 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 56684229500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250170 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1820562 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 3077854 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 3077854 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10339.327830 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.807892 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 1696 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 17535500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9162119 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34356.921715 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6458302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 92894829000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2703817 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 84304097500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2703817 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.484040 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.327555 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15861.025964 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10733.328518 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9162119 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34356.921715 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.482747 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.327799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 6458302 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 92894829000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_hits 6458351 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2703817 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 2703837 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 84304097500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2703817 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2693237 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2717881 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2693244 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 26594.354482 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7631516 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 148066834500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1171784 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 123159990 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 64312407 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 617102957 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 232568585 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1171773 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 1447982395 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1403932652 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 51393371 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 45015493 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 5887635 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 740841122 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 18541128 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 493389 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3535273918 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2734162916 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2047681663 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 528076479 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 88987438 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 27475071 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 671478700 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 885045 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 3534388873 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 54007891 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3612840225 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4916793262 # The number of ROB writes
|
||||
system.cpu.timesIdled 425188 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 2058465 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 721970868 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 493414 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3482054752 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2693944594 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2019690549 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 519735088 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 83930076 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 24596395 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 643487586 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 875387 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 3481179365 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 836 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 51588618 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 48 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3541690829 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4844528665 # The number of ROB writes
|
||||
system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:24:58
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 20:43:37
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -29,4 +28,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 683557152000 because target called exit()
|
||||
Exiting @ tick 642564184000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 125996 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 255276 # Number of bytes of host memory used
|
||||
host_seconds 13675.60 # Real time elapsed on the host
|
||||
host_tick_rate 49983689 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 146692 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 221392 # Number of bytes of host memory used
|
||||
host_seconds 11746.21 # Real time elapsed on the host
|
||||
host_tick_rate 54703941 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1723073909 # Number of instructions simulated
|
||||
sim_seconds 0.683557 # Number of seconds simulated
|
||||
sim_ticks 683557152000 # Number of ticks simulated
|
||||
sim_insts 1723073879 # Number of instructions simulated
|
||||
sim_seconds 0.642564 # Number of seconds simulated
|
||||
sim_ticks 642564184000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 234099742 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 270988691 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 420 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 18127020 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 253531298 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 308386285 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 18030825 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 213462255 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 50936466 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 223408375 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 259871172 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 422 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 18003899 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 242860493 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 296348291 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 17775010 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 213462249 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 57892406 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1236667650 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.393320 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.013912 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 1166021349 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.477738 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.107067 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 558967899 45.20% 45.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 311836050 25.22% 70.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 140294902 11.34% 81.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 77547164 6.27% 88.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 37361268 3.02% 91.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 31181150 2.52% 93.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 14635226 1.18% 94.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 13907525 1.12% 95.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 50936466 4.12% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 510165620 43.75% 43.75% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 303741868 26.05% 69.80% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 123389035 10.58% 80.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 73903803 6.34% 86.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 37047511 3.18% 89.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 32051525 2.75% 92.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 15551434 1.33% 93.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 12278147 1.05% 95.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 57892406 4.96% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1236667650 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1723073927 # Number of instructions committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 1166021349 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 1723073897 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 1536941901 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 485926783 # Number of loads committed
|
||||
system.cpu.commit.COM:int_insts 1536941877 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 485926777 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 62 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 660773841 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 660773829 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 18126668 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1723073927 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 469 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 561262265 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1723073909 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1723073909 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.793416 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.793416 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 89 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.commit.branchMispredicts 18003533 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1723073897 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 463 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 488491112 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1723073879 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1723073879 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.745835 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.745835 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38333.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 86 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 115000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.033708 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 507538299 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14918.210159 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11490.115727 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 499588577 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 118595623500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.015663 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7949722 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 299488 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 87902074000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015073 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7650234 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 74 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 74 # number of StoreCondReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 502016934 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15157.913551 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11504.970685 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 493884953 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 123263865000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016199 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 8131981 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 482230 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 88010161000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7649751 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 68 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 68 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23458.776949 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20845.524839 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 168361233 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 99108969278 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.024479 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4224814 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2332947 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 39436960540 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23727.454668 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20867.425320 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 168020006 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 108340530838 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.026457 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4566041 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 2674070 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 39480563550 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010962 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1891867 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3129.028905 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 19277.777778 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 70.000304 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 25082 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1891971 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3133.925265 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 19555.555556 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 69.369565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 25102 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 78482303 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 173500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 78667792 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 176000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 680124346 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 17881.962218 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 13344.968214 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 667949810 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 217704592778 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.017900 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 12174536 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2632435 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 127339034540 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014030 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9542101 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 674602981 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18239.407353 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 661904959 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 231604395838 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.018823 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 12698022 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 3156300 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 127490724550 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014144 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9541722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.997946 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4087.586245 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 680124346 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 17881.962218 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 13344.968214 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.997821 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 4087.076226 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 674602981 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18239.407353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 667949810 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 217704592778 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.017900 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 12174536 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2632435 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 127339034540 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014030 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9542101 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 661904959 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 231604395838 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.018823 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 12698022 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 3156300 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 127490724550 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014144 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9541722 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9538005 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9542101 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9537626 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9541722 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4087.586245 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 667949970 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 5054603000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 3121989 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 147560850 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 47355692 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2426461717 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 611352233 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 463432927 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 80642265 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 2276 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 14321639 # Number of cycles decode is unblocking
|
||||
system.cpu.dcache.tagsinuse 4087.076226 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 661905101 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 5039888000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 3122150 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 126134544 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 631 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 46158003 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2344918841 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 578373170 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 449937268 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 70475039 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 2244 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 11576366 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 308386285 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 291049356 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 486495532 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 5722216 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2234143439 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 20492527 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.225575 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 291049356 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 252130567 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.634204 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1317309914 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.875583 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.855181 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 296348291 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 276432138 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 470132828 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 5100693 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2155880694 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 18543154 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230598 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 276432138 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 241183385 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.677561 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1236496387 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.931778 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.884875 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 830814434 63.07% 63.07% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 33726973 2.56% 65.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 60219137 4.57% 70.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 62511674 4.75% 74.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 52124887 3.96% 78.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 58187439 4.42% 83.32% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 53878376 4.09% 87.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 20459280 1.55% 88.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 145387714 11.04% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 766363617 61.98% 61.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 33302617 2.69% 64.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 59273636 4.79% 69.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 61386146 4.96% 74.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 46873479 3.79% 78.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 54969771 4.45% 82.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 53004501 4.29% 86.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 18322602 1.48% 88.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 143000018 11.56% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1317309914 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 43 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 35 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 291049356 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34505.208333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34374.125874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 291048396 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 33125000 # number of ReadReq miss cycles
|
||||
system.cpu.fetch.rateDist::total 1236496387 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 41 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 33 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 276432138 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34722.162741 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34464.838256 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 276431204 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32430500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 960 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 245 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 24577500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 715 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 223 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 24504500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 711 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 407060.693706 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 388792.129395 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 291049356 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34505.208333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34374.125874 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 291048396 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 33125000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 276432138 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34722.162741 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 276431204 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32430500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 960 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 245 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 24577500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 715 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_misses 934 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 223 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 24504500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 711 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.282759 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 579.089793 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 291049356 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34505.208333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34374.125874 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.280397 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 574.252402 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 276432138 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34722.162741 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 291048396 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 33125000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 276431204 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32430500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 960 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 245 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 24577500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 715 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_misses 934 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 223 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 24504500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 711 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 8 # number of replacements
|
||||
system.cpu.icache.sampled_refs 715 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 711 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 579.089793 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 291048396 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 574.252402 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 276431204 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 49804391 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 234697761 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 547 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.436470 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 750034372 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 187740498 # Number of stores executed
|
||||
system.cpu.idleCycles 48631982 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 233424980 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 482 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.517936 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 747978494 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 187773804 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 2269897341 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1942898831 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.550573 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 2256428952 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1928922171 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.551030 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1249744182 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.421168 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1949681228 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 19483021 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 24433414 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 645564584 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 589 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5964223 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 233715447 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2284224586 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 562293874 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 22044144 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1963818585 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 950332 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1243359181 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.500957 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1935148462 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 19351048 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 24037939 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 626206356 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 572 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 5915627 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 225279083 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2211459502 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 560204690 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 21122432 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1950742523 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1443603 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 75248 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 80642265 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2065851 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 76182 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 70475039 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2501364 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 185250 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 50987012 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 396924 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 185277 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 54176834 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 572517 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 2672523 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 159637800 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 58868389 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 2672523 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3281489 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 16201532 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 5066759971 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1546862528 # number of integer regfile writes
|
||||
system.cpu.ipc 1.260373 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.260373 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 735122 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 140279578 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 50432031 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 735122 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 3222127 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 16128921 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 5041119538 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1533310252 # number of integer regfile writes
|
||||
system.cpu.ipc 1.340780 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.340780 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1224165403 61.64% 61.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1261545 0.06% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 6 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 570988512 28.75% 90.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 189447253 9.54% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212671548 61.50% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1140441 0.06% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 7 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 568624535 28.84% 90.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 189428413 9.61% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1985862729 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 19986735 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010065 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1971864955 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 20980180 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010640 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 275137 1.38% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 19210300 96.12% 97.49% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 501298 2.51% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 466922 2.23% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 19229106 91.65% 93.88% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1284151 6.12% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1317309914 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.507514 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.580852 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1236496387 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.594720 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635591 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 464070867 35.23% 35.23% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 308173295 23.39% 58.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 229356697 17.41% 76.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 153235086 11.63% 87.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 89874952 6.82% 94.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 46390462 3.52% 98.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 16857883 1.28% 99.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8134010 0.62% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 1216662 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 417933228 33.80% 33.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 278405850 22.52% 56.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 219666046 17.77% 74.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 150452877 12.17% 86.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 89712597 7.26% 93.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 51644953 4.18% 97.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 17725773 1.43% 99.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 8301913 0.67% 99.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 2653150 0.21% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1317309914 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.452595 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 148 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 2005849387 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5310203358 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1942898780 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 2844721675 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2284223375 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1985862729 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 664 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 557961709 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1181399 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1018791198 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1236496387 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.534372 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 65 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 124 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 53 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 108 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 1992845070 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 5201866882 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1928922118 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 2697398990 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 2211458379 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1971864955 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 641 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 485334084 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 660529 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 844272367 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,107 +416,107 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1891872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.042777 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.781802 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_accesses 1891974 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34486.894931 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.697108 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 979846 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 31429367000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 912026 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28570839500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 912026 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7650944 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34297.265152 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31122.429712 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5630539 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 69294366000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.264073 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2020405 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 62879632500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264071 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2020396 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 3121989 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 3121989 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3894.751535 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 31456462500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.482104 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 912128 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28587639500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482104 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 912128 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7650459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.020010 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.460219 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5630454 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 69318532000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.264037 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2020005 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 62879334000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264036 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2019995 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 3122150 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 3122150 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3879.110251 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.653371 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 3582 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.653657 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 3619 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 13951000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 14038500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9542816 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34348.202225 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.986192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6610385 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 100723733000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.307292 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2932431 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 91450472000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.307291 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2932422 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_accesses 9542433 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34369.175784 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6610300 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 100774994500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.307273 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2932133 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 91466973500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.307272 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2932123 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.491178 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.327642 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 16094.912992 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10736.176193 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9542816 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34348.202225 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.986192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.488260 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.329752 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 15999.295959 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 10805.300698 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 9542433 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34369.175784 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 6610385 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 100723733000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.307292 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2932431 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 91450472000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.307291 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2932422 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_hits 6610300 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 100774994500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.307273 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2932133 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 91466973500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.307272 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2932123 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2920032 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2947354 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2919711 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2947033 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 26831.089185 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7820423 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 144225858000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1216371 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 145182889 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 105876264 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 645564584 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 233715447 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 2966427922 # number of misc regfile reads
|
||||
system.cpu.l2cache.tagsinuse 26804.596658 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7820415 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 143356933000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1216362 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 94435755 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 90423649 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 626206356 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 225279083 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 2884410167 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 896 # number of misc regfile writes
|
||||
system.cpu.numCycles 1367114305 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1285128369 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 68709037 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1360917764 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 18606012 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 637141872 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 55034011 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 10097 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 6548789867 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2371291968 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1861474045 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 450935240 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 80642265 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 79866570 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 500556278 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 429 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 6548789438 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 14930 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 647 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 148781529 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 642 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3470066777 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4649325132 # The number of ROB writes
|
||||
system.cpu.timesIdled 1578606 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 66687922 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1360917734 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 14597587 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 600232966 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 40535929 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 10237 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 6332213633 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2292978845 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1803334951 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 438824808 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 70475039 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 60261068 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 442417214 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 432 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 6332213201 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 14584 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 629 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 117068052 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 624 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 3319693353 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4493611781 # The number of ROB writes
|
||||
system.cpu.timesIdled 1545196 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,13 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:48
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:44:40
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -28,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 40631511500 because target called exit()
|
||||
122 123 124 Exiting @ tick 34191076000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 68515 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230924 # Number of bytes of host memory used
|
||||
host_seconds 1228.63 # Real time elapsed on the host
|
||||
host_tick_rate 33070698 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 141441 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212592 # Number of bytes of host memory used
|
||||
host_seconds 595.16 # Real time elapsed on the host
|
||||
host_tick_rate 57448767 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040632 # Number of seconds simulated
|
||||
sim_ticks 40631511500 # Number of ticks simulated
|
||||
sim_seconds 0.034191 # Number of seconds simulated
|
||||
sim_ticks 34191076000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 11932962 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 15864027 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1214 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 1885603 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 14586720 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 19564106 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1732867 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2884434 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3636559 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 73022923 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.258551 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.953672 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 62672395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.466404 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 35697739 48.89% 48.89% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 18400471 25.20% 74.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 7461073 10.22% 84.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 3811930 5.22% 89.52% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 1995705 2.73% 92.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1288642 1.76% 94.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 737357 1.01% 95.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 745572 1.02% 96.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 2884434 3.95% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 62672395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 91903055 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 6862061 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 1029620 # Number of function calls committed.
|
||||
|
|
@ -44,72 +44,72 @@ system.cpu.commit.COM:loads 19996198 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 26497301 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 1872416 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 56371965 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.965352 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.965352 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 23336477 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30318.337130 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32167.647059 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23335599 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 26619500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 878 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 368 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16405500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35388.341031 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35272.360069 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493092 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 283496000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001232 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 8011 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6278 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 61127000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 13298.573785 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 29837580 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34887.557656 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29828691 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 310115500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 8889 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6646 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 77532500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.356524 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1460.322095 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 29837580 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34887.557656 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.356334 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 29828691 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 310115500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits 30012251 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 8889 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6646 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 77532500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_misses 8940 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -117,280 +117,280 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.dcache.replacements 160 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1460.322095 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29828701 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 109 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3982765 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3143444 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 162519421 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 39357415 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 29479520 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8131535 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 48925 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 203223 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 31749224 # DTB accesses
|
||||
system.cpu.decode.DECODE:BlockedCycles 838288 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 13474 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 2813146 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 143267385 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 35496040 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 26313036 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 5601227 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 49112 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 25031 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 32239873 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 31371389 # DTB hits
|
||||
system.cpu.dtb.data_misses 377835 # DTB misses
|
||||
system.cpu.dtb.data_hits 31883201 # DTB hits
|
||||
system.cpu.dtb.data_misses 356672 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 24565202 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 24961741 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 24188408 # DTB read hits
|
||||
system.cpu.dtb.read_misses 376794 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7184022 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 24606273 # DTB read hits
|
||||
system.cpu.dtb.read_misses 355468 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7278132 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 7182981 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1041 # DTB write misses
|
||||
system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 30564219 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 13665829 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.062844 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 81154458 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.065603 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.090223 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dtb.write_hits 7276928 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1204 # DTB write misses
|
||||
system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 50590239 62.34% 62.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3137902 3.87% 66.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1890959 2.33% 68.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3231189 3.98% 72.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 4367674 5.38% 77.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1502603 1.85% 79.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1888200 2.33% 82.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1658917 2.04% 84.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 12886775 15.88% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 6156758 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 6040765 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19048295 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 175829000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 11152 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1015 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120621000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1879.086022 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 19059447 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15766.588953 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19048295 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 175829000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 11152 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1015 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120621000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.756347 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1548.997868 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 19059447 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15766.588953 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.755537 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 19048295 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 175829000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 11152 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1015 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120621000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 17386201 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 11068 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 8219 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8218 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1548.997868 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19048295 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 108566 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12934750 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12801851 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.253335 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31749416 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7184063 # Number of stores executed
|
||||
system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12448390 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 11194543 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.455255 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 32240280 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7278167 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 91396336 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 100051870 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.721943 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 87558338 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 97422402 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.737743 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 65982976 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.231210 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100889956 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2057434 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 253528 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 33850050 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 64595544 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.424676 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 98290476 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1485832 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10655807 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 148273965 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24565353 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2165750 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 101849758 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 124164 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 47 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8131535 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 157443 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 842082 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2486 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 1076434 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 268955 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9838 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 13853852 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4154704 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 137465323 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 75768353 # number of integer regfile writes
|
||||
system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 361752 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9740 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 8840023 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 2710213 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 134796814 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 73485618 # number of integer regfile writes
|
||||
system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64603279 62.11% 62.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 474408 0.46% 62.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2788350 2.68% 65.25% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114559 0.11% 65.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2389553 2.30% 67.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305056 0.29% 67.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755116 0.73% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 25265594 24.29% 92.96% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7319262 7.04% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 104015508 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1951419 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018761 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 101956461 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1618550 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 264504 13.55% 13.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 67 0.00% 13.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 1979 0.10% 13.66% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 2355 0.12% 13.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 826053 42.33% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 733480 37.59% 93.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 122981 6.30% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 81154458 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.281698 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540203 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 68273622 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.493351 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 34964609 43.08% 43.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 18826048 23.20% 66.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 11595868 14.29% 80.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6807186 8.39% 88.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 5054639 6.23% 95.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2409288 2.97% 98.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1203500 1.48% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 256390 0.32% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 36930 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 8012478 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 15186691 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 7058808 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 12278263 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 97954442 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 276254930 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 92993062 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 174004519 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 68273622 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.490981 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 50629869 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 304728 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 47460542 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 19059519 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 17397343 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 19059447 # ITB hits
|
||||
system.cpu.itb.fetch_misses 72 # ITB misses
|
||||
system.cpu.itb.fetch_hits 17397269 # ITB hits
|
||||
system.cpu.itb.fetch_misses 74 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -399,105 +399,105 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34492.672919 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31439.624853 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 58844500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.984420 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53636000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984420 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10647 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34284.558824 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.500000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7247 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 116567500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.319339 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3400 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 105680500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319339 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3400 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.091984 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 12380 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34354.093224 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7274 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 175412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.412439 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5106 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 159316500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.412439 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5106 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.070256 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.000538 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2302.164021 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 17.613547 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 12380 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34354.093224 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.070076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.000540 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 7274 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 175412000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.412439 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5106 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 7279 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5098 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 159316500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.412439 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5106 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3468 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2319.777568 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7255 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 17824866 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 712336 # number of misc regfile reads
|
||||
system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 712206 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 81263024 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 68382153 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 332303 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 40588679 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 939622 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 202646679 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 157276395 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 115514667 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28432140 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 11932541 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 190714138 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 218412469 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 304705559 # The number of ROB writes
|
||||
system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 66062 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 36404617 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 178909439 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 138778599 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 101591818 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 25415273 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 5601227 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 515125 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 33164457 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 9732280 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 169177159 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 5077 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1208043 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 457 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 186605606 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 260771760 # The number of ROB writes
|
||||
system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:28:39
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 20:55:41
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -26,4 +25,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 129013619500 because target called exit()
|
||||
122 123 124 Exiting @ tick 124689161500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,142 +1,142 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 73857 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 259036 # Number of bytes of host memory used
|
||||
host_seconds 2527.09 # Real time elapsed on the host
|
||||
host_tick_rate 51052260 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 93351 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225124 # Number of bytes of host memory used
|
||||
host_seconds 2021.07 # Real time elapsed on the host
|
||||
host_tick_rate 61694693 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 186644197 # Number of instructions simulated
|
||||
sim_seconds 0.129014 # Number of seconds simulated
|
||||
sim_ticks 129013619500 # Number of ticks simulated
|
||||
sim_insts 188669147 # Number of instructions simulated
|
||||
sim_seconds 0.124689 # Number of seconds simulated
|
||||
sim_ticks 124689161500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 82595843 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 87704416 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 35994 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 9565909 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 85970608 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 110694771 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 4976778 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 39816389 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 1145946 # number cycles where commit BW limit reached
|
||||
system.cpu.BPredUnit.BTBHits 82388478 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 87434288 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 36044 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 9641646 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 85843084 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 110166863 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 4949514 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 40244076 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 1787959 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 230008327 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.811530 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.187276 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 222534164 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.847886 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.274260 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 121269072 52.72% 52.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 61996527 26.95% 79.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 32262930 14.03% 93.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 7261751 3.16% 96.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 3043345 1.32% 98.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1671954 0.73% 98.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 847387 0.37% 99.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 509415 0.22% 99.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 1145946 0.50% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 117100961 52.62% 52.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 58370166 26.23% 78.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 31670521 14.23% 93.08% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 7201653 3.24% 96.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 3053342 1.37% 97.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 1898242 0.85% 98.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 800122 0.36% 98.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 651198 0.29% 99.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 1787959 0.80% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 230008327 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 186658585 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 1835949 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 148665286 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 29539429 # Number of loads committed
|
||||
system.cpu.commit.COM:committed_per_cycle::total 222534164 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 188683535 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 1752310 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 1848934 # Number of function calls committed.
|
||||
system.cpu.commit.COM:int_insts 150271162 # Number of committed integer instructions.
|
||||
system.cpu.commit.COM:loads 29852012 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 22408 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 42068801 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 42499173 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 9469517 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 186658585 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 1617312 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 187111758 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 186644197 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 186644197 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.382455 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.382455 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 26640 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.commit.branchMispredicts 9542849 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 188683535 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 1635922 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 177752777 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 188669147 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 188669147 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.321776 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.321776 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 26639 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 26638 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 26637 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.000075 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 36653125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33700.747283 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32158.536585 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 36651653 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 49607500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 38457824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33236.876215 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32051.677852 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 38456281 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 51284500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000040 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1472 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 734 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 23733000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 738 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 24951 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 24951 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 12251566 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 31103.241534 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35107.404022 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 12243977 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 236042500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000619 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 7589 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6495 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38407500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1094 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_misses 1543 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 798 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 23878500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 24934 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 24934 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 12364290 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 31170.308568 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35114.010989 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 12356739 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 235367000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 7551 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6459 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 38344500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 26717.914301 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27688.944475 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 48904691 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31525.217967 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33919.486900 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 48895630 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 285650000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000185 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9061 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 7229 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 62140500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1832 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 50822114 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31520.947878 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 50813020 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 286651500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000179 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9094 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 7257 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 62223000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1837 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.340757 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1395.741753 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 48904691 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31525.217967 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33919.486900 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.341673 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1399.491436 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 50822114 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31520.947878 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 33872.074034 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 48895630 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 285650000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000185 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9061 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 7229 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 62140500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1832 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 50813020 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 286651500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000179 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9094 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 7257 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 62223000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1837 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 44 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1832 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 46 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1837 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1395.741753 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 48947219 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1399.491436 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 50864591 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 16 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 41216121 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 162173 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 17947429 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 450164827 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 82659496 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 104979793 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 27951688 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 694943 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1152916 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.DECODE:BlockedCycles 36483964 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 165697 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 17673947 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 443458046 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 81104837 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 104098479 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 26775543 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 708476 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 846883 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -158,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 110694771 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 38575932 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 111755859 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1956934 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 439020162 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 55086 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 9825072 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.429004 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 38575932 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 87572621 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.701449 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 257960014 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.834639 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.572532 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 110166863 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 38007450 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 110625948 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 2015006 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 433901698 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 54587 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 9922678 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.441766 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 38007450 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 87337992 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.739933 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 249309706 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.873850 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.579021 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 146405140 56.75% 56.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4345583 1.68% 58.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 33012115 12.80% 71.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 15727198 6.10% 77.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 9968006 3.86% 81.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 16602538 6.44% 87.63% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 8446634 3.27% 90.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 5474811 2.12% 93.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 17977989 6.97% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 138852417 55.69% 55.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4190440 1.68% 57.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 32866604 13.18% 70.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 15794774 6.34% 76.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 9866514 3.96% 80.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 16440428 6.59% 87.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 8394995 3.37% 90.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 5405379 2.17% 92.98% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 17498155 7.02% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 257960014 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 2918455 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2533041 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 38575932 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 23829.127878 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20456.359460 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 38571850 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 97270500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000106 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4082 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 71249500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3483 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 249309706 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 2867836 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2467423 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 38007450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 23681.144866 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20351.582549 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 38003467 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 94322000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000105 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3983 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 476 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 71373000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3507 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 11074.318117 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10836.460508 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 38575932 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 23829.127878 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 20456.359460 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 38571850 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 97270500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000106 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4082 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 71249500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3483 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 38007450 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 23681.144866 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 38003467 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 94322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000105 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3983 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 476 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 71373000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3507 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.621830 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1273.508184 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 38575932 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 23829.127878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 20456.359460 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.620951 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1271.708604 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 38007450 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 23681.144866 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 20351.582549 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 38571850 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 97270500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000106 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4082 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 71249500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3483 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 38003467 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 94322000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000105 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3983 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 476 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 71373000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3507 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1827 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3483 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1849 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3507 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1273.508184 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 38571850 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1271.708604 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 38003467 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 67226 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 52962106 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 84051 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.929014 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 51175949 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 13319638 # Number of stores executed
|
||||
system.cpu.idleCycles 68618 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 53002298 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 82764 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.971537 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 53752491 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 13612548 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 285530591 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 236209276 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.493714 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 284939700 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 238367932 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.498660 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 140970333 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.915443 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 237475950 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 10889279 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 87073 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 51734063 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2217181 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4617225 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 19417784 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 373778120 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 37856311 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 7515922 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 239710842 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 16182 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 142088077 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.955849 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 239814409 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 10973411 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 19948 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 49638370 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2232445 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4819384 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 18009283 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 366444127 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 40139943 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 7486863 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 242280268 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 4512 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 11289 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 27951688 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 27726 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 2549 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 26775543 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 7301 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 619448 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1421 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 948005 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 19233 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 246556 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 22194633 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 6888412 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 246556 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2322193 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 8567086 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 532811061 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 228488130 # number of integer regfile writes
|
||||
system.cpu.ipc 0.723351 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.723351 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 222493 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 19786357 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 5362122 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 222493 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2339474 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 8633937 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 541531980 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 230759535 # number of integer regfile writes
|
||||
system.cpu.ipc 0.756558 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.756558 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 192005801 77.66% 77.66% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 909911 0.37% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7519 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 78.03% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 33371 0.01% 78.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 78.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 158227 0.06% 78.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 303942 0.12% 78.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 75061 0.03% 78.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 513450 0.21% 78.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 198615 0.08% 78.55% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 72348 0.03% 78.58% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 326 0.00% 78.58% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 39354306 15.92% 94.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 13593887 5.50% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 191948188 76.85% 76.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 913529 0.37% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 7217 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 32763 0.01% 77.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 160980 0.06% 77.30% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 256110 0.10% 77.40% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 76473 0.03% 77.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 455650 0.18% 77.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 202844 0.08% 77.69% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71631 0.03% 77.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 326 0.00% 77.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 41826421 16.75% 94.47% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 13815002 5.53% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 247226764 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1255415 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005078 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 249767134 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1600059 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006406 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 17638 1.40% 1.40% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 5653 0.45% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1032005 82.20% 84.06% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 200119 15.94% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 17737 1.11% 1.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 5657 0.35% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.46% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 1269103 79.32% 80.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 307562 19.22% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 257960014 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.958392 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.149844 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 249309706 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.001835 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200885 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 118566541 45.96% 45.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 70125037 27.18% 73.15% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 44762596 17.35% 90.50% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 14438137 5.60% 96.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 6886623 2.67% 98.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2484508 0.96% 99.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 597059 0.23% 99.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 85366 0.03% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 14147 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 113103229 45.37% 45.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 65846302 26.41% 71.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 43653759 17.51% 89.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 15345322 6.16% 95.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 7500866 3.01% 98.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 2857086 1.15% 99.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 799949 0.32% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 136784 0.05% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 66409 0.03% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 257960014 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.958142 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 1985429 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3952184 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1885790 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 3082571 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 246496750 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 750098950 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234323486 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 555603223 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 371452773 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 247226764 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 2241296 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 184786827 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 382177 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 623984 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 306361873 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 249309706 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.001559 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 1880181 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 3740694 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 1822482 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 2256352 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 249487012 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 746951727 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 236545450 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 539735109 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 364104789 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 249767134 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 2256574 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 175408140 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 248391 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 620652 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 277084807 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,106 +416,106 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1094 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34292.357274 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31035.911602 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_accesses 1092 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34297.509225 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.822878 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 37241500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.992687 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1086 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33705000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992687 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1086 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34284.967067 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31071.317225 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1640 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 88489500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.611466 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2581 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 37178500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.992674 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1084 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33645000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992674 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1084 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4252 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34293.776575 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31074.261275 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1665 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 88718000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.608420 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 2587 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 79729000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607913 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2566 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 79923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.604892 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 2572 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.637141 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.645349 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 5315 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34287.155713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31060.788609 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1648 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 125731000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.689934 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3667 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 5344 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34294.878780 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1673 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 125896500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.686939 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3671 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 113434000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.687112 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3652 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 113568000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.684132 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3656 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.056054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::0 0.056059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1836.784505 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 3.029906 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 5315 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34287.155713 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31060.788609 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_blocks::0 1836.948830 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 3.029636 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 5344 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34294.878780 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.457330 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1648 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 125731000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.689934 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3667 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1673 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 125896500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.686939 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3671 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 113434000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.687112 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3652 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 113568000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.684132 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3656 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2574 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2580 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 1839.814411 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1640 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 1839.978467 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1665 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 20836418 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 10554028 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 51734063 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 19417784 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 525439504 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 4891826 # number of misc regfile writes
|
||||
system.cpu.numCycles 258027240 # number of cpu cycles simulated
|
||||
system.cpu.memDep0.conflictingLoads 5431209 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4203967 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 49638370 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 18009283 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 520185841 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 4959640 # number of misc regfile writes
|
||||
system.cpu.numCycles 249378324 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 2330030 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 180535361 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 944198 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 91504327 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3682942 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 971479303 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 419602585 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 423243474 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 97150161 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 27951688 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 7290618 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 242708110 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 16446952 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 955032351 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 31733190 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2646445 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 27810547 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2436395 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 602627523 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 775494029 # The number of ROB writes
|
||||
system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:BlockCycles 894474 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 182569794 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 613304 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 89635884 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2121775 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 950994709 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 412692464 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 417292399 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96328320 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 26775543 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 5285061 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 234722601 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 13811231 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 937183478 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 30390424 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 2644938 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 23801477 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 2441234 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 587177316 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 759649734 # The number of ROB writes
|
||||
system.cpu.timesIdled 1415 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -488,7 +491,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
|
||||
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -5,11 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 12 2011 02:22:23
|
||||
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
|
||||
M5 started Feb 12 2011 02:22:27
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
|
||||
M5 compiled Mar 18 2011 20:12:06
|
||||
M5 started Mar 18 2011 20:12:16
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -27,4 +26,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 108875474000 because target called exit()
|
||||
122 123 124 Exiting @ tick 106785381000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 92938 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 245208 # Number of bytes of host memory used
|
||||
host_seconds 2381.84 # Real time elapsed on the host
|
||||
host_tick_rate 45710653 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 118324 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224536 # Number of bytes of host memory used
|
||||
host_seconds 1870.83 # Real time elapsed on the host
|
||||
host_tick_rate 57079180 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 221363017 # Number of instructions simulated
|
||||
sim_seconds 0.108875 # Number of seconds simulated
|
||||
sim_ticks 108875474000 # Number of ticks simulated
|
||||
sim_seconds 0.106785 # Number of seconds simulated
|
||||
sim_ticks 106785381000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 19602584 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 22433110 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 3071588 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 12326943 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 2318001 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 190318905 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 1.163116 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 190318905 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 221363017 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -44,424 +44,430 @@ system.cpu.commit.COM:loads 56649590 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 77165306 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.964799 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 50490336 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33183.118741 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34227.979275 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 50489637 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 23195000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 699 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 313 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13212000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 386 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26460.898971 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.187380 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 187793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 5528 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 55659000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 36353.441884 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 71006066 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27063.622370 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 70998270 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 210988000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 7796 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 5841 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 68871000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1955 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.341442 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 71003033 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000109 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 7734 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 68562500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 70998270 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 210988000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 7796 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 5841 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 68871000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1955 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 48 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1953 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1398.546932 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 10 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.decode.DECODE:BlockedCycles 57112679 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 420105654 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 67048451 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 60385094 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 23161998 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 5772681 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 448608 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 261554963 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 3099299 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.117410 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 27531173 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 19602584 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.224676 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 213480903 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.014170 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.226415 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 145760613 68.28% 68.28% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3769966 1.77% 70.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 3155448 1.48% 71.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 4279066 2.00% 73.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 4652490 2.18% 75.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 4411215 2.07% 77.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 5002306 2.34% 80.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 3209548 1.50% 81.62% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 39240251 18.38% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 213480903 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 3511578 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2187329 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 27531173 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25557.221784 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22462.481426 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 27524838 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 161905000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 6335 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 951 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120938000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 5384 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5114.239688 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 27531173 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25557.221784 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 27524838 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 161905000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 6335 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 951 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120938000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 5384 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 27858568 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.784044 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 27852177 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 163077000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000229 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 6391 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1005 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 27524838 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 161905000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 6335 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 951 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120938000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 5384 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 3428 # number of replacements
|
||||
system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 3426 # number of replacements
|
||||
system.cpu.icache.sampled_refs 5382 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1605.721886 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 27524838 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 15799905 # Number of branches executed
|
||||
system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 15858881 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 22888685 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 1.303230 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 90240962 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 23196856 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 371845968 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 275965139 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.599241 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 223241922 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 222825226 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.292148 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 277010234 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 231101 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 37116725 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 395719031 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 67044106 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3514925 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 278331746 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 453294 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 16343714 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 514946932 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 284476955 # number of integer regfile writes
|
||||
system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1195391 0.42% 0.42% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 187555358 66.63% 67.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.05% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589850 0.56% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 67998663 24.16% 91.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 23168272 8.23% 100.00% # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 35659 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 45746 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 48346210 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 16601009 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 516469209 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 283974364 # number of integer regfile writes
|
||||
system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 281846671 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 2813875 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2334735 84.00% 86.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 386272 13.90% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 217661766 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 213480903 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.320243 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 37681009 17.31% 82.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2526643 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 213480903 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.319688 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 564126820 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 395717604 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 281846671 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1427 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 174039946 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 53929500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.996171 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1561 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48940000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996171 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1561 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 5768 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34292.872747 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.872747 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2106 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 125580500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.634882 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 113679000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634882 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.574468 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34369.136512 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2112 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 179510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.712065 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5223 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 162619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.712065 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::0 0.074157 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2116 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5220 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 2112 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 179510000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.712065 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5223 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 162619000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.712065 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5223 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2431.000786 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2106 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads
|
||||
system.cpu.memDep0.conflictingLoads 90499072 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 30541649 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 104995800 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 37116725 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 145140832 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
||||
system.cpu.numCycles 217750949 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 213570763 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 18060003 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 592991425 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 827053987 # The number of ROB writes
|
||||
system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 21564374 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 74887260 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 1054491347 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 409882715 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 430914543 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 57380379 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 23161998 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 39968831 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 196551134 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 11087102 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 1043404245 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 22432 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 1444 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 83221554 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 1312 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 583734688 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 814640460 # The number of ROB writes
|
||||
system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:44:43
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 12412500 because target called exit()
|
||||
Exiting @ tick 12357500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 34686 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223912 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 67319594 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 83889 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205772 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 161742329 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 12412500 # Number of ticks simulated
|
||||
sim_ticks 12357500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2222 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2180 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 1051 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 127 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12090 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.529611 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12090 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 6403 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 127 # Number of function calls committed.
|
||||
|
|
@ -47,348 +47,348 @@ system.cpu.commit.COM:swp_count 0 # Nu
|
|||
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.026841 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2119 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 511 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 2064 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 506 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BlockedCycles 1035 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:BranchResolved 181 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12021 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8780 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2228 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 825 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 2921 # DTB accesses
|
||||
system.cpu.decode.DECODE:UnblockCycles 47 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 2822 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2860 # DTB hits
|
||||
system.cpu.dtb.data_hits 2761 # DTB hits
|
||||
system.cpu.dtb.data_misses 61 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 1845 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 1786 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1809 # DTB read hits
|
||||
system.cpu.dtb.read_hits 1750 # DTB read hits
|
||||
system.cpu.dtb.read_misses 36 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 1076 # DTB write accesses
|
||||
system.cpu.dtb.write_accesses 1036 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 1051 # DTB write hits
|
||||
system.cpu.dtb.write_hits 1011 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25 # DTB write misses
|
||||
system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency
|
||||
system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 410 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency
|
||||
system.cpu.icache.occ_%::0 0.076986 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1348 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 426 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_hits 1301 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 410 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1348 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1301 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1435 # Number of branches executed
|
||||
system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1424 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 82 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1078 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.357542 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2832 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1038 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 6007 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 8682 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 5952 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 8559 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.744120 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 4474 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 4429 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.346294 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8658 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 959 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 11489 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6462 # number of integer regfile writes
|
||||
system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 11291 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6385 # number of integer regfile writes
|
||||
system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 9108 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 12915 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705226 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 12915 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.368506 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 9351 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 31807 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8672 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 14983 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued
|
||||
system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 1808 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 1744 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 1774 # ITB hits
|
||||
system.cpu.itb.fetch_misses 34 # ITB misses
|
||||
system.cpu.itb.fetch_hits 1711 # ITB hits
|
||||
system.cpu.itb.fetch_misses 33 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
|
|
@ -398,22 +398,22 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -425,31 +425,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.006698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -457,40 +457,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 24826 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 24716 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 337 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:IdleCycles 8928 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 260 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14615 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11616 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8669 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2118 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 825 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 301 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4086 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 15016 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 14598 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 754 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 22718 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22732 # The number of ROB writes
|
||||
system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rob.rob_reads 22264 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 22135 # The number of ROB writes
|
||||
system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:49
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:45:02
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 7300000 because target called exit()
|
||||
Exiting @ tick 7289000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 33498 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222808 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 102057061 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 58135 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204672 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 176416397 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
sim_ticks 7300000 # Number of ticks simulated
|
||||
sim_ticks 7289000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 197 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 687 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 926 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condIncorrect 223 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 931 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 6308 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.408370 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 6308 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 2576 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 71 # Number of function calls committed.
|
||||
|
|
@ -44,24 +44,24 @@ system.cpu.commit.COM:loads 415 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.107667 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 589 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33939.814815 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35704.918033 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 481 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3665500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.183362 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 108 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2178000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.103565 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency
|
||||
|
|
@ -76,317 +76,317 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m
|
|||
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.270588 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 883 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35891.666667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 703 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 6460500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.203851 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 180 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3045500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.096263 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.011366 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 721 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 172 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 703 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 6460500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.203851 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 180 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3045500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.096263 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 721 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 46.556735 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 703 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BlockedCycles 217 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:DecodedInsts 5047 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 5111 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 977 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 374 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 1016 # DTB accesses
|
||||
system.cpu.decode.DECODE:UnblockCycles 3 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.data_accesses 1010 # DTB accesses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_hits 978 # DTB hits
|
||||
system.cpu.dtb.data_misses 38 # DTB misses
|
||||
system.cpu.dtb.data_hits 964 # DTB hits
|
||||
system.cpu.dtb.data_misses 46 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 648 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 644 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 627 # DTB read hits
|
||||
system.cpu.dtb.read_misses 21 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 368 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 617 # DTB read hits
|
||||
system.cpu.dtb.read_misses 27 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 366 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 351 # DTB write hits
|
||||
system.cpu.dtb.write_misses 17 # DTB write misses
|
||||
system.cpu.fetch.Branches 926 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 782 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed
|
||||
system.cpu.dtb.write_hits 347 # DTB write hits
|
||||
system.cpu.dtb.write_misses 19 # DTB write misses
|
||||
system.cpu.fetch.Branches 931 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 777 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 986 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 113 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5745 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 246 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.063859 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 777 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.394060 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 6682 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.859773 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.273067 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 5696 85.24% 85.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 43 0.64% 85.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 112 1.68% 87.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 72 1.08% 88.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 53 0.79% 91.28% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 50 0.75% 92.02% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 59 0.88% 92.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 474 7.09% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 6682 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 777 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36200.431034 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35306.629834 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 545 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 8398500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.298584 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 232 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6390500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.232947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.011050 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 548 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 234 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 777 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36200.431034 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 545 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 8398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.298584 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 232 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6390500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.232947 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.044195 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 548 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 234 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 545 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 8398500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.298584 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 232 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6390500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.232947 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 548 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 90.511194 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 545 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 601 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 306 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 1017 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 368 # Number of stores executed
|
||||
system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 600 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 311 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.241855 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 1011 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 366 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1981 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3402 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1995 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3404 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790977 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1576 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 793 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 1578 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.233487 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3463 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 649 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 58 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4585 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 645 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 109 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3526 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 4 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 378 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 4283 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2601 # number of integer regfile writes
|
||||
system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 364 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 134 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 4291 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2610 # number of integer regfile writes
|
||||
system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 2584 71.16% 71.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 3635 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 32 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 6682 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543999 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 6682 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.249331 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued
|
||||
system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 5975 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 4268 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3635 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 1704 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 811 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 806 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 782 # ITB hits
|
||||
system.cpu.itb.fetch_hits 777 # ITB hits
|
||||
system.cpu.itb.fetch_misses 29 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -406,12 +406,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000
|
|||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.446281 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.628099 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8307000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 7537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -423,31 +423,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34351.503759 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 9137500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8293000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.003658 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 9137500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 266 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8293000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -455,40 +455,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 119.871330 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 779 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.numCycles 14601 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 14579 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 55 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 5189 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 5515 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4879 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3490 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:SquashCycles 374 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 17 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1722 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 5503 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 74 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 10620 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 9524 # The number of ROB writes
|
||||
system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rob.rob_reads 10591 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 9519 # The number of ROB writes
|
||||
system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -496,7 +496,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 11 2011 20:10:09
|
||||
M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch
|
||||
M5 started Mar 11 2011 20:10:13
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
M5 compiled Mar 18 2011 20:12:03
|
||||
M5 started Mar 18 2011 21:02:41
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 10855000 because target called exit()
|
||||
Exiting @ tick 10827000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 4296 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 251256 # Number of bytes of host memory used
|
||||
host_seconds 1.34 # Real time elapsed on the host
|
||||
host_tick_rate 8125103 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 64369 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217368 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 121073299 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5739 # Number of instructions simulated
|
||||
sim_seconds 0.000011 # Number of seconds simulated
|
||||
sim_ticks 10855000 # Number of ticks simulated
|
||||
sim_ticks 10827000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 646 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1753 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 638 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1727 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1655 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2162 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condPredicted 1625 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2128 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 927 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 60 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 11145 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.514939 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.233206 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 11088 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.517587 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.238879 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 8562 76.82% 76.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1244 11.16% 87.99% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 554 4.97% 92.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 326 2.93% 95.88% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 181 1.62% 97.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 133 1.19% 98.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 54 0.48% 99.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 59 0.53% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 8513 76.78% 76.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1240 11.18% 87.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 548 4.94% 92.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 324 2.92% 95.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 182 1.64% 97.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 135 1.22% 98.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 54 0.49% 99.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 60 0.54% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 11145 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 11088 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5739 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 82 # Number of function calls committed.
|
||||
|
|
@ -47,11 +47,11 @@ system.cpu.commit.COM:swp_count 0 # Nu
|
|||
system.cpu.commit.branchMispredicts 318 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 4681 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4548 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5739 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.783063 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.783063 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 3.773305 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.773305 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
||||
|
|
@ -59,82 +59,82 @@ system.cpu.dcache.LoadLockedReq_miss_latency 76500
|
|||
system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_accesses 1862 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 32845.679012 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29990.825688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1700 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5321000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.087003 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 162 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3269000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.058539 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_accesses 1838 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 32906.832298 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1677 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5298000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.087595 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3270000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 109 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35254.295533 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35797.619048 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35365.979381 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35785.714286 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10259000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 10291500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1503500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1503000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 15.509934 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 15.357616 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34392.935982 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 31605.960265 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2322 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 15580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.163243 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 453 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 302 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4772500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.054414 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2751 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34490.044248 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2299 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 15589500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.164304 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 452 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4773000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.054889 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.022190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 90.890102 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34392.935982 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 31605.960265 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.022173 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 90.822117 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2751 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34490.044248 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2322 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 15580000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.163243 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 453 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 302 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4772500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.054414 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 2299 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 15589500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.164304 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 452 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4773000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.054889 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 90.890102 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2342 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 90.822117 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2319 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1262 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BlockedCycles 1287 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 156 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 341 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12417 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7526 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2297 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 804 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:BranchResolved 338 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12224 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7477 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2264 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 778 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 556 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
|
|
@ -158,175 +158,175 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 2162 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1609 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2418 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11261 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2128 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1580 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2383 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11094 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 506 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.099581 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1609 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 889 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.518677 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 11948 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.172497 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.587798 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.098268 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1580 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 875 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.512307 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 11865 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.163675 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.580533 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9530 79.76% 79.76% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 215 1.80% 81.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 150 1.26% 82.82% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 199 1.67% 84.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 194 1.62% 86.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 272 2.28% 88.38% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 117 0.98% 89.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 109 0.91% 90.27% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1162 9.73% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9482 79.92% 79.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 214 1.80% 81.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 146 1.23% 82.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 197 1.66% 84.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 189 1.59% 86.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 268 2.26% 88.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 115 0.97% 89.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 108 0.91% 90.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1146 9.66% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11948 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11865 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 1609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34710.914454 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33335.069444 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1270 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 11767000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.210690 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 339 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 9600500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.178993 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 1580 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34689.349112 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33338.541667 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1242 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 11725000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.213924 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 338 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 9601500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.182278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 4.409722 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.312500 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1609 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34710.914454 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 33335.069444 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1270 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 11767000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.210690 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 339 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 9600500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.178993 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 1580 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34689.349112 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1242 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 11725000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.213924 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 338 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 50 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 9601500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.182278 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.071695 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 146.831980 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1609 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34710.914454 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 33335.069444 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.071625 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 146.687091 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1580 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34689.349112 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1270 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 11767000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.210690 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 339 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 9600500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.178993 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 1242 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 11725000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.213924 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 338 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 50 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 9601500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.182278 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 288 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.sampled_refs 288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 146.831980 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1270 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 146.687091 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1242 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 9763 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1290 # Number of branches executed
|
||||
system.cpu.idleCycles 9790 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1278 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 18 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.381972 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 3149 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1151 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.379774 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 3122 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1148 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 7351 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7821 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.493674 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 7311 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7762 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.493093 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 3629 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.360232 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8026 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 368 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 195 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2420 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 3605 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.358439 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7965 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 367 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 201 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2382 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1527 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10583 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1998 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8293 # Number of executed instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1514 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10450 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1974 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8224 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 778 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 51 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1219 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 589 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 273 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1181 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 576 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 18798 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5617 # number of integer regfile writes
|
||||
system.cpu.ipc 0.264336 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.264336 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 18651 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5571 # number of integer regfile writes
|
||||
system.cpu.ipc 0.265020 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.265020 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5295 61.38% 61.38% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.45% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.03% 61.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2134 24.74% 86.23% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1188 13.77% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5254 61.43% 61.43% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.50% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.04% 61.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2109 24.66% 86.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1181 13.81% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 8626 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 8553 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.021563 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.021747 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 6 3.23% 3.23% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available
|
||||
|
|
@ -361,39 +361,39 @@ system.cpu.iq.ISSUE:fu_full::MemRead 120 64.52% 67.74% # at
|
|||
system.cpu.iq.ISSUE:fu_full::MemWrite 60 32.26% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 11948 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.721962 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.365135 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 11865 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.720860 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.364573 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8312 69.57% 69.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1403 11.74% 81.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 852 7.13% 88.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 582 4.87% 93.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 409 3.42% 96.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 241 2.02% 98.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 119 1.00% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 22 0.18% 99.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8254 69.57% 69.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1404 11.83% 81.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 840 7.08% 88.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 572 4.82% 93.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 408 3.44% 96.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 241 2.03% 98.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 114 0.96% 99.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 24 0.20% 99.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 11948 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.397310 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 11865 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.394967 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 8792 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 29375 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7805 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 14943 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 10540 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8626 # Number of instructions issued
|
||||
system.cpu.iq.int_alu_accesses 8719 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 29141 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7746 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 14669 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 10407 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8553 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4372 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6854 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6639 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -416,19 +416,19 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.761905 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31285.714286 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1445000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34416.666667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.809524 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1445500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1314000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34355.153203 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34356.545961 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31244.318182 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 12333500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 12334000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.904282 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 359 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
|
||||
|
|
@ -444,31 +444,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34360.349127 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31248.730964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34362.842893 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 13778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 13779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.913440 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 401 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 12312000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 12311500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.897494 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.005712 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 187.177998 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.005707 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 187.002555 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34360.349127 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31248.730964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34362.842893 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 38 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 13778500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 13779500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.913440 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 401 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 12312000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 12311500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.897494 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -476,40 +476,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 187.177998 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 187.002555 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2420 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1527 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 14141 # number of misc regfile reads
|
||||
system.cpu.memDep0.insertedLoads 2382 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1514 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 13955 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 4 # number of misc regfile writes
|
||||
system.cpu.numCycles 21711 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 21655 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 331 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4124 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 29 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 7791 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 7738 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 132 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 30367 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11639 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8331 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2090 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 804 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 195 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4204 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 29900 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11466 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8204 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2060 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 778 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 198 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4077 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 390 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 29977 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 745 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:int_rename_lookups 29510 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 760 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 568 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 569 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 21349 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21656 # The number of ROB writes
|
||||
system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rob.rob_reads 21158 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21364 # The number of ROB writes
|
||||
system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -169,6 +169,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -467,6 +468,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -502,6 +504,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:55:51
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:56:01
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 23:01:20
|
||||
M5 started Mar 17 2011 23:01:33
|
||||
M5 executing on zizzer
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 12784500 because target called exit()
|
||||
Exiting @ tick 12793500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 37179 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224748 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 91756799 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 71769 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206840 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 176990793 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5169 # Number of instructions simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 12784500 # Number of ticks simulated
|
||||
sim_ticks 12793500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 538 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1522 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 378 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1192 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 1744 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 1716 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 916 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 76 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 77 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12273 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.474701 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.213395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12220 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.476759 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 9782 79.70% 79.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1006 8.20% 87.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 705 5.74% 93.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 340 2.77% 96.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 96 0.78% 98.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 67 0.55% 99.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 76 0.62% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12220 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5826 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 87 # Number of function calls committed.
|
||||
|
|
@ -44,88 +44,88 @@ system.cpu.commit.COM:loads 1164 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2089 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 3481 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5169 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
|
||||
system.cpu.cpi 4.946798 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.946798 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 36046.875000 # average ReadReq miss latency
|
||||
system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1696 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4614000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.070175 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.049342 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34184.971098 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.078431 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 11828000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 16.134752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2749 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34687.763713 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 16442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.172426 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5080500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.022390 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 91.708831 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2749 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34687.763713 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.022393 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2275 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 16442000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.172426 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 2249 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 474 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5080500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 91.708831 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 736 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BlockedCycles 742 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 88 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 10461 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8771 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2729 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 649 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:BranchResolved 89 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 10279 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8753 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2688 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 636 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
|
|
@ -137,243 +137,242 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.432225 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 12922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.855286 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.122030 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10085 78.05% 78.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1182 9.15% 87.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 138 1.07% 88.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 127 0.98% 89.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 278 2.15% 91.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 124 0.96% 92.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 162 1.25% 93.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 99 0.77% 94.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 727 5.63% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10062 78.27% 78.27% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1173 9.12% 87.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 132 1.03% 88.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 122 0.95% 89.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 273 2.12% 91.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 123 0.96% 92.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 157 1.22% 93.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 97 0.75% 94.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 717 5.58% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1150 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14691000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.260450 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 405 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 76 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11523000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.211576 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.495441 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1555 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36274.074074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1150 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14691000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.260450 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 405 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 76 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11523000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.211576 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 402 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.077565 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 158.853467 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1555 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36274.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.077515 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1150 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14691000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.260450 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 405 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 76 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11523000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.211576 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 1129 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 402 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 15 # number of replacements
|
||||
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 158.853467 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1150 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1129 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 12648 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1183 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1244 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.279625 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2950 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1042 # Number of stores executed
|
||||
system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1171 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1220 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.276575 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2915 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1038 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 3586 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 6793 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.717513 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 3566 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 6732 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.716489 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 2573 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.265663 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 6861 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.WB:producers 2555 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.263092 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 6801 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2139 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1135 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9313 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 223 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7150 # Number of executed instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 649 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 66 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 5 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 975 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 210 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 945 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 202 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 9780 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 4751 # number of integer regfile writes
|
||||
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 9689 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 4703 # number of integer regfile writes
|
||||
system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 4328 58.70% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.75% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.78% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 7373 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.019259 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 7293 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 143 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.93% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 12922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.570577 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213210 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 12856 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567284 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 9579 74.13% 74.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1454 11.25% 85.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 793 6.14% 91.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 511 3.95% 95.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 304 2.35% 97.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 12856 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.285016 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 2456 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1522 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
|
|
@ -384,22 +383,22 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.078431 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1769500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34325.721154 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31134.615385 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14279500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
|
|
@ -411,31 +410,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34366.167024 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 16049000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14558000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.006661 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 218.261856 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.006657 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34366.167024 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 16049000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 467 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14558000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -443,38 +442,38 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 218.261856 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 136 # number of misc regfile reads
|
||||
system.cpu.numCycles 25570 # number of cpu cycles simulated
|
||||
system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 134 # number of misc regfile reads
|
||||
system.cpu.numCycles 25588 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 8904 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 12088 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 6119 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2609 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 11929 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 9880 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 6029 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2577 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 636 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:UndoneMaps 2619 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 21491 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 19268 # The number of ROB writes
|
||||
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:int_rename_lookups 11924 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 420 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 15 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 193 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 10 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 21319 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 19020 # The number of ROB writes
|
||||
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -116,6 +116,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -414,6 +415,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -449,6 +451,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: allowing mmap of file @ fd 42898616. This will break if not /dev/zero.
|
||||
warn: allowing mmap of file @ fd 17488232. This will break if not /dev/zero.
|
||||
For more information see: http://www.m5sim.org/warn/3a2134f6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 02:06:34
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:06:41
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 18 2011 02:41:27
|
||||
M5 started Mar 18 2011 02:41:29
|
||||
M5 executing on zizzer
|
||||
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 11733000 because target called exit()
|
||||
Exiting @ tick 11695000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 32835 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222408 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 66311402 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 15140 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204452 # Number of bytes of host memory used
|
||||
host_seconds 0.38 # Real time elapsed on the host
|
||||
host_tick_rate 30510356 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5800 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 11733000 # Number of ticks simulated
|
||||
sim_ticks 11695000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 679 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1865 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2100 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1734 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2075 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 187 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 1038 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 42 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 10395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.557961 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.275569 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 7869 75.70% 75.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1103 10.61% 86.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 649 6.24% 92.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 257 2.47% 95.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 223 2.15% 97.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 132 1.27% 98.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 100 0.96% 99.40% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 20 0.19% 99.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 42 0.40% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 10395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5800 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 103 # Number of function calls committed.
|
||||
|
|
@ -47,86 +47,86 @@ system.cpu.commit.COM:swp_count 0 # Nu
|
|||
system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 3301 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5800 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
|
||||
system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency
|
||||
system.cpu.cpi 4.032931 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.032931 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1431 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33954.022989 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_hits 1344 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2954000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.060797 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039133 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33770.226537 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36291.666667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 10435000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1742000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 20.009615 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_accesses 2477 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 33810.606061 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2081 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.159871 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 396 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 292 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3672000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.041986 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.016225 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 66.459259 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2477 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 33810.606061 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2093 # number of overall hits
|
||||
system.cpu.dcache.overall_hits 2081 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 397 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.159871 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 396 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 292 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3672000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.041986 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 66.459259 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2081 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:BlockedCycles 887 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 151 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 265 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 10261 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7524 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 1914 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 549 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 421 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
|
|
@ -137,243 +137,243 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2075 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1460 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 2040 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 218 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11548 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 402 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.088709 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1460 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 866 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.493694 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 10944 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.055190 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.449465 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 8904 81.36% 81.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 156 1.43% 82.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 186 1.70% 84.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 150 1.37% 85.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 199 1.82% 87.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 133 1.22% 88.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 272 2.49% 91.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 75 0.69% 92.06% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 869 7.94% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 10944 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 1460 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36594.488189 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34774.774775 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1079 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13942500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.260959 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11580000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.228082 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 333 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.240240 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 386 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 1460 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36594.488189 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1079 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13942500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.260959 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 381 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11580000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.228082 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 333 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.078664 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 161.104076 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1460 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36594.488189 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1104 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 386 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 1079 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13942500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.260959 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 381 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11580000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.228082 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 333 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 333 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1104 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 161.104076 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1079 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1261 # Number of branches executed
|
||||
system.cpu.idleCycles 12447 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1262 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1315 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.332008 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2790 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1305 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 5926 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7582 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 5916 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7563 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.645030 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 3825 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.WB:producers 3816 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.323329 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7623 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 1666 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 100 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1436 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9097 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1485 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 12419 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6594 # number of integer regfile writes
|
||||
system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 704 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 390 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 12407 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 6585 # number of integer regfile writes
|
||||
system.cpu.ipc 0.247959 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.247959 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5116 63.51% 63.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.51% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.54% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1580 19.62% 83.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1357 16.85% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 8055 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 152 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018870 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.24% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.24% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 72 47.37% 54.61% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.39% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 10944 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.736020 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.423307 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 7700 70.36% 70.36% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1176 10.75% 81.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 793 7.25% 88.35% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 485 4.43% 92.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 365 3.34% 96.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 233 2.13% 98.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 138 1.26% 99.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 47 0.43% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 10944 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.344363 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued
|
||||
system.cpu.iq.int_alu_accesses 8176 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 27162 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7536 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 11998 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 9075 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8055 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 2924 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2633 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
|
|
@ -384,97 +384,97 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34937.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1677000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 389 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34322.834646 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.981627 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 13077000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.979434 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 381 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11867000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979434 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 381 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.020997 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 437 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34391.608392 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 14754000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.981693 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 429 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13392000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.981693 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.005859 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 191.979751 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 437 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34391.608392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 8 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 428 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 14754000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.981693 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 429 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13392000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.981693 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 429 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 381 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 191.979751 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 23467 # number of cpu cycles simulated
|
||||
system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 1666 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1436 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 23391 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:BlockCycles 314 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 7703 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 16001 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 9789 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8584 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 1797 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 549 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 244 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 3577 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 15946 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 471 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 19611 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 18950 # The number of ROB writes
|
||||
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rob.rob_reads 19454 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 18753 # The number of ROB writes
|
||||
system.cpu.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 1 2011 23:14:11
|
||||
M5 revision 42f62a19a71d 8104 default qbase qtip tip x86seo3stats.patch
|
||||
M5 started Mar 1 2011 23:14:13
|
||||
M5 executing on burrito
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
|
||||
M5 compiled Mar 18 2011 20:12:06
|
||||
M5 started Mar 18 2011 20:30:23
|
||||
M5 executing on zizzer
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 11421500 because target called exit()
|
||||
Exiting @ tick 11371000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 103787 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224152 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 120600528 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 85944 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211192 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 99394076 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9809 # Number of instructions simulated
|
||||
sim_seconds 0.000011 # Number of seconds simulated
|
||||
sim_ticks 11421500 # Number of ticks simulated
|
||||
sim_ticks 11371000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 931 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 2531 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2777 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 2758 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2758 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 1214 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 141 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 11809 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.830638 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.597584 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 8189 69.35% 69.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1225 10.37% 79.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 582 4.93% 84.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 11809 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 9809 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -47,334 +47,334 @@ system.cpu.commit.COM:swp_count 0 # Nu
|
|||
system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 9222 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 9809 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 2.318585 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.318585 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.020965 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 85.873455 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2048 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 427 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 2039 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 426 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 85.873455 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed
|
||||
system.cpu.decode.DECODE:BlockedCycles 1369 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 22088 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7085 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 3278 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1477 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 77 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 2758 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1703 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3590 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 238 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12847 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.121268 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1703 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 931 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.564877 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 13286 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.734834 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.110520 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 9786 73.66% 73.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 161 1.21% 74.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 122 0.92% 75.79% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 227 1.71% 77.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 192 1.45% 78.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 168 1.26% 80.20% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 257 1.93% 82.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 171 1.29% 83.43% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 2202 16.57% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13286 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
||||
system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 1703 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36577.562327 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1342 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13204500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.211979 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10354500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.173224 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.549153 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 1703 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36577.562327 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35100 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1342 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.211979 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 361 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10354500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.173224 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.070743 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 144.881554 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1703 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36577.562327 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35100 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1367 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 365 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 1342 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13204500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.211979 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 361 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10354500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.173224 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1367 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 144.881554 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1342 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1551 # Number of branches executed
|
||||
system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1545 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.676108 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2970 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1306 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.675461 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2952 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1295 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 14702 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 15138 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.679703 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 14668 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 15056 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.677734 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 9993 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 15262 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.WB:producers 9941 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.662006 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 15179 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 566 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2082 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1664 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 15445 # Number of executed instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1617 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 19032 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 693 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 15362 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 69 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1026 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 683 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 23049 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 14062 # number of integer regfile writes
|
||||
system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 22959 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 13993 # number of integer regfile writes
|
||||
system.cpu.ipc 0.431298 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.431298 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.27% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1785 11.05% 91.34% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 12893 80.31% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 16155 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.008790 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 16055 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 147 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009156 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.71% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 27 18.37% 87.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204698 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912453 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 13286 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.208415 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.917020 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 788 5.88% 90.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 587 4.38% 94.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 8201 61.73% 61.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1290 9.71% 71.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.42% 78.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 726 5.46% 84.32% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 782 5.89% 90.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 580 4.37% 94.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.707188 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 13286 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.705931 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 16288 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 45906 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 19151 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 16155 # Number of instructions issued
|
||||
system.cpu.iq.int_alu_accesses 16193 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 45588 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 15052 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 27650 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 18999 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 16055 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 8610 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 11055 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 10851 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2664500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 12328000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -389,31 +389,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34307.780320 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 14992500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.005438 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 178.188786 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34307.780320 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 14992500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 437 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -421,39 +421,39 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 178.188786 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 23 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 6856 # number of misc regfile reads
|
||||
system.cpu.numCycles 22844 # number of cpu cycles simulated
|
||||
system.cpu.memDep0.insertedLoads 2082 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1617 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 6812 # number of misc regfile reads
|
||||
system.cpu.numCycles 22743 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:IQFullEvents 52 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 7327 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 248 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 44292 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 21008 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 19746 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 3097 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1477 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 380 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 10378 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:int_rename_lookups 44276 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 1483 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 30950 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 39896 # The number of ROB writes
|
||||
system.cpu.rob.rob_reads 30699 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 39564 # The number of ROB writes
|
||||
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:39
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 21:44:37
|
||||
M5 started Mar 17 2011 21:44:41
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -16,4 +15,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Hello world!
|
||||
Exiting @ tick 14139000 because target called exit()
|
||||
Exiting @ tick 14058000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -115,6 +115,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -413,6 +414,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
@ -448,6 +450,7 @@ assoc=2
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
|
|
|
|||
|
|
@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:49
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 23:04:27
|
||||
M5 started Mar 17 2011 23:04:36
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -23,4 +22,4 @@ LDTX: Passed
|
|||
LDTW: Passed
|
||||
STTW: Passed
|
||||
Done
|
||||
Exiting @ tick 18656000 because target called exit()
|
||||
Exiting @ tick 18633000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 30834 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 224180 # Number of bytes of host memory used
|
||||
host_seconds 0.47 # Real time elapsed on the host
|
||||
host_tick_rate 39786625 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 81712 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206196 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 105251575 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18656000 # Number of ticks simulated
|
||||
sim_ticks 18633000 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 2698 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 5085 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 5172 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 5172 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 5154 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 3359 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 86 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 27579 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.550237 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.187070 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 27481 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.552200 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 19793 71.77% 71.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 4521 16.39% 88.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 1461 5.30% 93.46% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 765 2.77% 96.23% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 373 1.35% 97.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 38 0.14% 99.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 86 0.31% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 27481 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 15175 # Number of instructions committed
|
||||
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
|
||||
|
|
@ -47,254 +47,254 @@ system.cpu.commit.COM:swp_count 0 # Nu
|
|||
system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 5133 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 14449 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.582393 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.582393 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2777 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.cpi 2.579210 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.579210 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2764 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2653 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits 2640 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.044653 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.044863 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022793 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35892.156863 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35843.373494 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35890.931373 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35837.349398 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 14644000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 14643500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2975000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2974500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 25.294521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 25.205479 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 4219 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3687 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.126096 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 4206 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35361.842105 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3674 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 18812500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.126486 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.034605 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.034712 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.024937 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 102.143173 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 4219 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.024936 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 102.139862 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 4206 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35361.842105 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 3687 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.126096 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 3674 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 18812500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.126486 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 532 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.034605 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5215000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.034712 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 102.143173 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3693 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 102.139862 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3680 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 7077 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 23586 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 13112 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 7266 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1178 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:BlockedCycles 7079 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 23444 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 13037 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 7241 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1159 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 5154 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4051 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 7481 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 377 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 23840 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2698 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.642725 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 28740 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.834447 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.949360 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.SquashCycles 813 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.138299 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4051 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2697 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.639708 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 28623 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.832897 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.946042 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 21234 73.88% 73.88% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3581 12.46% 86.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 587 2.04% 88.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 509 1.77% 90.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 664 2.31% 92.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 529 1.84% 94.31% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 246 0.86% 95.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 197 0.69% 95.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1193 4.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 21142 73.86% 73.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3578 12.50% 86.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 587 2.05% 88.41% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 505 1.76% 90.18% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 662 2.31% 92.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 528 1.84% 94.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 244 0.85% 95.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 195 0.68% 95.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1182 4.13% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 28740 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 4077 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34819.301848 # average ReadReq miss latency
|
||||
system.cpu.fetch.rateDist::total 28623 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 4051 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35069.791667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 3590 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 16957000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.119451 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_hits 3571 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 16833500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.118489 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 480 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 126 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.086829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.087386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 10.141243 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10.087571 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4077 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34819.301848 # average overall miss latency
|
||||
system.cpu.icache.demand_accesses 4051 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35069.791667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 3590 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 16957000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.119451 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 487 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_hits 3571 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 16833500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.118489 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 480 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 126 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.086829 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.087386 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.099779 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 204.347725 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 4077 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34819.301848 # average overall miss latency
|
||||
system.cpu.icache.occ_%::0 0.099792 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 204.373592 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 4051 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35069.791667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 3590 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 16957000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.119451 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 487 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_hits 3571 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 16833500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.118489 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 480 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 126 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.086829 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.087386 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 204.347725 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 3590 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 204.373592 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 3571 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 8573 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3856 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1087 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.470989 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 4619 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1763 # Number of stores executed
|
||||
system.cpu.idleCycles 8644 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3851 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1086 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.469692 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 4584 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1742 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 9338 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 17128 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.855858 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 9307 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 17063 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.856022 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 7992 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.459036 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 17304 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.WB:producers 7967 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.457858 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 17239 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 566 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispLoadInsts 3044 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 564 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1925 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 20324 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2856 # Number of load instructions executed
|
||||
system.cpu.iew.iewDispStoreInsts 1894 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 20242 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2842 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 17574 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 17504 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1178 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 31 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 832 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 477 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 818 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 446 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.int_regfile_reads 28146 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 15679 # number of integer regfile writes
|
||||
system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 28062 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 15640 # number of integer regfile writes
|
||||
system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 13302 73.74% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.74% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2921 16.19% 89.93% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1816 10.07% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 13268 73.84% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2908 16.18% 90.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1793 9.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 18039 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 17969 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 125 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006929 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006956 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available
|
||||
|
|
@ -329,43 +329,43 @@ system.cpu.iq.ISSUE:fu_full::MemRead 29 23.20% 45.60% # at
|
|||
system.cpu.iq.ISSUE:fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 28740 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627662 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192852 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 28623 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627782 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.193207 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 19886 69.19% 69.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 4262 14.83% 84.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 1894 6.59% 90.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 1722 5.99% 96.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 431 1.50% 98.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 279 0.97% 99.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 19805 69.19% 69.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 4241 14.82% 84.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 1891 6.61% 90.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 1717 6.00% 96.61% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 425 1.48% 98.10% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 278 0.97% 99.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 79 0.28% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 28623 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.482169 # Inst issue rate
|
||||
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
||||
system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4088 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.int_alu_accesses 18094 # Number of integer alu accesses
|
||||
system.cpu.iq.int_inst_queue_reads 64767 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 17063 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_writes 23189 # Number of integer instruction queue writes
|
||||
system.cpu.iq.iqInstsAdded 18592 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 17969 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 564 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4009 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3563 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2871500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2871000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles
|
||||
|
|
@ -390,10 +390,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34361.895161 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34360.887097 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 17043500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 17043000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -403,14 +403,14 @@ system.cpu.l2cache.demand_mshr_misses 496 # nu
|
|||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.007282 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 238.619810 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.007283 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 238.651434 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34361.895161 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34360.887097 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 17043500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 17043000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 496 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -422,38 +422,38 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 238.619810 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 238.651434 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 6238 # number of misc regfile reads
|
||||
system.cpu.memDep0.insertedLoads 3044 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1894 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.misc_regfile_reads 6202 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.numCycles 37313 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 37267 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 13492 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 40450 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 21815 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 19528 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 7042 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 40241 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 21695 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 19448 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 7019 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1159 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 46980 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 41800 # The number of ROB writes
|
||||
system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:UndoneMaps 5616 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:int_rename_lookups 40241 # Number of integer rename lookups
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6278 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 613 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2673 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 579 # count of temporary serializing insts renamed
|
||||
system.cpu.rob.rob_reads 46798 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 41616 # The number of ROB writes
|
||||
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -115,6 +115,7 @@ assoc=4
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -413,6 +414,7 @@ assoc=1
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -560,6 +562,7 @@ assoc=4
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -858,6 +861,7 @@ assoc=1
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -986,6 +990,7 @@ assoc=4
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -1284,6 +1289,7 @@ assoc=1
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -1412,6 +1418,7 @@ assoc=4
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -1710,6 +1717,7 @@ assoc=1
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
|
|
@ -1748,6 +1756,7 @@ assoc=8
|
|||
block_size=64
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
|
|
|
|||
|
|
@ -5,69 +5,68 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 02:13:30
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 02:13:39
|
||||
M5 executing on burrito
|
||||
M5 compiled Mar 17 2011 23:04:27
|
||||
M5 started Mar 17 2011 23:09:03
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Init done
|
||||
[Iteration 1, Thread 2] Got lock
|
||||
[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 1, Thread 3] Got lock
|
||||
[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 1, Thread 1] Got lock
|
||||
[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 1, Thread 3] Got lock
|
||||
[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
|
||||
Iteration 1 completed
|
||||
[Iteration 2, Thread 3] Got lock
|
||||
[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 2, Thread 1] Got lock
|
||||
[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 2, Thread 2] Got lock
|
||||
[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 2, Thread 3] Got lock
|
||||
[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
|
||||
Iteration 2 completed
|
||||
[Iteration 3, Thread 2] Got lock
|
||||
[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 3, Thread 3] Got lock
|
||||
[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 3, Thread 1] Got lock
|
||||
[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 3, Thread 2] Got lock
|
||||
[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
|
||||
Iteration 3 completed
|
||||
[Iteration 4, Thread 1] Got lock
|
||||
[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 4, Thread 2] Got lock
|
||||
[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 4, Thread 3] Got lock
|
||||
[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 4, Thread 1] Got lock
|
||||
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
|
||||
Iteration 4 completed
|
||||
[Iteration 5, Thread 3] Got lock
|
||||
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 5, Thread 2] Got lock
|
||||
[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 5, Thread 1] Got lock
|
||||
[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 5, Thread 3] Got lock
|
||||
[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
|
||||
Iteration 5 completed
|
||||
[Iteration 6, Thread 1] Got lock
|
||||
[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 6, Thread 3] Got lock
|
||||
[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 6, Thread 2] Got lock
|
||||
[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 6, Thread 3] Got lock
|
||||
[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
|
||||
Iteration 6 completed
|
||||
[Iteration 7, Thread 2] Got lock
|
||||
[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 7, Thread 1] Got lock
|
||||
[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 7, Thread 3] Got lock
|
||||
[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 7, Thread 2] Got lock
|
||||
[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
|
||||
Iteration 7 completed
|
||||
[Iteration 8, Thread 2] Got lock
|
||||
[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 8, Thread 3] Got lock
|
||||
[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 8, Thread 2] Got lock
|
||||
[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 8, Thread 1] Got lock
|
||||
[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
|
||||
Iteration 8 completed
|
||||
[Iteration 9, Thread 2] Got lock
|
||||
[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
|
||||
|
|
@ -76,12 +75,12 @@ Iteration 8 completed
|
|||
[Iteration 9, Thread 1] Got lock
|
||||
[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
|
||||
Iteration 9 completed
|
||||
[Iteration 10, Thread 3] Got lock
|
||||
[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 10, Thread 2] Got lock
|
||||
[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 10, Thread 1] Got lock
|
||||
[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 10, Thread 2] Got lock
|
||||
[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 10, Thread 3] Got lock
|
||||
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
|
||||
Iteration 10 completed
|
||||
PASSED :-)
|
||||
Exiting @ tick 117496500 because target called exit()
|
||||
Exiting @ tick 117445500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue