522 lines
58 KiB
Text
522 lines
58 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 146692 # Simulator instruction rate (inst/s)
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host_mem_usage 221392 # Number of bytes of host memory used
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host_seconds 11746.21 # Real time elapsed on the host
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host_tick_rate 54703941 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1723073879 # Number of instructions simulated
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sim_seconds 0.642564 # Number of seconds simulated
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sim_ticks 642564184000 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 223408375 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 259871172 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 422 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 18003899 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 242860493 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 296348291 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 17775010 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 213462249 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 57892406 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 1166021349 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.477738 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.107067 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 510165620 43.75% 43.75% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 303741868 26.05% 69.80% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 123389035 10.58% 80.38% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 73903803 6.34% 86.72% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 37047511 3.18% 89.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 32051525 2.75% 92.65% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 15551434 1.33% 93.98% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 12278147 1.05% 95.04% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 57892406 4.96% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1166021349 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1723073897 # Number of instructions committed
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system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 13665177 # Number of function calls committed.
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system.cpu.commit.COM:int_insts 1536941877 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 485926777 # Number of loads committed
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system.cpu.commit.COM:membars 62 # Number of memory barriers committed
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system.cpu.commit.COM:refs 660773829 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 18003533 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1723073897 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 463 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 488491112 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1723073879 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1723073879 # Number of Instructions Simulated
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system.cpu.cpi 0.745835 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.745835 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 38333.333333 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 115000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_accesses 502016934 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15157.913551 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11504.970685 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 493884953 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 123263865000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.016199 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 8131981 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 482230 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 88010161000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.015238 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7649751 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 68 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 68 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23727.454668 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20867.425320 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 168020006 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 108340530838 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.026457 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 4566041 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 2674070 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 39480563550 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.010962 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1891971 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 3133.925265 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 19555.555556 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 69.369565 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 25102 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 78667792 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 176000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 674602981 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 18239.407353 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 661904959 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 231604395838 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.018823 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 12698022 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 3156300 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 127490724550 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.014144 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9541722 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.997821 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4087.076226 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 674602981 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 18239.407353 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 13361.395831 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 661904959 # number of overall hits
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system.cpu.dcache.overall_miss_latency 231604395838 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.018823 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 12698022 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 3156300 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 127490724550 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.014144 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9541722 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 9537626 # number of replacements
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system.cpu.dcache.sampled_refs 9541722 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4087.076226 # Cycle average of tags in use
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system.cpu.dcache.total_refs 661905101 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 5039888000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 3122150 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 126134544 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 631 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 46158003 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 2344918841 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 578373170 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 449937268 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 70475039 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 2244 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 11576366 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 296348291 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 276432138 # Number of cache lines fetched
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system.cpu.fetch.Cycles 470132828 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 5100693 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2155880694 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 18543154 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.230598 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 276432138 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 241183385 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.677561 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1236496387 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.931778 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.884875 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 766363617 61.98% 61.98% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 33302617 2.69% 64.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 59273636 4.79% 69.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 61386146 4.96% 74.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 46873479 3.79% 78.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 54969771 4.45% 82.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 53004501 4.29% 86.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 18322602 1.48% 88.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 143000018 11.56% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1236496387 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 41 # number of floating regfile reads
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system.cpu.fp_regfile_writes 33 # number of floating regfile writes
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system.cpu.icache.ReadReq_accesses 276432138 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 34722.162741 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34464.838256 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 276431204 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 32430500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 223 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 24504500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 711 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 388792.129395 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 276432138 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 34722.162741 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency
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system.cpu.icache.demand_hits 276431204 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 32430500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_misses 934 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 223 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 24504500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 711 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.280397 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 574.252402 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 276432138 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 34722.162741 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 34464.838256 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 276431204 # number of overall hits
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system.cpu.icache.overall_miss_latency 32430500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
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system.cpu.icache.overall_misses 934 # number of overall misses
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system.cpu.icache.overall_mshr_hits 223 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 24504500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 711 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 8 # number of replacements
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system.cpu.icache.sampled_refs 711 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 574.252402 # Cycle average of tags in use
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system.cpu.icache.total_refs 276431204 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 48631982 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 233424980 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 482 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.517936 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 747978494 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 187773804 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 2256428952 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 1928922171 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.551030 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 1243359181 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.500957 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 1935148462 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 19351048 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 24037939 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 626206356 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 572 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 5915627 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 225279083 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 2211459502 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 560204690 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 21122432 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 1950742523 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 1443603 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 76182 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 70475039 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 2501364 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 185277 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 54176834 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 572517 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 735122 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 140279578 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 50432031 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 735122 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 3222127 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 16128921 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.int_regfile_reads 5041119538 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1533310252 # number of integer regfile writes
|
|
system.cpu.ipc 1.340780 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.340780 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1212671548 61.50% 61.50% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1140441 0.06% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 7 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 8 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 568624535 28.84% 90.39% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 189428413 9.61% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 1971864955 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 20980180 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010640 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 466922 2.23% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 19229106 91.65% 93.88% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 1284151 6.12% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1236496387 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.594720 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.635591 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 417933228 33.80% 33.80% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 278405850 22.52% 56.32% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 219666046 17.77% 74.08% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 150452877 12.17% 86.25% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 89712597 7.26% 93.50% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 51644953 4.18% 97.68% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 17725773 1.43% 99.11% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 8301913 0.67% 99.79% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 2653150 0.21% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1236496387 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 1.534372 # Inst issue rate
|
|
system.cpu.iq.fp_alu_accesses 65 # Number of floating point alu accesses
|
|
system.cpu.iq.fp_inst_queue_reads 124 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 53 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_writes 108 # Number of floating instruction queue writes
|
|
system.cpu.iq.int_alu_accesses 1992845070 # Number of integer alu accesses
|
|
system.cpu.iq.int_inst_queue_reads 5201866882 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1928922118 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.int_inst_queue_writes 2697398990 # Number of integer instruction queue writes
|
|
system.cpu.iq.iqInstsAdded 2211458379 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 1971864955 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 641 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 485334084 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 660529 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 844272367 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 1891974 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34486.894931 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.697108 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_hits 979846 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31456462500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482104 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 912128 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28587639500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482104 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912128 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 7650459 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.020010 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.460219 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 5630454 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 69318532000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.264037 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 2020005 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 62879334000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264036 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2019995 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 3122150 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 3122150 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3879.110251 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 2.653657 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 3619 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 14038500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 9542433 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34369.175784 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 6610300 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 100774994500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.307273 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 2932133 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 91466973500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307272 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 2932123 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.488260 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_%::1 0.329752 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 15999.295959 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 10805.300698 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 9542433 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34369.175784 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.794182 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 6610300 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 100774994500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.307273 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 2932133 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 91466973500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307272 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 2932123 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 2919711 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 2947033 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 26804.596658 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 7820415 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 143356933000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 1216362 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 94435755 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 90423649 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 626206356 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 225279083 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.misc_regfile_reads 2884410167 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 896 # number of misc regfile writes
|
|
system.cpu.numCycles 1285128369 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.rename.RENAME:BlockCycles 66687922 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1360917734 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 14597587 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 600232966 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 40535929 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 10237 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 6332213633 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 2292978845 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 1803334951 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 438824808 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 70475039 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 60261068 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 442417214 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:fp_rename_lookups 432 # Number of floating rename lookups
|
|
system.cpu.rename.RENAME:int_rename_lookups 6332213201 # Number of integer rename lookups
|
|
system.cpu.rename.RENAME:serializeStallCycles 14584 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 629 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 117068052 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 624 # count of temporary serializing insts renamed
|
|
system.cpu.rob.rob_reads 3319693353 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4493611781 # The number of ROB writes
|
|
system.cpu.timesIdled 1545196 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|