525 lines
59 KiB
Plaintext
525 lines
59 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 120907 # Simulator instruction rate (inst/s)
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host_mem_usage 227772 # Number of bytes of host memory used
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host_seconds 15593.28 # Real time elapsed on the host
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host_tick_rate 54949698 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1885343186 # Number of instructions simulated
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sim_seconds 0.856846 # Number of seconds simulated
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sim_ticks 856846060000 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 305871415 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 427428565 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 4211226 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 36020935 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 415846626 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 551391601 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 57603360 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 291323460 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 56939437 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 1535085949 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.228175 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.842995 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 710902830 46.31% 46.31% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 422912424 27.55% 73.86% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 179951323 11.72% 85.58% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 73924591 4.82% 90.40% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 52811288 3.44% 93.84% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 15756065 1.03% 94.86% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 17991551 1.17% 96.04% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 3896440 0.25% 96.29% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 56939437 3.71% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1535085949 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1885354202 # Number of instructions committed
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system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 41577833 # Number of function calls committed.
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system.cpu.commit.COM:int_insts 1660589612 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 631390749 # Number of loads committed
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system.cpu.commit.COM:membars 9986 # Number of memory barriers committed
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system.cpu.commit.COM:refs 908389613 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 41574667 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1885354202 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 211799 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1130143872 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1885343186 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1885343186 # Number of Instructions Simulated
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system.cpu.cpi 0.908955 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.908955 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 16574 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 16571 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.000181 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_accesses 710900650 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34447.466761 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34122.014006 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 708969387 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 66527118000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002717 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1931263 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 468894 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 49898975500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002057 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1462369 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 13552 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 13552 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 276935679 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 35080.855979 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32457.559426 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 276128837 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 28304708000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002913 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 806842 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 734105 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2360865500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 72737 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 641.733949 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 987836329 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34634.108626 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 985098224 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 94831826000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.002772 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2738105 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1202999 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 52259841000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.001554 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1535106 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999728 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.887061 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 987836329 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34634.108626 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 34043.148160 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 985098224 # number of overall hits
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system.cpu.dcache.overall_miss_latency 94831826000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.002772 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2738105 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1202999 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 52259841000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.001554 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1535106 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1531008 # number of replacements
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system.cpu.dcache.sampled_refs 1535104 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.887061 # Cycle average of tags in use
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system.cpu.dcache.total_refs 985128352 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 336577000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 107051 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 147664711 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 10715 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 87011249 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 3347721217 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 741403203 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 643451103 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 155800890 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 20615 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 2566930 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 551391601 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 362185761 # Number of cache lines fetched
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system.cpu.fetch.Cycles 665483414 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 16434136 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2595927696 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 41205 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 42962333 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.321757 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 362185761 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 363474775 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.514816 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1690886837 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.036253 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.984064 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 1025439720 60.65% 60.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 44027477 2.60% 63.25% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 104237585 6.16% 69.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 62717330 3.71% 73.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 88060980 5.21% 78.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 56164505 3.32% 81.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 31149333 1.84% 83.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 50263393 2.97% 86.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 228826514 13.53% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1690886837 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 71543856 # number of floating regfile reads
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system.cpu.fp_regfile_writes 49528271 # number of floating regfile writes
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system.cpu.icache.ReadReq_accesses 362185761 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 9513.703009 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 6161.539130 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 362162299 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 223210500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 23462 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 449 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 141795500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 23013 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 15738.659728 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 362185761 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 9513.703009 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency
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system.cpu.icache.demand_hits 362162299 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 223210500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses
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system.cpu.icache.demand_misses 23462 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 141795500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 23013 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.754539 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 1545.296100 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 362185761 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 9513.703009 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 6161.539130 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 362162299 # number of overall hits
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system.cpu.icache.overall_miss_latency 223210500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses
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system.cpu.icache.overall_misses 23462 # number of overall misses
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system.cpu.icache.overall_mshr_hits 449 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 141795500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 23013 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 21424 # number of replacements
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system.cpu.icache.sampled_refs 23011 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1545.296100 # Cycle average of tags in use
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system.cpu.icache.total_refs 362162299 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 22805284 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 354837598 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 98250 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.389523 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 1168779203 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 410575996 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 2421323747 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 2344814753 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.534499 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 1294194313 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.368282 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 2351424737 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 45254697 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 17472224 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 920596247 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 229114 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 5701638 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 478927516 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 3015512989 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 758203207 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 66026694 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 2381213830 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 1233247 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 293 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 155800890 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 2569235 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 34849398 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 1378004 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 2578924 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 289205497 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 201928652 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 2578924 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 7840428 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 37414269 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.int_regfile_reads 5603494067 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1718225433 # number of integer regfile writes
|
|
system.cpu.ipc 1.100164 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.100164 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1176897350 48.09% 48.09% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 11209556 0.46% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 8683 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.55% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 48.61% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.61% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876474 0.28% 48.89% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501174 0.22% 49.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.11% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23385811 0.96% 50.07% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.07% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.07% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.07% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 790636932 32.31% 82.37% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 431349255 17.63% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 2447240524 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 85394641 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.034894 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 17844 0.02% 0.02% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.03% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 55081470 64.50% 64.55% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 30271214 35.45% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1690886837 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.447312 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.581356 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 652913002 38.61% 38.61% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 347943808 20.58% 59.19% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 308699944 18.26% 77.45% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 176613135 10.45% 87.89% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 115002206 6.80% 94.69% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 60495189 3.58% 98.27% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 19163759 1.13% 99.41% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 5856252 0.35% 99.75% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 4199542 0.25% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1690886837 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 1.428051 # Inst issue rate
|
|
system.cpu.iq.fp_alu_accesses 67428170 # Number of floating point alu accesses
|
|
system.cpu.iq.fp_inst_queue_reads 127980204 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 59166521 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_writes 84999921 # Number of floating instruction queue writes
|
|
system.cpu.iq.int_alu_accesses 2465206995 # Number of integer alu accesses
|
|
system.cpu.iq.int_inst_queue_reads 6542850406 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2285648232 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.int_inst_queue_writes 4061650965 # Number of integer instruction queue writes
|
|
system.cpu.iq.iqInstsAdded 3015173249 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 2447240524 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 241490 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 1129860503 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 68084 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 29691 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 1732452415 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 72735 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.577525 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.142520 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_hits 6653 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2279735000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908531 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048617500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908531 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 1485380 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34263.370250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.336529 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 70915 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 48464338000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.952258 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 1414465 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43848085000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.952241 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1414439 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
|
|
system.cpu.l2cache.Writeback_accesses 107051 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 107051 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.052408 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 1558115 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34273.868374 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 77568 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 50744073000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.950217 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 1480547 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 45896702500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.950200 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 1480521 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.884259 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_%::1 0.091385 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 28975.398232 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 2994.491803 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 1558115 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34273.868374 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.372504 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 77568 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 50744073000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.950217 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 1480547 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 45896702500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.950200 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 1480521 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 1479423 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 1512143 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 31969.890035 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 79248 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 68608597 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 90712102 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 920596247 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 478927516 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.misc_regfile_reads 3922986795 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 14227477 # number of misc regfile writes
|
|
system.cpu.numCycles 1713692121 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.rename.RENAME:BlockCycles 26481185 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 1523914787 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 14530739 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 769489537 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 9665417 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 8794817078 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 3244153999 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 2590050394 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 617757360 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 155800890 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 32816862 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1066135604 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:fp_rename_lookups 420246695 # Number of floating rename lookups
|
|
system.cpu.rename.RENAME:int_rename_lookups 8374570383 # Number of integer rename lookups
|
|
system.cpu.rename.RENAME:serializeStallCycles 88541003 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 8494560 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 86318102 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 244150 # count of temporary serializing insts renamed
|
|
system.cpu.rob.rob_reads 4493626241 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6186797097 # The number of ROB writes
|
|
system.cpu.timesIdled 1346446 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|