Stats: Update stats for the end of macroop O3 fix.
This commit is contained in:
Gabe Black
parent
96df6bedb7
commit
c3e7b57fe7
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 29 2011 20:26:37
|
||||
gem5 started Jul 29 2011 20:48:01
|
||||
gem5 executing on chips
|
||||
gem5 compiled Aug 9 2011 03:42:03
|
||||
gem5 started Aug 9 2011 03:42:10
|
||||
gem5 executing on burrito
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -77,4 +77,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 589091030500 because target called exit()
|
||||
Exiting @ tick 589090675500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,111 +1,111 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.589091 # Number of seconds simulated
|
||||
sim_ticks 589091030500 # Number of ticks simulated
|
||||
sim_ticks 589090675500 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 49258 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 18978173 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295880 # Number of bytes of host memory used
|
||||
host_seconds 31040.45 # Real time elapsed on the host
|
||||
host_inst_rate 112556 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 43365548 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 283452 # Number of bytes of host memory used
|
||||
host_seconds 13584.30 # Real time elapsed on the host
|
||||
sim_insts 1528988756 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1178182062 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1178181352 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 273761265 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 273761265 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 16674451 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 263536276 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 242767541 # Number of BTB hits
|
||||
system.cpu.BPredUnit.lookups 273757623 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 273757623 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 16675490 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 263549341 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 242783389 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 225401739 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1479491237 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 273761265 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 242767541 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 481293479 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 151906639 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 310358481 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 81567 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 542630 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 210837285 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 3978525 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1150020807 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.401549 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.263992 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.icacheStallCycles 225396443 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1479442245 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 273757623 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 242783389 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 481291877 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 151896782 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 310377272 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 81634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 545852 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 210829674 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 3979750 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1150024812 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.401504 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.263970 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 673309579 58.55% 58.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 35910144 3.12% 61.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 42110719 3.66% 65.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 37429485 3.25% 68.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 23065553 2.01% 70.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 42484640 3.69% 74.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 50557962 4.40% 78.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 39843815 3.46% 82.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 205308910 17.85% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 673316869 58.55% 58.55% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 35917007 3.12% 61.67% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 42114186 3.66% 65.33% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 37411519 3.25% 68.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 23065398 2.01% 70.59% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 42495758 3.70% 74.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 50561789 4.40% 78.68% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 39840695 3.46% 82.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 205301591 17.85% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1150020807 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.232359 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.255741 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 295424078 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 258223028 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 403450354 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 60580436 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 132342911 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2687346681 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 53 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 132342911 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 338937785 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 65386701 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 28791 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 418304100 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 195020519 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2631430164 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 26828 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 78975062 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 100019003 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 2450674734 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6174029240 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6173774386 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 254854 # Number of floating rename lookups
|
||||
system.cpu.fetch.rateDist::total 1150024812 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.232356 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.255700 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 295420546 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 258244912 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 403447600 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 60580020 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 132331734 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2687300913 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 91 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 132331734 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 338940336 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 65400772 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 26776 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 418290403 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 195034791 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2631340951 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 26774 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 78955690 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 100051719 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 2450677508 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 6173942616 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 6173688000 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 254616 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 1023375707 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 3026 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 3017 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 414859907 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 629524588 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 242192886 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 419436220 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 160455315 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2509631781 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 14404 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1981481071 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1143998 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 979086387 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1684803176 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 13851 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1150020807 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.722996 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.682483 # Number of insts issued each cycle
|
||||
system.cpu.rename.UndoneMaps 1023378481 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 2754 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 2753 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 414898876 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 629493820 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 242177233 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 419306187 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 160446985 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2509527923 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 14190 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1981485424 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1148160 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 978984128 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1684574275 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 13637 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1150024812 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.722994 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.682548 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 371533826 32.31% 32.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 234816384 20.42% 52.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 195375201 16.99% 69.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 160336940 13.94% 83.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 104083103 9.05% 92.71% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 52438845 4.56% 97.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 24322326 2.11% 99.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 6470584 0.56% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 643598 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 371543440 32.31% 32.31% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 234819664 20.42% 52.73% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 195395940 16.99% 69.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 160294242 13.94% 83.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 104067895 9.05% 92.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 52467261 4.56% 97.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 24318535 2.11% 99.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 6470621 0.56% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 647214 0.06% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1150020807 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1150024812 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2000225 14.58% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 1998808 14.58% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.58% # attempts to use FU when none available
|
||||
|
|
@ -134,119 +134,119 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.58% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.58% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 9217501 67.18% 81.76% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2502434 18.24% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 9206664 67.16% 81.74% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2503442 18.26% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2582217 0.13% 0.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1339393426 67.60% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.73% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 465725544 23.50% 91.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 173779884 8.77% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2582418 0.13% 0.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1339368351 67.59% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.72% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 465740046 23.50% 91.23% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 173794609 8.77% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 1981481071 # Type of FU issued
|
||||
system.cpu.iq.rate 1.681812 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 13720160 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006924 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 5127845401 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3491473389 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1932208552 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 1706 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 91974 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1992618257 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 757 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 130432763 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iq.FU_type_0::total 1981485424 # Type of FU issued
|
||||
system.cpu.iq.rate 1.681817 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 13708914 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.006919 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 5127851040 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3491267168 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1932205427 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 1694 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 91886 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 39 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1992611169 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 751 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 130415085 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 245422428 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 85551 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 2844514 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 93035934 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 245391660 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 85410 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 2844591 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 93021148 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2121 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2158 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 132342911 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 11594389 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 3099842 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2509646185 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 554822 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 629524588 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 242196119 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 14404 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2636094 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 28755 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 2844514 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 15750968 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2390539 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 18141507 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1946393182 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 456989279 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 35087889 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewSquashCycles 132331734 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 11601856 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 3101094 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2509542113 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 554187 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 629493820 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 242181333 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 14190 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2636658 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 28899 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 2844591 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 15755168 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2389146 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 18144314 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1946393893 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 456999579 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 35091531 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 625199049 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 178040378 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 168209770 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.652031 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1940174750 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1932208592 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1494691214 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2239401377 # num instructions consuming a value
|
||||
system.cpu.iew.exec_refs 625221825 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 178038000 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 168222246 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.652033 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1940172687 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1932205466 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1494674923 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2239381815 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.639992 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.667451 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 1.639990 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.667450 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 980665541 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 980561742 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 16734282 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1017677896 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.502429 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.032638 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 16735567 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1017693078 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.502407 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.032730 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 426781997 41.94% 41.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 262838334 25.83% 67.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 100636861 9.89% 77.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 98086659 9.64% 87.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 37562130 3.69% 90.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 27349053 2.69% 93.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 11151176 1.10% 94.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 9457606 0.93% 95.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 43814080 4.31% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 426815329 41.94% 41.94% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 262847392 25.83% 67.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 100615569 9.89% 77.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 98071508 9.64% 87.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 37557703 3.69% 90.98% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 27347686 2.69% 93.67% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 11159718 1.10% 94.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 9457232 0.93% 95.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 43820941 4.31% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1017677896 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1017693078 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 1528988756 # Number of instructions committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 533262345 # Number of memory references committed
|
||||
|
|
@ -256,48 +256,48 @@ system.cpu.commit.branches 149758588 # Nu
|
|||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 43814080 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 43820941 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3483518113 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5151797552 # The number of ROB writes
|
||||
system.cpu.timesIdled 664618 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 28161255 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 3483422635 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5151578594 # The number of ROB writes
|
||||
system.cpu.timesIdled 664776 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 28156540 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.770563 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.770563 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.770562 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.770562 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.297753 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.297753 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3171957706 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1803005697 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1059979955 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 11725 # number of replacements
|
||||
system.cpu.icache.tagsinuse 992.230576 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 210562208 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 13217 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15931.165015 # Average number of references to valid blocks.
|
||||
system.cpu.int_regfile_reads 3172016251 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1803001798 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 39 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1059991063 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 11761 # number of replacements
|
||||
system.cpu.icache.tagsinuse 991.922218 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 210553808 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 13257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 15882.462699 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 992.230576 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.484488 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 210569056 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 210569056 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 210569056 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 268229 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 268229 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 268229 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 1801320500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1801320500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1801320500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 210837285 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 210837285 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 210837285 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001272 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.001272 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.001272 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6715.606814 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 6715.606814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 6715.606814 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::0 991.922218 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.484337 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 210560945 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 210560945 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 210560945 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 268729 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 268729 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 268729 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 1804643000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1804643000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1804643000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 210829674 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 210829674 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 210829674 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001275 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.001275 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.001275 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6715.475442 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 6715.475442 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 6715.475442 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -306,60 +306,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 8 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 1476 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 1476 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 1476 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 266753 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 266753 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 266753 # number of overall MSHR misses
|
||||
system.cpu.icache.writebacks 10 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 1466 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 1466 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 1466 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 267263 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 267263 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 267263 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 963323500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 963323500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 963323500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 965191000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 965191000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 965191000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001265 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001265 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001265 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3611.293969 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001268 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001268 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001268 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3611.390278 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3611.390278 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3611.390278 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2529482 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4088.837997 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 471282230 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2533578 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 186.014494 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2529381 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4088.837993 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 471314476 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2533477 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 186.034638 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2156497000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4088.837997 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_blocks::0 4088.837993 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.998251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 322424417 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 147507556 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 469931973 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 469931973 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 3022528 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1652645 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 4675173 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 4675173 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 48854788500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 39692091500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 88546880000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 88546880000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 325446945 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_hits 322454983 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 147504907 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 469959890 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 469959890 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 3024204 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1655294 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 4679498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 4679498 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 48898075500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 39778792000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 88676867500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 88676867500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 325479187 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 474607146 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 474607146 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.009287 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011080 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.009851 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.009851 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16163.552000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 24017.312550 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 18939.808217 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 18939.808217 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 474639388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 474639388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.009292 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.011097 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.009859 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.009859 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16168.907752 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 24031.254871 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 18950.081291 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 18950.081291 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -368,75 +368,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 2230911 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1260687 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 634109 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1894796 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1894796 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1761841 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1018536 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2780377 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2780377 # number of overall MSHR misses
|
||||
system.cpu.dcache.writebacks 2230882 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1262448 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 636309 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1898757 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1898757 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1761756 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1018985 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2780741 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2780741 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14865117000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 18574590500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 33439707500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 33439707500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14863304000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 18590602000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 33453906000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 33453906000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005414 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006828 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005858 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005858 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8437.263635 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18236.557667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12027.040757 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12027.040757 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005413 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006831 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005859 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005859 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8436.641623 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18244.235195 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12030.572427 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12030.572427 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 576328 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21485.488039 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3192646 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 595469 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.361565 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 312361641000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7744.786330 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13740.701709 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.236352 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.419333 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1431746 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2230919 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 1301 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 527734 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1959480 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1959480 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 339175 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 252088 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 248002 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 587177 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 587177 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11584401000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 11543000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8495722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20080123000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20080123000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1770921 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2230919 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 253389 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 775736 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2546657 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2546657 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191525 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994866 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.319699 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.230568 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.230568 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34154.642883 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 45.789566 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.667285 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34197.734244 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34197.734244 # average overall miss latency
|
||||
system.cpu.l2cache.replacements 576290 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21486.143377 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3192786 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 595434 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.362116 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 312361724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7744.012474 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13742.130903 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.236329 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.419377 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1431726 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2230892 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 1300 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 527729 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1959455 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1959455 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 339145 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 252556 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 247993 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 587138 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 587138 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11583445500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 11508500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8495413000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20078858500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20078858500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1770871 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2230892 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 253856 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 775722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2546593 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2546593 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191513 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994879 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.319693 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.230558 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.230558 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34154.846747 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 45.568112 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.664503 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34197.852123 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34197.852123 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -445,31 +445,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 412300 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 412302 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 339175 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 252088 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 248002 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 587177 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 587177 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 339145 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 252556 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247993 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 587138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 587138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10515780500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7815593500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7689085500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18204866000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18204866000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10514861000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7830071000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7688785500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18203646500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18203646500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191525 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994866 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319699 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230568 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230568 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.996462 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.433325 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.126983 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191513 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994879 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319693 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230558 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230558 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.027776 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.306197 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.042453 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.033975 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.033975 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
|
|
|
|||
Loading…
Reference in a new issue