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X86: Update stats for in place TLB miss handling.

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This commit is contained in:
Gabe Black 2009-02-25 10:16:29 -08:00
parent 40fdba2454
commit f02df8cb74
24 changed files with 233 additions and 231 deletions
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10
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:00:03
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -44,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 962935342000 because target called exit()
Exiting @ tick 962928676500 because target called exit()

16
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1622364 # Simulator instruction rate (inst/s)
host_mem_usage 197488 # Number of bytes of host memory used
host_seconds 998.15 # Real time elapsed on the host
host_tick_rate 964717823 # Simulator tick rate (ticks/s)
host_inst_rate 977325 # Simulator instruction rate (inst/s)
host_mem_usage 197144 # Number of bytes of host memory used
host_seconds 1656.94 # Real time elapsed on the host
host_tick_rate 581149945 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 0.962935 # Number of seconds simulated
sim_ticks 962935342000 # Number of ticks simulated
sim_seconds 0.962929 # Number of seconds simulated
sim_ticks 962928676500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1925870685 # number of cpu cycles simulated
system.cpu.numCycles 1925857354 # number of cpu cycles simulated
system.cpu.num_insts 1619365942 # Number of instructions executed
system.cpu.num_refs 607160031 # Number of memory references
system.cpu.num_refs 607148814 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:02:02
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -44,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2554098117000 because target called exit()
Exiting @ tick 2554084828000 because target called exit()

40
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1065301 # Simulator instruction rate (inst/s)
host_mem_usage 204932 # Number of bytes of host memory used
host_seconds 1520.10 # Real time elapsed on the host
host_tick_rate 1680214432 # Simulator tick rate (ticks/s)
host_inst_rate 751612 # Simulator instruction rate (inst/s)
host_mem_usage 204588 # Number of bytes of host memory used
host_seconds 2154.53 # Real time elapsed on the host
host_tick_rate 1185451424 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 2.554098 # Number of seconds simulated
sim_ticks 2554098117000 # Number of ticks simulated
sim_seconds 2.554085 # Number of seconds simulated
sim_ticks 2554084828000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency
@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 439707 # number of replacements
system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.609383 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.610676 # Cycle average of tags in use
system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1593417000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 1592465000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 308507 # number of writebacks
system.cpu.icache.ReadReq_accesses 1925870644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 1925857355 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1925869923 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 1925856634 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses
@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms
system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2671109.463245 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 2671091.031900 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1925870644 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 1925857355 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1925869923 # number of demand (read+write) hits
system.cpu.icache.demand_hits 1925856634 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 721 # number of demand (read+write) misses
@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 721 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1925870644 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 1925857355 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1925869923 # number of overall hits
system.cpu.icache.overall_hits 1925856634 # number of overall hits
system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 721 # number of overall misses
@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 658.724449 # Cycle average of tags in use
system.cpu.icache.total_refs 1925869923 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 658.724808 # Cycle average of tags in use
system.cpu.icache.total_refs 1925856634 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 82097 # number of replacements
system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 16428.000401 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 16428.009263 # Cycle average of tags in use
system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61702 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5108196234 # number of cpu cycles simulated
system.cpu.numCycles 5108169656 # number of cpu cycles simulated
system.cpu.num_insts 1619365942 # Number of instructions executed
system.cpu.num_refs 607160031 # Number of memory references
system.cpu.num_refs 607148814 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:06:25
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 165726426000 because target called exit()
Exiting @ tick 164697191500 because target called exit()

16
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1454099 # Simulator instruction rate (inst/s)
host_mem_usage 332016 # Number of bytes of host memory used
host_seconds 185.47 # Real time elapsed on the host
host_tick_rate 893563512 # Simulator tick rate (ticks/s)
host_inst_rate 738696 # Simulator instruction rate (inst/s)
host_mem_usage 331676 # Number of bytes of host memory used
host_seconds 365.09 # Real time elapsed on the host
host_tick_rate 451120089 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.165726 # Number of seconds simulated
sim_ticks 165726426000 # Number of ticks simulated
sim_seconds 0.164697 # Number of seconds simulated
sim_ticks 164697191500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 331452853 # number of cpu cycles simulated
system.cpu.numCycles 329394384 # number of cpu cycles simulated
system.cpu.num_insts 269686773 # Number of instructions executed
system.cpu.num_refs 124054655 # Number of memory references
system.cpu.num_refs 122219131 # Number of memory references
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:06:48
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 495377140000 because target called exit()
Exiting @ tick 493318720000 because target called exit()

40
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 939339 # Simulator instruction rate (inst/s)
host_mem_usage 339456 # Number of bytes of host memory used
host_seconds 287.10 # Real time elapsed on the host
host_tick_rate 1725433923 # Simulator tick rate (ticks/s)
host_inst_rate 472092 # Simulator instruction rate (inst/s)
host_mem_usage 339120 # Number of bytes of host memory used
host_seconds 571.26 # Real time elapsed on the host
host_tick_rate 863564130 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.495377 # Number of seconds simulated
sim_ticks 495377140000 # Number of ticks simulated
sim_seconds 0.493319 # Number of seconds simulated
sim_ticks 493318720000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency
@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 2049944 # number of replacements
system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4078.631489 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4078.561270 # Cycle average of tags in use
system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 165919055000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 165886080000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 229129 # number of writebacks
system.cpu.icache.ReadReq_accesses 331452805 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 329394385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 331451998 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 329393578 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses
@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms
system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 410721.187113 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 408170.480793 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 331452805 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 329394385 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 331451998 # number of demand (read+write) hits
system.cpu.icache.demand_hits 329393578 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_misses 807 # number of demand (read+write) misses
@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 807 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 331452805 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 329394385 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 331451998 # number of overall hits
system.cpu.icache.overall_hits 329393578 # number of overall hits
system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_misses 807 # number of overall misses
@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 666.115369 # Cycle average of tags in use
system.cpu.icache.total_refs 331451998 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 665.896527 # Cycle average of tags in use
system.cpu.icache.total_refs 329393578 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 108885 # number of replacements
system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18052.413380 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 18017.047263 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 70892 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 990754280 # number of cpu cycles simulated
system.cpu.numCycles 986637440 # number of cpu cycles simulated
system.cpu.num_insts 269686773 # Number of instructions executed
system.cpu.num_refs 124054655 # Number of memory references
system.cpu.num_refs 122219131 # Number of memory references
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:09:31
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 868682305500 because target called exit()
Exiting @ tick 868476152500 because target called exit()

16
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1649324 # Simulator instruction rate (inst/s)
host_mem_usage 201208 # Number of bytes of host memory used
host_seconds 906.72 # Real time elapsed on the host
host_tick_rate 958044415 # Simulator tick rate (ticks/s)
host_inst_rate 954040 # Simulator instruction rate (inst/s)
host_mem_usage 200820 # Number of bytes of host memory used
host_seconds 1567.53 # Real time elapsed on the host
host_tick_rate 554042856 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 0.868682 # Number of seconds simulated
sim_ticks 868682305500 # Number of ticks simulated
sim_seconds 0.868476 # Number of seconds simulated
sim_ticks 868476152500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1737364612 # number of cpu cycles simulated
system.cpu.numCycles 1736952306 # number of cpu cycles simulated
system.cpu.num_insts 1495482356 # Number of instructions executed
system.cpu.num_refs 533548971 # Number of memory references
system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:11:36
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 2391369984000 because target called exit()
Exiting @ tick 2390957741000 because target called exit()

42
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1421036 # Simulator instruction rate (inst/s)
host_mem_usage 208620 # Number of bytes of host memory used
host_seconds 1052.39 # Real time elapsed on the host
host_tick_rate 2272325062 # Simulator tick rate (ticks/s)
host_inst_rate 732305 # Simulator instruction rate (inst/s)
host_mem_usage 208264 # Number of bytes of host memory used
host_seconds 2042.16 # Real time elapsed on the host
host_tick_rate 1170799737 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 2.391370 # Number of seconds simulated
sim_ticks 2391369984000 # Number of ticks simulated
sim_seconds 2.390958 # Number of seconds simulated
sim_ticks 2390957741000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4086.149487 # Cycle average of tags in use
system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 12270471000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1463913 # number of writebacks
system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 1736952307 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 1736949494 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms
system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 617472.269463 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 1736952307 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits
system.cpu.icache.demand_hits 1736949494 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 1736952307 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1737361737 # number of overall hits
system.cpu.icache.overall_hits 1736949494 # number of overall hits
system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_misses 2813 # number of overall misses
@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use
system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 873.828248 # Cycle average of tags in use
system.cpu.icache.total_refs 1736949494 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 663512 # number of replacements
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 17171.450430 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 1312958337000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 481430 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4782739968 # number of cpu cycles simulated
system.cpu.numCycles 4781915482 # number of cpu cycles simulated
system.cpu.num_insts 1495482356 # Number of instructions executed
system.cpu.num_refs 533548971 # Number of memory references
system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:15:07
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -29,4 +29,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2835189187500 because target called exit()
Exiting @ tick 2829164056000 because target called exit()

16
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2107205 # Simulator instruction rate (inst/s)
host_mem_usage 197384 # Number of bytes of host memory used
host_seconds 2208.22 # Real time elapsed on the host
host_tick_rate 1283923835 # Simulator tick rate (ticks/s)
host_inst_rate 1367500 # Simulator instruction rate (inst/s)
host_mem_usage 197040 # Number of bytes of host memory used
host_seconds 3402.69 # Real time elapsed on the host
host_tick_rate 831449663 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176258 # Number of instructions simulated
sim_seconds 2.835189 # Number of seconds simulated
sim_ticks 2835189187500 # Number of ticks simulated
sim_seconds 2.829164 # Number of seconds simulated
sim_ticks 2829164056000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5670378376 # number of cpu cycles simulated
system.cpu.numCycles 5658328113 # number of cpu cycles simulated
system.cpu.num_insts 4653176258 # Number of instructions executed
system.cpu.num_refs 1686313781 # Number of memory references
system.cpu.num_refs 1677713078 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:16:41
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:48:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -29,4 +29,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 7645209486000 because target called exit()
Exiting @ tick 7633159262000 because target called exit()

42
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1048991 # Simulator instruction rate (inst/s)
host_mem_usage 204820 # Number of bytes of host memory used
host_seconds 4435.86 # Real time elapsed on the host
host_tick_rate 1723500836 # Simulator tick rate (ticks/s)
host_inst_rate 953941 # Simulator instruction rate (inst/s)
host_mem_usage 204484 # Number of bytes of host memory used
host_seconds 4877.84 # Real time elapsed on the host
host_tick_rate 1564863626 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176258 # Number of instructions simulated
sim_seconds 7.645209 # Number of seconds simulated
sim_ticks 7645209486000 # Number of ticks simulated
sim_seconds 7.633159 # Number of seconds simulated
sim_ticks 7633159262000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 9108982 # number of replacements
system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4084.377593 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 78020119000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244013 # number of writebacks
system.cpu.icache.ReadReq_accesses 5670378338 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5670377663 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 8400559.500741 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5670378338 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.demand_hits 5670377663 # number of demand (read+write) hits
system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5670378338 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5670377663 # number of overall hits
system.cpu.icache.overall_hits 5658327439 # number of overall hits
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 675 # number of overall misses
@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 555.334555 # Cycle average of tags in use
system.cpu.icache.total_refs 5670377663 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use
system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 2772128 # number of replacements
system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25740.146811 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 6038871723000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1199171 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 15290418972 # number of cpu cycles simulated
system.cpu.numCycles 15266318524 # number of cpu cycles simulated
system.cpu.num_insts 4653176258 # Number of instructions executed
system.cpu.num_refs 1686313781 # Number of memory references
system.cpu.num_refs 1677713078 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
---------- End Simulation Statistics ----------

12
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:24:38
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:54:15
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -27,4 +29,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 130009362500 because target called exit()
122 123 124 Exiting @ tick 130009234000 because target called exit()

14
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1349784 # Simulator instruction rate (inst/s)
host_mem_usage 204760 # Number of bytes of host memory used
host_seconds 161.95 # Real time elapsed on the host
host_tick_rate 802781753 # Simulator tick rate (ticks/s)
host_inst_rate 744144 # Simulator instruction rate (inst/s)
host_mem_usage 204416 # Number of bytes of host memory used
host_seconds 293.75 # Real time elapsed on the host
host_tick_rate 442578451 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 218595300 # Number of instructions simulated
sim_seconds 0.130009 # Number of seconds simulated
sim_ticks 130009362500 # Number of ticks simulated
sim_ticks 130009234000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 260018726 # number of cpu cycles simulated
system.cpu.numCycles 260018469 # number of cpu cycles simulated
system.cpu.num_insts 218595300 # Number of instructions executed
system.cpu.num_refs 77165364 # Number of memory references
system.cpu.num_refs 77165298 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:27:21
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:57:42
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
@ -29,4 +29,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 337469692000 because target called exit()
122 123 124 Exiting @ tick 337469588000 because target called exit()

36
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1082313 # Simulator instruction rate (inst/s)
host_mem_usage 212196 # Number of bytes of host memory used
host_seconds 201.97 # Real time elapsed on the host
host_tick_rate 1670883730 # Simulator tick rate (ticks/s)
host_inst_rate 565225 # Simulator instruction rate (inst/s)
host_mem_usage 211860 # Number of bytes of host memory used
host_seconds 386.74 # Real time elapsed on the host
host_tick_rate 872598896 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 218595300 # Number of instructions simulated
sim_seconds 0.337470 # Number of seconds simulated
sim_ticks 337469692000 # Number of ticks simulated
sim_ticks 337469588000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 27 # number of replacements
system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1362.541033 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use
system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2 # number of writebacks
system.cpu.icache.ReadReq_accesses 260018574 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 260013881 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses
@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # ms
system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 55404.619859 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 260018574 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
system.cpu.icache.demand_hits 260013881 # number of demand (read+write) hits
system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses
@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 4693 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 260018574 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 260013881 # number of overall hits
system.cpu.icache.overall_hits 260013777 # number of overall hits
system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
system.cpu.icache.overall_misses 4693 # number of overall misses
@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 2835 # number of replacements
system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1453.991128 # Cycle average of tags in use
system.cpu.icache.total_refs 260013881 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use
system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2031.720476 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 674939384 # number of cpu cycles simulated
system.cpu.numCycles 674939176 # number of cpu cycles simulated
system.cpu.num_insts 218595300 # Number of instructions executed
system.cpu.num_refs 77165364 # Number of memory references
system.cpu.num_refs 77165298 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:19:16
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:59:09
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 5513500 because target called exit()
Exiting @ tick 5484500 because target called exit()

16
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 51320 # Simulator instruction rate (inst/s)
host_mem_usage 193224 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_tick_rate 29796099 # Simulator tick rate (ticks/s)
host_inst_rate 165270 # Simulator instruction rate (inst/s)
host_mem_usage 192880 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 95268287 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 5513500 # Number of ticks simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 5484500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 11028 # number of cpu cycles simulated
system.cpu.numCycles 10970 # number of cpu cycles simulated
system.cpu.num_insts 9484 # Number of instructions executed
system.cpu.num_refs 2003 # Number of memory references
system.cpu.num_refs 1987 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------

10
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:19:16
M5 executing on zizzer
M5 compiled Feb 23 2009 23:45:19
M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
M5 started Feb 23 2009 23:59:10
M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 33842000 because target called exit()
Exiting @ tick 33815000 because target called exit()

48
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 63293 # Simulator instruction rate (inst/s)
host_mem_usage 200624 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_tick_rate 225441997 # Simulator tick rate (ticks/s)
host_inst_rate 184291 # Simulator instruction rate (inst/s)
host_mem_usage 200284 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 654707739 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
sim_ticks 33842000 # Number of ticks simulated
sim_ticks 33815000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 81.592815 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 81.615734 # Cycle average of tags in use
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 10998 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses 10971 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 10770 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 10743 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.020731 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate 0.020782 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.020731 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate 0.020782 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 47.236842 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 47.118421 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 10998 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses 10971 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
system.cpu.icache.demand_hits 10770 # number of demand (read+write) hits
system.cpu.icache.demand_hits 10743 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.020731 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate 0.020782 # miss rate for demand accesses
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.020731 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate 0.020782 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 10998 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses 10971 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 10770 # number of overall hits
system.cpu.icache.overall_hits 10743 # number of overall hits
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.020731 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate 0.020782 # miss rate for overall accesses
system.cpu.icache.overall_misses 228 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.020731 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate 0.020782 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 107.523643 # Cycle average of tags in use
system.cpu.icache.total_refs 10770 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 107.556413 # Cycle average of tags in use
system.cpu.icache.total_refs 10743 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -192,14 +192,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 129.119087 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 129.158632 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 67684 # number of cpu cycles simulated
system.cpu.numCycles 67630 # number of cpu cycles simulated
system.cpu.num_insts 9484 # Number of instructions executed
system.cpu.num_refs 2003 # Number of memory references
system.cpu.num_refs 1987 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------