MOESI Hammer: Update regression test output
This commit is contained in:
Nilay Vaish
parent
70cb16ba14
commit
d272bdb1bf
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@ -9,6 +9,8 @@ time_sync_spin_threshold=100000
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type=System
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children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
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mem_mode=timing
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memories=system.physmem
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num_work_ids=16
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -41,8 +43,8 @@ progress_interval=0
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.ruby.cpu_ruby_ports.port[1]
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icache_port=system.ruby.cpu_ruby_ports.port[0]
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dcache_port=system.l1_cntrl0.sequencer.port[1]
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icache_port=system.l1_cntrl0.sequencer.port[0]
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[system.cpu.dtb]
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type=AlphaTLB
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@ -63,7 +65,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -87,6 +89,7 @@ number_of_TBEs=256
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probeFilter=system.dir_cntrl0.probeFilter
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probe_filter_enabled=false
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recycle_latency=10
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ruby_system=system.ruby
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transitions_per_cycle=32
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version=0
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@ -122,6 +125,7 @@ version=0
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[system.dir_cntrl0.probeFilter]
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type=RubyCache
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assoc=4
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is_icache=false
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latency=1
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replacement_policy=PSEUDO_LRU
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size=1024
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@ -129,9 +133,9 @@ start_index_bit=6
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[system.l1_cntrl0]
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type=L1Cache_Controller
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children=L2cacheMemory
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L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
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L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
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children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
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L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
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L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
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L2cacheMemory=system.l1_cntrl0.L2cacheMemory
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buffer_size=0
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cache_response_latency=10
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@ -141,18 +145,53 @@ l2_cache_hit_latency=10
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no_mig_atomic=true
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number_of_TBEs=256
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recycle_latency=10
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sequencer=system.ruby.cpu_ruby_ports
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ruby_system=system.ruby
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sequencer=system.l1_cntrl0.sequencer
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transitions_per_cycle=32
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version=0
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[system.l1_cntrl0.L1DcacheMemory]
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type=RubyCache
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assoc=2
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is_icache=false
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latency=2
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.l1_cntrl0.L1IcacheMemory]
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type=RubyCache
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assoc=2
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is_icache=true
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latency=2
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.l1_cntrl0.L2cacheMemory]
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type=RubyCache
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assoc=2
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is_icache=false
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latency=10
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replacement_policy=PSEUDO_LRU
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size=512
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start_index_bit=6
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[system.l1_cntrl0.sequencer]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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ruby_system=system.ruby
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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file=
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@ -161,52 +200,18 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.ruby.cpu_ruby_ports.physMemPort
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port=system.l1_cntrl0.sequencer.physMemPort
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[system.ruby]
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type=RubySystem
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children=cpu_ruby_ports network profiler tracer
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children=network profiler tracer
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block_size_bytes=64
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clock=1
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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profiler=system.ruby.profiler
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random_seed=1234
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randomization=false
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stats_filename=ruby.stats
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tracer=system.ruby.tracer
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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children=dcache icache
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access_phys_mem=true
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dcache=system.ruby.cpu_ruby_ports.dcache
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deadlock_threshold=500000
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icache=system.ruby.cpu_ruby_ports.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.ruby.cpu_ruby_ports.dcache]
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type=RubyCache
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assoc=2
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latency=2
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.ruby.cpu_ruby_ports.icache]
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type=RubyCache
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assoc=2
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latency=2
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replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.ruby.network]
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type=SimpleNetwork
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@ -216,6 +221,7 @@ buffer_size=0
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control_msg_size=8
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endpoint_bandwidth=1000
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number_of_virtual_networks=10
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ruby_system=system.ruby
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topology=system.ruby.network.topology
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[system.ruby.network.topology]
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@ -280,8 +286,10 @@ type=RubyProfiler
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all_instructions=false
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hot_lines=false
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num_of_sequencers=1
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ruby_system=system.ruby
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[system.ruby.tracer]
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type=RubyTracer
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ruby_system=system.ruby
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warmup_length=100000
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@ -34,27 +34,27 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Apr/28/2011 15:12:18
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Real time: Jan/10/2012 12:41:50
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.46
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Virtual_time_in_minutes: 0.00766667
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Virtual_time_in_hours: 0.000127778
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Virtual_time_in_days: 5.32407e-06
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Virtual_time_in_seconds: 0.28
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Virtual_time_in_minutes: 0.00466667
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Virtual_time_in_hours: 7.77778e-05
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Virtual_time_in_days: 3.24074e-06
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Ruby_current_time: 208400
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Ruby_start_time: 0
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Ruby_cycles: 208400
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mbytes_resident: 39.1133
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mbytes_total: 221.852
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resident_ratio: 0.176357
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mbytes_resident: 39.0547
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mbytes_total: 234.742
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resident_ratio: 0.166439
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ruby_cycles_executed: [ 208401 ]
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@ -126,8 +126,8 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 11228
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page_faults: 0
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page_reclaims: 10898
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page_faults: 53
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15187
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outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
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Cache Stats: system.ruby.cpu_ruby_ports.icache
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system.ruby.cpu_ruby_ports.icache_total_misses: 646
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system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
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system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
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system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
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system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.L1IcacheMemory
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system.l1_cntrl0.L1IcacheMemory_total_misses: 646
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system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
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system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
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system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
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system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
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system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
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system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
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system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 646 100%
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system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100%
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Cache Stats: system.ruby.cpu_ruby_ports.dcache
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system.ruby.cpu_ruby_ports.dcache_total_misses: 716
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system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
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system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
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system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
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system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.L1DcacheMemory
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system.l1_cntrl0.L1DcacheMemory_total_misses: 716
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system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716
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system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
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system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
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system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
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system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324%
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system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676%
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system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.324%
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system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.676%
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system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 716 100%
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system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 716 100%
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Cache Stats: system.l1_cntrl0.L2cacheMemory
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system.l1_cntrl0.L2cacheMemory_total_misses: 1362
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@ -289,9 +289,9 @@ O NC_DMA_GETS [0 ] 0
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O Invalidate [0 ] 0
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O Flush_line [0 ] 0
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M Load [368 ] 368
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M Ifetch [5833 ] 5833
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M Store [66 ] 66
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M Load [306 ] 306
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M Ifetch [5768 ] 5768
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M Store [60 ] 60
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M L2_Replacement [923 ] 923
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M L1_to_L2 [1061 ] 1061
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M Trigger_L2_to_L1D [68 ] 68
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@ -304,9 +304,9 @@ M NC_DMA_GETS [0 ] 0
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M Invalidate [0 ] 0
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M Flush_line [0 ] 0
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MM Load [397 ] 397
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MM Load [354 ] 354
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MM Ifetch [0 ] 0
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MM Store [641 ] 641
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MM Store [614 ] 614
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MM L2_Replacement [220 ] 220
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MM L1_to_L2 [293 ] 293
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MM Trigger_L2_to_L1D [70 ] 70
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@ -319,6 +319,36 @@ MM NC_DMA_GETS [0 ] 0
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MM Invalidate [0 ] 0
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MM Flush_line [0 ] 0
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IR Load [0 ] 0
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IR Ifetch [0 ] 0
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IR Store [0 ] 0
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IR L1_to_L2 [0 ] 0
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IR Flush_line [0 ] 0
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SR Load [0 ] 0
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SR Ifetch [0 ] 0
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SR Store [0 ] 0
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SR L1_to_L2 [0 ] 0
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SR Flush_line [0 ] 0
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OR Load [0 ] 0
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OR Ifetch [0 ] 0
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OR Store [0 ] 0
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OR L1_to_L2 [0 ] 0
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OR Flush_line [0 ] 0
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MR Load [62 ] 62
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MR Ifetch [65 ] 65
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MR Store [6 ] 6
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MR L1_to_L2 [0 ] 0
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MR Flush_line [0 ] 0
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MMR Load [43 ] 43
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MMR Ifetch [0 ] 0
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MMR Store [27 ] 27
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MMR L1_to_L2 [0 ] 0
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MMR Flush_line [0 ] 0
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IM Load [0 ] 0
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IM Ifetch [0 ] 0
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IM Store [0 ] 0
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@ -468,13 +498,6 @@ IT Store [0 ] 0
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IT L2_Replacement [0 ] 0
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IT L1_to_L2 [0 ] 0
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IT Complete_L2_to_L1 [0 ] 0
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IT Other_GETX [0 ] 0
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IT Other_GETS [0 ] 0
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IT Merged_GETS [0 ] 0
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IT Other_GETS_No_Mig [0 ] 0
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IT NC_DMA_GETS [0 ] 0
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IT Invalidate [0 ] 0
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IT Flush_line [0 ] 0
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ST Load [0 ] 0
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ST Ifetch [0 ] 0
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@ -482,13 +505,6 @@ ST Store [0 ] 0
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ST L2_Replacement [0 ] 0
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ST L1_to_L2 [0 ] 0
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ST Complete_L2_to_L1 [0 ] 0
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ST Other_GETX [0 ] 0
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ST Other_GETS [0 ] 0
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ST Merged_GETS [0 ] 0
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ST Other_GETS_No_Mig [0 ] 0
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ST NC_DMA_GETS [0 ] 0
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ST Invalidate [0 ] 0
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ST Flush_line [0 ] 0
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OT Load [0 ] 0
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OT Ifetch [0 ] 0
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@ -496,13 +512,6 @@ OT Store [0 ] 0
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OT L2_Replacement [0 ] 0
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OT L1_to_L2 [0 ] 0
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OT Complete_L2_to_L1 [0 ] 0
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OT Other_GETX [0 ] 0
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OT Other_GETS [0 ] 0
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OT Merged_GETS [0 ] 0
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OT Other_GETS_No_Mig [0 ] 0
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OT NC_DMA_GETS [0 ] 0
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OT Invalidate [0 ] 0
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OT Flush_line [0 ] 0
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MT Load [0 ] 0
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MT Ifetch [0 ] 0
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@ -510,13 +519,6 @@ MT Store [0 ] 0
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MT L2_Replacement [0 ] 0
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MT L1_to_L2 [0 ] 0
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MT Complete_L2_to_L1 [133 ] 133
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MT Other_GETX [0 ] 0
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MT Other_GETS [0 ] 0
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MT Merged_GETS [0 ] 0
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MT Other_GETS_No_Mig [0 ] 0
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MT NC_DMA_GETS [0 ] 0
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MT Invalidate [0 ] 0
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MT Flush_line [0 ] 0
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MMT Load [0 ] 0
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MMT Ifetch [0 ] 0
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@ -524,13 +526,6 @@ MMT Store [0 ] 0
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MMT L2_Replacement [0 ] 0
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MMT L1_to_L2 [0 ] 0
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MMT Complete_L2_to_L1 [70 ] 70
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MMT Other_GETX [0 ] 0
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MMT Other_GETS [0 ] 0
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MMT Merged_GETS [0 ] 0
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MMT Other_GETS_No_Mig [0 ] 0
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MMT NC_DMA_GETS [0 ] 0
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MMT Invalidate [0 ] 0
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MMT Flush_line [0 ] 0
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MI_F Load [0 ] 0
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MI_F Ifetch [0 ] 0
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@ -974,4 +969,5 @@ NO_F_W Pf_Replacement [0 ] 0
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NO_F_W DMA_READ [0 ] 0
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NO_F_W DMA_WRITE [0 ] 0
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NO_F_W Memory_Data [0 ] 0
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NO_F_W GETF
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NO_F_W GETF [0 ] 0
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@ -1,3 +1,2 @@
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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hack: be nice to actually delete the event here
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@ -1,14 +1,12 @@
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M5 Simulator System
|
||||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 28 2011 15:11:39
|
||||
M5 started Apr 28 2011 15:12:18
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
gem5 compiled Jan 10 2012 12:41:45
|
||||
gem5 started Jan 10 2012 12:41:49
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,66 +1,66 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 38626 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 227180 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_tick_rate 1255686 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 208400 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 9071 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 295192 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240380 # Number of bytes of host memory used
|
||||
host_seconds 0.71 # Real time elapsed on the host
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 208400 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 208400 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 208400 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -41,8 +43,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -63,7 +65,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -87,6 +89,7 @@ number_of_TBEs=256
|
|||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
|
|
@ -122,6 +125,7 @@ version=0
|
|||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
is_icache=false
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
|
|
@ -129,9 +133,9 @@ start_index_bit=6
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
|
|
@ -141,18 +145,53 @@ l2_cache_hit_latency=10
|
|||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
ruby_system=system.ruby
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -161,52 +200,18 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
children=network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.cpu_ruby_ports.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -216,6 +221,7 @@ buffer_size=0
|
|||
control_msg_size=8
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
|
|
@ -280,8 +286,10 @@ type=RubyProfiler
|
|||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
ruby_system=system.ruby
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Apr/28/2011 15:12:18
|
||||
Real time: Jan/10/2012 12:42:00
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.36
|
||||
Virtual_time_in_minutes: 0.006
|
||||
Virtual_time_in_hours: 0.0001
|
||||
Virtual_time_in_days: 4.16667e-06
|
||||
Virtual_time_in_seconds: 0.21
|
||||
Virtual_time_in_minutes: 0.0035
|
||||
Virtual_time_in_hours: 5.83333e-05
|
||||
Virtual_time_in_days: 2.43056e-06
|
||||
|
||||
Ruby_current_time: 78448
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 78448
|
||||
|
||||
mbytes_resident: 37.8359
|
||||
mbytes_total: 220.914
|
||||
resident_ratio: 0.171323
|
||||
mbytes_resident: 37.832
|
||||
mbytes_total: 233.867
|
||||
resident_ratio: 0.161817
|
||||
|
||||
ruby_cycles_executed: [ 78449 ]
|
||||
|
||||
|
|
@ -126,7 +126,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10907
|
||||
page_reclaims: 10644
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15844
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
system.ruby.cpu_ruby_ports.icache_total_misses: 270
|
||||
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
|
||||
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 270
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 270 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100%
|
||||
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 240
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 240
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667%
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 240 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 510
|
||||
|
|
@ -289,9 +289,9 @@ O NC_DMA_GETS [0 ] 0
|
|||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [131 ] 131
|
||||
M Ifetch [2337 ] 2337
|
||||
M Store [36 ] 36
|
||||
M Load [109 ] 109
|
||||
M Ifetch [2315 ] 2315
|
||||
M Store [35 ] 35
|
||||
M L2_Replacement [344 ] 344
|
||||
M L1_to_L2 [397 ] 397
|
||||
M Trigger_L2_to_L1D [23 ] 23
|
||||
|
|
@ -304,9 +304,9 @@ M NC_DMA_GETS [0 ] 0
|
|||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [138 ] 138
|
||||
MM Load [124 ] 124
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [211 ] 211
|
||||
MM Store [201 ] 201
|
||||
MM L2_Replacement [81 ] 81
|
||||
MM L1_to_L2 [105 ] 105
|
||||
MM Trigger_L2_to_L1D [24 ] 24
|
||||
|
|
@ -319,6 +319,36 @@ MM NC_DMA_GETS [0 ] 0
|
|||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IR Load [0 ] 0
|
||||
IR Ifetch [0 ] 0
|
||||
IR Store [0 ] 0
|
||||
IR L1_to_L2 [0 ] 0
|
||||
IR Flush_line [0 ] 0
|
||||
|
||||
SR Load [0 ] 0
|
||||
SR Ifetch [0 ] 0
|
||||
SR Store [0 ] 0
|
||||
SR L1_to_L2 [0 ] 0
|
||||
SR Flush_line [0 ] 0
|
||||
|
||||
OR Load [0 ] 0
|
||||
OR Ifetch [0 ] 0
|
||||
OR Store [0 ] 0
|
||||
OR L1_to_L2 [0 ] 0
|
||||
OR Flush_line [0 ] 0
|
||||
|
||||
MR Load [22 ] 22
|
||||
MR Ifetch [22 ] 22
|
||||
MR Store [1 ] 1
|
||||
MR L1_to_L2 [0 ] 0
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [14 ] 14
|
||||
MMR Ifetch [0 ] 0
|
||||
MMR Store [10 ] 10
|
||||
MMR L1_to_L2 [0 ] 0
|
||||
MMR Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
|
|
@ -468,13 +498,6 @@ IT Store [0 ] 0
|
|||
IT L2_Replacement [0 ] 0
|
||||
IT L1_to_L2 [0 ] 0
|
||||
IT Complete_L2_to_L1 [0 ] 0
|
||||
IT Other_GETX [0 ] 0
|
||||
IT Other_GETS [0 ] 0
|
||||
IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
IT Flush_line [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
|
|
@ -482,13 +505,6 @@ ST Store [0 ] 0
|
|||
ST L2_Replacement [0 ] 0
|
||||
ST L1_to_L2 [0 ] 0
|
||||
ST Complete_L2_to_L1 [0 ] 0
|
||||
ST Other_GETX [0 ] 0
|
||||
ST Other_GETS [0 ] 0
|
||||
ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
ST Flush_line [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
|
|
@ -496,13 +512,6 @@ OT Store [0 ] 0
|
|||
OT L2_Replacement [0 ] 0
|
||||
OT L1_to_L2 [0 ] 0
|
||||
OT Complete_L2_to_L1 [0 ] 0
|
||||
OT Other_GETX [0 ] 0
|
||||
OT Other_GETS [0 ] 0
|
||||
OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
OT Flush_line [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
|
|
@ -510,13 +519,6 @@ MT Store [0 ] 0
|
|||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [0 ] 0
|
||||
MT Complete_L2_to_L1 [45 ] 45
|
||||
MT Other_GETX [0 ] 0
|
||||
MT Other_GETS [0 ] 0
|
||||
MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
MT Flush_line [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
|
|
@ -524,13 +526,6 @@ MMT Store [0 ] 0
|
|||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [0 ] 0
|
||||
MMT Complete_L2_to_L1 [24 ] 24
|
||||
MMT Other_GETX [0 ] 0
|
||||
MMT Other_GETS [0 ] 0
|
||||
MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
MMT Flush_line [0 ] 0
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
|
|
@ -974,4 +969,5 @@ NO_F_W Pf_Replacement [0 ] 0
|
|||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF
|
||||
NO_F_W GETF [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 28 2011 15:11:39
|
||||
M5 started Apr 28 2011 15:12:18
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
gem5 compiled Jan 10 2012 12:41:45
|
||||
gem5 started Jan 10 2012 12:42:00
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,66 +1,66 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 38360 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226220 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 1164850 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000078 # Number of seconds simulated
|
||||
sim_ticks 78448 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
system.cpu.dtb.data_misses 8 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 54765 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1666412 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239484 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 415 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
system.cpu.dtb.data_misses 8 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2586 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 78448 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 78448 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 78448 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.funcmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -204,6 +205,7 @@ version=0
|
|||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
is_icache=false
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
|
|
@ -241,6 +243,7 @@ version=0
|
|||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -249,6 +252,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -257,6 +261,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -299,6 +304,7 @@ version=1
|
|||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -307,6 +313,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -315,6 +322,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl1.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -357,6 +365,7 @@ version=2
|
|||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -365,6 +374,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -373,6 +383,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl2.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -415,6 +426,7 @@ version=3
|
|||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -423,6 +435,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -431,6 +444,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl3.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -473,6 +487,7 @@ version=4
|
|||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -481,6 +496,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -489,6 +505,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl4.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -531,6 +548,7 @@ version=5
|
|||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -539,6 +557,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -547,6 +566,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl5.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -589,6 +609,7 @@ version=6
|
|||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -597,6 +618,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -605,6 +627,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl6.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
@ -647,6 +670,7 @@ version=7
|
|||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -655,6 +679,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -663,6 +688,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl7.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu4: completed 10000 read, 5368 write accesses @1896819
|
||||
system.cpu0: completed 10000 read, 5327 write accesses @1910725
|
||||
system.cpu5: completed 10000 read, 5493 write accesses @1929799
|
||||
system.cpu2: completed 10000 read, 5341 write accesses @1933339
|
||||
system.cpu1: completed 10000 read, 5585 write accesses @1940439
|
||||
system.cpu7: completed 10000 read, 5510 write accesses @1944309
|
||||
system.cpu6: completed 10000 read, 5231 write accesses @1946469
|
||||
system.cpu3: completed 10000 read, 5461 write accesses @1963728
|
||||
system.cpu0: completed 20000 read, 10595 write accesses @3805359
|
||||
system.cpu2: completed 20000 read, 10586 write accesses @3820599
|
||||
system.cpu3: completed 20000 read, 10867 write accesses @3829429
|
||||
system.cpu4: completed 20000 read, 10761 write accesses @3846318
|
||||
system.cpu6: completed 20000 read, 10413 write accesses @3857570
|
||||
system.cpu5: completed 20000 read, 10874 write accesses @3859158
|
||||
system.cpu7: completed 20000 read, 10747 write accesses @3866018
|
||||
system.cpu1: completed 20000 read, 11096 write accesses @3900361
|
||||
system.cpu3: completed 30000 read, 16232 write accesses @5720598
|
||||
system.cpu2: completed 30000 read, 15880 write accesses @5740479
|
||||
system.cpu7: completed 30000 read, 16148 write accesses @5769618
|
||||
system.cpu0: completed 30000 read, 16080 write accesses @5774128
|
||||
system.cpu6: completed 30000 read, 15848 write accesses @5779758
|
||||
system.cpu4: completed 30000 read, 16090 write accesses @5782899
|
||||
system.cpu1: completed 30000 read, 16550 write accesses @5821028
|
||||
system.cpu5: completed 30000 read, 16439 write accesses @5824429
|
||||
system.cpu3: completed 40000 read, 21587 write accesses @7653178
|
||||
system.cpu0: completed 40000 read, 21623 write accesses @7670365
|
||||
system.cpu2: completed 40000 read, 21273 write accesses @7684699
|
||||
system.cpu7: completed 40000 read, 21445 write accesses @7713338
|
||||
system.cpu6: completed 40000 read, 21321 write accesses @7719841
|
||||
system.cpu4: completed 40000 read, 21451 write accesses @7726211
|
||||
system.cpu1: completed 40000 read, 21832 write accesses @7734179
|
||||
system.cpu5: completed 40000 read, 21913 write accesses @7792051
|
||||
system.cpu0: completed 50000 read, 27135 write accesses @9608539
|
||||
system.cpu4: completed 50000 read, 26878 write accesses @9641109
|
||||
system.cpu3: completed 50000 read, 27076 write accesses @9643149
|
||||
system.cpu6: completed 50000 read, 26709 write accesses @9646978
|
||||
system.cpu2: completed 50000 read, 26734 write accesses @9654151
|
||||
system.cpu7: completed 50000 read, 26876 write accesses @9682409
|
||||
system.cpu5: completed 50000 read, 27248 write accesses @9689700
|
||||
system.cpu1: completed 50000 read, 27302 write accesses @9695809
|
||||
system.cpu0: completed 60000 read, 32449 write accesses @11491779
|
||||
system.cpu3: completed 60000 read, 32401 write accesses @11561629
|
||||
system.cpu6: completed 60000 read, 32081 write accesses @11565049
|
||||
system.cpu7: completed 60000 read, 32080 write accesses @11566379
|
||||
system.cpu4: completed 60000 read, 32352 write accesses @11573283
|
||||
system.cpu5: completed 60000 read, 32718 write accesses @11575018
|
||||
system.cpu2: completed 60000 read, 32150 write accesses @11585149
|
||||
system.cpu1: completed 60000 read, 32680 write accesses @11632119
|
||||
system.cpu0: completed 70000 read, 37771 write accesses @13429459
|
||||
system.cpu7: completed 70000 read, 37234 write accesses @13447809
|
||||
system.cpu4: completed 70000 read, 37607 write accesses @13456099
|
||||
system.cpu6: completed 70000 read, 37614 write accesses @13484149
|
||||
system.cpu5: completed 70000 read, 38039 write accesses @13487310
|
||||
system.cpu3: completed 70000 read, 37787 write accesses @13523429
|
||||
system.cpu1: completed 70000 read, 38168 write accesses @13544389
|
||||
system.cpu2: completed 70000 read, 37479 write accesses @13559549
|
||||
system.cpu0: completed 80000 read, 43086 write accesses @15325259
|
||||
system.cpu4: completed 80000 read, 42854 write accesses @15364368
|
||||
system.cpu7: completed 80000 read, 42627 write accesses @15378763
|
||||
system.cpu6: completed 80000 read, 42741 write accesses @15379020
|
||||
system.cpu3: completed 80000 read, 43087 write accesses @15412649
|
||||
system.cpu5: completed 80000 read, 43504 write accesses @15439469
|
||||
system.cpu1: completed 80000 read, 43522 write accesses @15480429
|
||||
system.cpu2: completed 80000 read, 42764 write accesses @15493419
|
||||
system.cpu0: completed 90000 read, 48539 write accesses @17246629
|
||||
system.cpu5: completed 90000 read, 48747 write accesses @17277729
|
||||
system.cpu6: completed 90000 read, 48097 write accesses @17293679
|
||||
system.cpu4: completed 90000 read, 48405 write accesses @17331308
|
||||
system.cpu7: completed 90000 read, 48155 write accesses @17349560
|
||||
system.cpu3: completed 90000 read, 48566 write accesses @17362109
|
||||
system.cpu2: completed 90000 read, 48156 write accesses @17435789
|
||||
system.cpu1: completed 90000 read, 49002 write accesses @17469038
|
||||
system.cpu0: completed 100000 read, 53926 write accesses @19175808
|
||||
system.cpu2: completed 10000 read, 5414 write accesses @1885229
|
||||
system.cpu1: completed 10000 read, 5302 write accesses @1890168
|
||||
system.cpu3: completed 10000 read, 5360 write accesses @1915688
|
||||
system.cpu7: completed 10000 read, 5642 write accesses @1921599
|
||||
system.cpu4: completed 10000 read, 5405 write accesses @1938259
|
||||
system.cpu0: completed 10000 read, 5276 write accesses @1954368
|
||||
system.cpu5: completed 10000 read, 5459 write accesses @1966609
|
||||
system.cpu6: completed 10000 read, 5462 write accesses @1976068
|
||||
system.cpu7: completed 20000 read, 10887 write accesses @3769229
|
||||
system.cpu2: completed 20000 read, 10839 write accesses @3812419
|
||||
system.cpu3: completed 20000 read, 10626 write accesses @3834729
|
||||
system.cpu4: completed 20000 read, 10795 write accesses @3849978
|
||||
system.cpu6: completed 20000 read, 10711 write accesses @3859128
|
||||
system.cpu1: completed 20000 read, 10709 write accesses @3868509
|
||||
system.cpu0: completed 20000 read, 10487 write accesses @3883829
|
||||
system.cpu5: completed 20000 read, 10981 write accesses @3886079
|
||||
system.cpu7: completed 30000 read, 16345 write accesses @5699399
|
||||
system.cpu2: completed 30000 read, 16163 write accesses @5707569
|
||||
system.cpu3: completed 30000 read, 16054 write accesses @5753608
|
||||
system.cpu4: completed 30000 read, 16228 write accesses @5762628
|
||||
system.cpu1: completed 30000 read, 15958 write accesses @5788449
|
||||
system.cpu5: completed 30000 read, 16533 write accesses @5821749
|
||||
system.cpu0: completed 30000 read, 15924 write accesses @5824589
|
||||
system.cpu6: completed 30000 read, 16129 write accesses @5834348
|
||||
system.cpu7: completed 40000 read, 21899 write accesses @7654549
|
||||
system.cpu4: completed 40000 read, 21830 write accesses @7666399
|
||||
system.cpu2: completed 40000 read, 21530 write accesses @7670799
|
||||
system.cpu3: completed 40000 read, 21349 write accesses @7687899
|
||||
system.cpu5: completed 40000 read, 21853 write accesses @7706209
|
||||
system.cpu1: completed 40000 read, 21335 write accesses @7740999
|
||||
system.cpu0: completed 40000 read, 21207 write accesses @7785709
|
||||
system.cpu6: completed 40000 read, 21495 write accesses @7787590
|
||||
system.cpu2: completed 50000 read, 26843 write accesses @9593621
|
||||
system.cpu4: completed 50000 read, 27326 write accesses @9612259
|
||||
system.cpu7: completed 50000 read, 27316 write accesses @9617878
|
||||
system.cpu5: completed 50000 read, 27312 write accesses @9642000
|
||||
system.cpu3: completed 50000 read, 26959 write accesses @9653721
|
||||
system.cpu6: completed 50000 read, 26913 write accesses @9694819
|
||||
system.cpu1: completed 50000 read, 26597 write accesses @9697068
|
||||
system.cpu0: completed 50000 read, 26748 write accesses @9738679
|
||||
system.cpu2: completed 60000 read, 32089 write accesses @11467409
|
||||
system.cpu4: completed 60000 read, 32735 write accesses @11491009
|
||||
system.cpu5: completed 60000 read, 32633 write accesses @11520189
|
||||
system.cpu7: completed 60000 read, 32794 write accesses @11539719
|
||||
system.cpu3: completed 60000 read, 32320 write accesses @11596739
|
||||
system.cpu0: completed 60000 read, 32089 write accesses @11619948
|
||||
system.cpu6: completed 60000 read, 32335 write accesses @11642479
|
||||
system.cpu1: completed 60000 read, 31985 write accesses @11677349
|
||||
system.cpu4: completed 70000 read, 38118 write accesses @13391159
|
||||
system.cpu2: completed 70000 read, 37499 write accesses @13402439
|
||||
system.cpu5: completed 70000 read, 38044 write accesses @13419869
|
||||
system.cpu7: completed 70000 read, 38074 write accesses @13454578
|
||||
system.cpu3: completed 70000 read, 37729 write accesses @13532920
|
||||
system.cpu0: completed 70000 read, 37349 write accesses @13535619
|
||||
system.cpu6: completed 70000 read, 37688 write accesses @13582560
|
||||
system.cpu1: completed 70000 read, 37275 write accesses @13667028
|
||||
system.cpu4: completed 80000 read, 43427 write accesses @15278311
|
||||
system.cpu5: completed 80000 read, 43269 write accesses @15290669
|
||||
system.cpu2: completed 80000 read, 42945 write accesses @15354249
|
||||
system.cpu7: completed 80000 read, 43467 write accesses @15377329
|
||||
system.cpu3: completed 80000 read, 42965 write accesses @15400433
|
||||
system.cpu0: completed 80000 read, 42539 write accesses @15436171
|
||||
system.cpu6: completed 80000 read, 42985 write accesses @15520509
|
||||
system.cpu1: completed 80000 read, 42662 write accesses @15613459
|
||||
system.cpu4: completed 90000 read, 48791 write accesses @17215361
|
||||
system.cpu5: completed 90000 read, 48724 write accesses @17227780
|
||||
system.cpu2: completed 90000 read, 48516 write accesses @17311279
|
||||
system.cpu7: completed 90000 read, 48844 write accesses @17312899
|
||||
system.cpu3: completed 90000 read, 48360 write accesses @17361088
|
||||
system.cpu0: completed 90000 read, 47879 write accesses @17373929
|
||||
system.cpu6: completed 90000 read, 48388 write accesses @17425899
|
||||
system.cpu1: completed 90000 read, 48067 write accesses @17546750
|
||||
system.cpu5: completed 100000 read, 53955 write accesses @19129228
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 1 2011 11:03:29
|
||||
gem5 started Dec 1 2011 11:03:44
|
||||
gem5 executing on SC2B0612
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
gem5 compiled Jan 10 2012 12:41:45
|
||||
gem5 started Jan 10 2012 12:42:10
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19175808 because maximum number of loads reached
|
||||
Exiting @ tick 19129228 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.019176 # Number of seconds simulated
|
||||
sim_ticks 19175808 # Number of ticks simulated
|
||||
sim_seconds 0.019129 # Number of seconds simulated
|
||||
sim_ticks 19129228 # Number of ticks simulated
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 134618 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 381740 # Number of bytes of host memory used
|
||||
host_seconds 142.45 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53926 # number of write accesses completed
|
||||
host_tick_rate 171766 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 371104 # Number of bytes of host memory used
|
||||
host_seconds 111.37 # Real time elapsed on the host
|
||||
system.cpu0.num_reads 99101 # number of read accesses completed
|
||||
system.cpu0.num_writes 52800 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98882 # number of read accesses completed
|
||||
system.cpu1.num_writes 53707 # number of write accesses completed
|
||||
system.cpu1.num_reads 98228 # number of read accesses completed
|
||||
system.cpu1.num_writes 52503 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98977 # number of read accesses completed
|
||||
system.cpu2.num_writes 53060 # number of write accesses completed
|
||||
system.cpu2.num_reads 99319 # number of read accesses completed
|
||||
system.cpu2.num_writes 53658 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99594 # number of read accesses completed
|
||||
system.cpu3.num_writes 53686 # number of write accesses completed
|
||||
system.cpu3.num_reads 99213 # number of read accesses completed
|
||||
system.cpu3.num_writes 53383 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99524 # number of read accesses completed
|
||||
system.cpu4.num_writes 53497 # number of write accesses completed
|
||||
system.cpu4.num_reads 99738 # number of read accesses completed
|
||||
system.cpu4.num_writes 54039 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99742 # number of read accesses completed
|
||||
system.cpu5.num_writes 53984 # number of write accesses completed
|
||||
system.cpu5.num_reads 100000 # number of read accesses completed
|
||||
system.cpu5.num_writes 53955 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99887 # number of read accesses completed
|
||||
system.cpu6.num_writes 53292 # number of write accesses completed
|
||||
system.cpu6.num_reads 98936 # number of read accesses completed
|
||||
system.cpu6.num_writes 53130 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99347 # number of read accesses completed
|
||||
system.cpu7.num_writes 53300 # number of write accesses completed
|
||||
system.cpu7.num_reads 99406 # number of read accesses completed
|
||||
system.cpu7.num_writes 53912 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=dir_cntrl0 l1_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -68,6 +69,7 @@ version=0
|
|||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
is_icache=false
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
|
|
@ -95,6 +97,7 @@ version=0
|
|||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -103,6 +106,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=true
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
|
@ -111,6 +115,7 @@ start_index_bit=6
|
|||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Dec/01/2011 11:03:43
|
||||
Real time: Jan/10/2012 12:44:12
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.46
|
||||
Virtual_time_in_minutes: 0.00766667
|
||||
Virtual_time_in_hours: 0.000127778
|
||||
Virtual_time_in_days: 5.32407e-06
|
||||
Virtual_time_in_seconds: 0.26
|
||||
Virtual_time_in_minutes: 0.00433333
|
||||
Virtual_time_in_hours: 7.22222e-05
|
||||
Virtual_time_in_days: 3.00926e-06
|
||||
|
||||
Ruby_current_time: 208411
|
||||
Ruby_current_time: 213131
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 208411
|
||||
Ruby_cycles: 213131
|
||||
|
||||
mbytes_resident: 37.7227
|
||||
mbytes_total: 242.977
|
||||
resident_ratio: 0.155268
|
||||
mbytes_resident: 35.9023
|
||||
mbytes_total: 232.609
|
||||
resident_ratio: 0.154396
|
||||
|
||||
ruby_cycles_executed: [ 208412 ]
|
||||
ruby_cycles_executed: [ 213132 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -65,17 +65,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 956 average: 15.7887 | standard deviation: 1.16133 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5 75 863 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.7883 | standard deviation: 1.14907 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 82 879 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 6811 count: 941 average: 3500.81 | standard deviation: 1691.94 | 69 9 9 1 10 4 14 20 8 15 4 7 3 4 5 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 7 1 9 8 8 18 13 21 17 21 28 37 31 37 40 46 28 35 31 30 27 28 32 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 6620 count: 49 average: 3597.61 | standard deviation: 1746.75 | 5 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6811 count: 841 average: 3677.95 | standard deviation: 1562.59 | 61 8 4 0 5 4 3 14 3 9 2 3 1 3 5 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 5 1 9 7 8 18 12 20 17 18 28 37 27 35 37 43 27 32 30 29 26 26 31 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1159 count: 51 average: 486.745 | standard deviation: 255.245 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 116 count: 70 average: 16.2571 | standard deviation: 35.3332 | 0 9 16 14 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 4640 count: 34 average: 2534.59 | standard deviation: 1878.68 | 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6811 count: 837 average: 3831.48 | standard deviation: 1383.91 | 0 0 9 1 9 4 14 19 7 15 4 7 2 4 4 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 6 1 8 8 8 16 12 19 17 21 27 36 30 35 39 45 28 35 30 27 27 27 31 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 6858 count: 963 average: 3505.41 | standard deviation: 1666 | 67 16 4 2 10 5 22 17 6 9 5 8 4 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 9 13 24 17 17 29 22 26 32 30 39 37 41 29 39 32 34 28 34 30 27 28 19 18 10 3 7 12 5 7 7 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6253 count: 51 average: 3926.14 | standard deviation: 1480.7 | 3 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6858 count: 863 average: 3652.34 | standard deviation: 1553.9 | 60 13 3 2 7 3 9 13 1 7 0 4 1 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 8 13 21 16 16 26 21 25 32 30 37 35 38 27 38 28 33 28 33 28 23 25 18 18 9 1 7 10 5 7 7 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1022 count: 49 average: 479.796 | standard deviation: 243.565 | 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 114 count: 72 average: 17.4167 | standard deviation: 35.9832 | 0 9 9 12 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 1 2 0 0 1 0 0 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 5339 count: 41 average: 2283.05 | standard deviation: 1908.79 | 5 0 0 6 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6858 count: 850 average: 3859.83 | standard deviation: 1320.43 | 0 0 4 0 10 4 22 15 6 8 5 8 3 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 9 12 23 17 15 27 21 25 31 29 38 35 41 29 39 32 33 28 32 30 27 28 19 18 9 3 7 12 5 7 6 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,14 +85,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 837
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 104 count: 6 average: 19.8333 | standard deviation: 41.248 | 0 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 64 max: 6620 count: 43 average: 4096.84 | standard deviation: 1184.49 | 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 64 average: 15.9219 | standard deviation: 35.0852 | 0 8 16 12 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 4640 count: 31 average: 2779.26 | standard deviation: 1783.63 | 5 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6811 count: 746 average: 4029.46 | standard deviation: 1146.93 | 0 0 4 0 4 4 3 13 2 9 2 3 0 3 4 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 4 1 8 7 8 16 11 18 17 18 27 36 26 33 36 42 27 32 29 26 26 25 30 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 9 count: 3 average: 6.33333 | standard deviation: 3.08221 | 0 0 0 1 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1159 count: 48 average: 516.771 | standard deviation: 231.637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 850
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 103 count: 4 average: 27.75 | standard deviation: 50.183 | 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6253 count: 47 average: 4257.91 | standard deviation: 974.148 | 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 114 count: 66 average: 17.197 | standard deviation: 35.8598 | 0 8 9 11 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 2 0 0 1 0 0 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 5339 count: 37 average: 2523.57 | standard deviation: 1854.34 | 3 0 0 4 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6858 count: 760 average: 4022.97 | standard deviation: 1109.22 | 0 0 3 0 7 2 9 11 1 6 0 4 0 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 8 12 20 16 14 24 20 24 31 29 36 33 38 27 38 28 32 28 31 28 23 25 18 18 8 1 7 10 5 7 6 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 2 average: 4 | standard deviation: 0 | 0 0 0 0 2 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 112 count: 4 average: 58.25 | standard deviation: 60.9289 | 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1022 count: 43 average: 541.14 | standard deviation: 189.677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -124,7 +125,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10661
|
||||
page_reclaims: 10130
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -133,98 +134,98 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 2511 20088
|
||||
total_msg_count_Response_Data: 2511 180792
|
||||
total_msg_count_Writeback_Data: 2248 161856
|
||||
total_msg_count_Writeback_Control: 5220 41760
|
||||
total_msg_count_Unblock_Control: 2506 20048
|
||||
total_msgs: 14996 total_bytes: 424544
|
||||
total_msg_count_Request_Control: 2553 20424
|
||||
total_msg_count_Response_Data: 2550 183600
|
||||
total_msg_count_Writeback_Data: 2292 165024
|
||||
total_msg_count_Writeback_Control: 5291 42328
|
||||
total_msg_count_Unblock_Control: 2546 20368
|
||||
total_msgs: 15232 total_bytes: 431744
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 2.12273
|
||||
links_utilized_percent_switch_0_link_0: 2.00637 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.23909 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.11044
|
||||
links_utilized_percent_switch_0_link_0: 1.9922 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.22868 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 750 54000 [ 0 0 0 0 0 750 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 836 6688 [ 0 0 0 0 0 836 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 0 0 845 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 2.12153
|
||||
links_utilized_percent_switch_1_link_0: 2.23669 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.00637 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.10985
|
||||
links_utilized_percent_switch_1_link_0: 2.2275 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 1.9922 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 850 6800 [ 0 0 850 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 848 6784 [ 0 0 0 0 0 848 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 2.12153
|
||||
links_utilized_percent_switch_2_link_0: 2.00637 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.23669 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 2.11009
|
||||
links_utilized_percent_switch_2_link_0: 1.9922 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.22797 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 51
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 51
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 47
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 51 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 820
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 820
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 846
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 846
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.2439%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.7561%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 820 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 846 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 871
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 871
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 893
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 893
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.93685%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2078%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.85534%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.26316%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.4737%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.26316%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 871 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 893 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [49 ] 49
|
||||
Ifetch [55 ] 55
|
||||
Store [863 ] 863
|
||||
L2_Replacement [830 ] 830
|
||||
L1_to_L2 [15990 ] 15990
|
||||
Trigger_L2_to_L1D [31 ] 31
|
||||
Trigger_L2_to_L1I [3 ] 3
|
||||
Complete_L2_to_L1 [34 ] 34
|
||||
Load [51 ] 51
|
||||
Ifetch [52 ] 52
|
||||
Store [889 ] 889
|
||||
L2_Replacement [845 ] 845
|
||||
L1_to_L2 [15901 ] 15901
|
||||
Trigger_L2_to_L1D [37 ] 37
|
||||
Trigger_L2_to_L1I [4 ] 4
|
||||
Complete_L2_to_L1 [41 ] 41
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
|
|
@ -235,18 +236,18 @@ Ack [0 ] 0
|
|||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [837 ] 837
|
||||
Writeback_Ack [830 ] 830
|
||||
Exclusive_Data [850 ] 850
|
||||
Writeback_Ack [842 ] 842
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [836 ] 836
|
||||
All_acks_no_sharers [850 ] 850
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [43 ] 43
|
||||
I Ifetch [48 ] 48
|
||||
I Store [746 ] 746
|
||||
I Load [47 ] 47
|
||||
I Ifetch [43 ] 43
|
||||
I Store [762 ] 762
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
|
|
@ -288,11 +289,11 @@ O Invalidate [0 ] 0
|
|||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Store [0 ] 0
|
||||
M L2_Replacement [80 ] 80
|
||||
M L1_to_L2 [87 ] 87
|
||||
M Trigger_L2_to_L1D [7 ] 7
|
||||
M L2_Replacement [79 ] 79
|
||||
M L1_to_L2 [88 ] 88
|
||||
M Trigger_L2_to_L1D [9 ] 9
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
|
|
@ -302,13 +303,13 @@ M NC_DMA_GETS [0 ] 0
|
|||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [6 ] 6
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [63 ] 63
|
||||
MM L2_Replacement [750 ] 750
|
||||
MM L1_to_L2 [779 ] 779
|
||||
MM Trigger_L2_to_L1D [24 ] 24
|
||||
MM Trigger_L2_to_L1I [3 ] 3
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [1 ] 1
|
||||
MM Store [65 ] 65
|
||||
MM L2_Replacement [766 ] 766
|
||||
MM L1_to_L2 [800 ] 800
|
||||
MM Trigger_L2_to_L1D [28 ] 28
|
||||
MM Trigger_L2_to_L1I [4 ] 4
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
|
|
@ -337,20 +338,21 @@ OR Flush_line [0 ] 0
|
|||
|
||||
MR Load [0 ] 0
|
||||
MR Ifetch [0 ] 0
|
||||
MR Store [7 ] 7
|
||||
MR L1_to_L2 [52 ] 52
|
||||
MR Store [9 ] 9
|
||||
MR L1_to_L2 [43 ] 43
|
||||
MR Flush_line [0 ] 0
|
||||
|
||||
MMR Load [0 ] 0
|
||||
MMR Ifetch [3 ] 3
|
||||
MMR Store [24 ] 24
|
||||
MMR L1_to_L2 [92 ] 92
|
||||
MMR Ifetch [4 ] 4
|
||||
MMR Store [28 ] 28
|
||||
MMR L1_to_L2 [78 ] 78
|
||||
MMR Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [9590 ] 9590
|
||||
IM L1_to_L2 [9451 ] 9451
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -358,7 +360,7 @@ IM NC_DMA_GETS [0 ] 0
|
|||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [746 ] 746
|
||||
IM Exclusive_Data [760 ] 760
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
|
|
@ -405,7 +407,7 @@ M_W Load [0 ] 0
|
|||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [263 ] 263
|
||||
M_W L1_to_L2 [239 ] 239
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [90 ] 90
|
||||
M_W Flush_line [0 ] 0
|
||||
|
|
@ -414,16 +416,16 @@ MM_W Load [0 ] 0
|
|||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [1 ] 1
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [4391 ] 4391
|
||||
MM_W L1_to_L2 [4486 ] 4486
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [746 ] 746
|
||||
MM_W All_acks_no_sharers [760 ] 760
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [619 ] 619
|
||||
IS L1_to_L2 [611 ] 611
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
|
|
@ -433,7 +435,7 @@ IS Ack [0 ] 0
|
|||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [91 ] 91
|
||||
IS Exclusive_Data [90 ] 90
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
|
|
@ -462,8 +464,8 @@ OI Writeback_Ack [0 ] 0
|
|||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [3 ] 3
|
||||
MI Store [1 ] 1
|
||||
MI Ifetch [1 ] 1
|
||||
MI Store [2 ] 2
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
|
|
@ -472,7 +474,7 @@ MI Merged_GETS [0 ] 0
|
|||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [830 ] 830
|
||||
MI Writeback_Ack [842 ] 842
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
|
|
@ -512,17 +514,17 @@ OT Complete_L2_to_L1 [0 ] 0
|
|||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [2 ] 2
|
||||
MT Store [3 ] 3
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [52 ] 52
|
||||
MT Complete_L2_to_L1 [7 ] 7
|
||||
MT L1_to_L2 [81 ] 81
|
||||
MT Complete_L2_to_L1 [9 ] 9
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [1 ] 1
|
||||
MMT Ifetch [2 ] 2
|
||||
MMT Store [19 ] 19
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [65 ] 65
|
||||
MMT Complete_L2_to_L1 [27 ] 27
|
||||
MMT L1_to_L2 [24 ] 24
|
||||
MMT Complete_L2_to_L1 [32 ] 32
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
|
|
@ -620,42 +622,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
|
|||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1586
|
||||
memory_reads: 837
|
||||
memory_writes: 749
|
||||
memory_refreshes: 435
|
||||
memory_total_request_delays: 1175
|
||||
memory_delays_per_request: 0.740858
|
||||
memory_delays_in_input_queue: 168
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1004
|
||||
memory_stalls_for_bank_busy: 269
|
||||
memory_total_requests: 1614
|
||||
memory_reads: 850
|
||||
memory_writes: 764
|
||||
memory_refreshes: 444
|
||||
memory_total_request_delays: 1136
|
||||
memory_delays_per_request: 0.703841
|
||||
memory_delays_in_input_queue: 148
|
||||
memory_delays_behind_head_of_bank_queue: 4
|
||||
memory_delays_stalled_at_head_of_bank_queue: 984
|
||||
memory_stalls_for_bank_busy: 278
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 76
|
||||
memory_stalls_for_bus: 376
|
||||
memory_stalls_for_arbitration: 71
|
||||
memory_stalls_for_bus: 363
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 160
|
||||
memory_stalls_for_read_read_turnaround: 123
|
||||
accesses_per_bank: 59 53 47 85 75 57 58 40 39 53 46 64 35 48 41 50 42 53 58 54 53 40 32 36 33 45 49 57 36 47 49 52
|
||||
memory_stalls_for_read_write_turnaround: 151
|
||||
memory_stalls_for_read_read_turnaround: 121
|
||||
accesses_per_bank: 44 58 47 90 75 58 58 48 47 49 56 50 32 37 53 44 53 47 48 55 53 40 39 41 34 44 54 59 55 47 50 49
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [747 ] 747
|
||||
GETS [92 ] 92
|
||||
PUT [900 ] 900
|
||||
GETX [760 ] 760
|
||||
GETS [91 ] 91
|
||||
PUT [889 ] 889
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [835 ] 835
|
||||
UnblockM [848 ] 848
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [79 ] 79
|
||||
Writeback_Exclusive_Dirty [749 ] 749
|
||||
Writeback_Exclusive_Clean [78 ] 78
|
||||
Writeback_Exclusive_Dirty [764 ] 764
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [837 ] 837
|
||||
Memory_Ack [749 ] 749
|
||||
Memory_Data [850 ] 850
|
||||
Memory_Ack [763 ] 763
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
|
|
@ -679,7 +681,7 @@ NX GETF [0 ] 0
|
|||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [830 ] 830
|
||||
NO PUT [842 ] 842
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
|
@ -701,8 +703,8 @@ O DMA_READ [0 ] 0
|
|||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [746 ] 746
|
||||
E GETS [91 ] 91
|
||||
E GETX [760 ] 760
|
||||
E GETS [90 ] 90
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
|
|
@ -743,9 +745,9 @@ NO_R GETF [0 ] 0
|
|||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [70 ] 70
|
||||
NO_B PUT [47 ] 47
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [835 ] 835
|
||||
NO_B UnblockM [848 ] 848
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
|
|
@ -799,7 +801,7 @@ NO_B_W UnblockM [0 ] 0
|
|||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [837 ] 837
|
||||
NO_B_W Memory_Data [850 ] 850
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
|
|
@ -920,14 +922,14 @@ O_DR_B All_acks_and_owner_data [0 ] 0
|
|||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [1 ] 1
|
||||
WB GETX [0 ] 0
|
||||
WB GETS [1 ] 1
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [79 ] 79
|
||||
WB Writeback_Exclusive_Dirty [749 ] 749
|
||||
WB Writeback_Exclusive_Clean [78 ] 78
|
||||
WB Writeback_Exclusive_Dirty [764 ] 764
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
|
|
@ -948,7 +950,7 @@ WB_E_W PUT [0 ] 0
|
|||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack [749 ] 749
|
||||
WB_E_W Memory_Ack [763 ] 763
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 1 2011 11:03:29
|
||||
gem5 started Dec 1 2011 11:03:42
|
||||
gem5 executing on SC2B0612
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
gem5 compiled Jan 10 2012 12:41:45
|
||||
gem5 started Jan 10 2012 12:44:12
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 208411 because Ruby Tester completed
|
||||
Exiting @ tick 213131 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 208411 # Number of ticks simulated
|
||||
sim_seconds 0.000213 # Number of seconds simulated
|
||||
sim_ticks 213131 # Number of ticks simulated
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1657766 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248812 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 2251733 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238196 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue